An Analog Floating Gate Memory in a Standard Digital Technology

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An Analog Floating-Gate Memory in a Standard Digital TechnologyTor Sverre Lande ', Htzssan Ranj bar', Moham med Ismai12 and Yngvar Berg'

1 . D e p t . of InfoTmatics, University of Oslo, O S L O , NORWAY2 . Dep t . Elec. Eng . , Ohio State Univ. , USA and on leave at The Helsinki Univ. of Technology, Finland

E-mail: bassenQifi . io .noAbstract

I n t h i s pape r w e p re se n t a s im p le CMOS analogm e m ory s t ruc tu re u s ing the f l oa ting gate o f a M O St ransistor. Th e struc ture is based on a spec ia l but s i m -ple layout which allows significant tunneling at rela-t ive ly low vol tage leve ls . Th e programm ing of the me m -ory is achieved using the standard Fowler-Nordheimtunnel ing and is implemented in a standard digitalCMOS process with only one polysilicon layer . A s i m -ple on-chip memory driver c ircui t i s a lso presented .Experim ental resul ts f r om test chips fabricated in as tandard %m ic ron CM O S process show sia: orders ofmagni tude dynamic range in current for subthresholdoperation.

1: IntroductionA basic functio n offered by a s ingle MO S tran s is tor

is that of an analog memory [12]. Th e ga te vo lt agemay be s tored for many years on the gate capaci tancewhen th e gate terminal i s lef t f loat ing. Float ing-gateMOS t rans is tors are becoming important e lements incontempo rary analog VLSI s ignal process ing. Theyfind application s in areas such as long-term nonvolatiles torage of neural network model parameters 1121-131,on-chip analog trimming [4] 9] and s ignal condi t ioningfor integrated sensors [Ill.

In recent years, a floating-gate MOS t rans is tor istypically fabricated in a s tan da rd or special ized double-poly CM OS process where the f loat ing g ate is the f i rs tpolysilicon layer. In industrial floating-gate system san ultrathin layer of sil icondioxide is used. Severalmethods have been reported for injecting charge onto,or removing charge from a floating gate . One of thebest was presented by C. Diorio [6 ] using tunnel ingto remove charge and hot carrier injection for addingcharge. Th e claimed resolution of more than 14 bit

using only a fewp W of power for programming is tak-ing analog non-volati le m emory anothe r leap forward.Several other reported programm ing devices are us ingtunnel ing injectors in double-poly CMOS process [SI-[13] and fairly high resolution and remarkably long re-tent ion t ime have been demonstrated.The major problem with tunnel ing s t ructures is thehigh (> 2 0 V ) voltage required. High-vo ltage driversare area-consuming and the switching of high voltagesmay affect th e surround ing circuits severly. An alter-native is short-wave UV-light (UV -C) makin g silicon-dioxide slightly conductive without any high voltages111. Besides the inconvenience with short-wave UV-light, optical shielding must be used and the passiva-t ion layer should not ab sorb the UV-l ight (no ni t r ide) .Th e chal lenge of making a versatile analog memory-s t ruc ture in s t and ard d ig i t a l CMOS technology stil l re-mains. Doub le polysilicon mus t be avoided and highvoltages reduced as much as possible. In large ana-log VLSI systems even low-precision analog memorystructures may be a t t ract ive, part icular ly i f they ares imple and occupy a smal l chip area. Furthermore,analog des ign solut ions in s tan dar d digi ta l technologiesshould allow the implementation of low-cost mixed-signal VLSI systems.In this p aper we discuss the implemen tat ion of a sim-ple analog f loat ing gate mem ory based on th e s tandardFowler-Nordheim [7] tunnel ing in a s tandard s ingle-polysilicon (digital) CMOS process . Th e basic s t ruc-ture is discussed first followed by a descrip tion of th eon-chip memory drivers. Th e complete analog mem-ory is then presented together wi th experimental re-sul ts from tes t chips fabricated in a 2-micron CMOSprocess.2: The Analog Memory Structure

The principle of operat ion is the same as reportedearlier by La zzaro et al . [8]and shown in figure 1. T h e

1086-1947196 5.000 1996 EEEProceedings of MicroNeuro '96 271


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Figure1.Two capacitors are connected o thefloating gate. A s indicated there is one coupling capacitor ten times the size of the tunneling capacitor. T I i s a small Ptype readouttransistor, T2 the tunneling structure basedon a N ype transistor while T 3 s a large coupling capacitor realized with Ptype transistorwith source and drain connected to the well.

floating gate of a MO S-transis tor has two f loat ing ca-paci tors connected, one appro xima tely ten t imes th esize of the o ther . Th e smal l capac i tor i s used for tun-neling while th e large one is a boo t s t r ap capac i t o r . Th estandard way of making f loat ing capaci tors in CMOSis done wi th a n ex t ra polysi licon layer . We a re l imi tedt o a single polysil icon layer an d ar e using the cap acito rmade up by t he MO S- t r ans i s to r . T he smal l est capac-i t o r , C,unnel, s where the Fowler-Nordheim tunnel ingtakes p lace. Both adding charge to or removing chargefrom the f loat ing gate i s done through the Ctunnei. h el arge boo t s t r ap capac i t o r , Cleve), omi nat es t he ac t ua lpotent ial of the f loating gate. Th e potent ial on theinput of Cleuelwil l appear on the f loat ing gate scaleddown by the to tal load capaci tance (capaci t ive divi -sion).

Adding charge is simply done by applying a largeposit ive potential over the Ctunnelcapac i t o r ( ' up ' -term inal ) while keeping the 'down'-termina l of theClcur l apaci tor grounded. Removing charge i s sym met-r ic, ie . by rai s ing th e f loat ing gate potent ial throug hth e Clcurl apaci tor ( 'do wn' - term inal ) while keeping theinput s ide of Crunnel rounded .2.1: Tunneling structure

Th e th inne st oxide in a standard digi tal CMOS pro-cess is found in t he g ate of t he M OS- t r ans i s t o r . Car ley[4 ] suggested using the MOS t ransis tor as a t unnel -ing s t ructure . Al though th e nominal tunnel ing vol tageof the gate-active stru ctu re is 25V, t he t wo ex t r acorners in Car ley ' s s t ruc ture are claimed to reduce thetunnel ing vol tage to 17-18V due to field enhan cem ent .More recent results [6 ] indicate no f ield enhancem entdue t o corners s imply because in fabr icat ion al l cornersare rounded . Th e charge t r anspor t t akes p l ace a long

1 h) 1

Figure 2. The tunneling structure is simplya metalpoly contact with a channel underneath or a MOS ransistor with a stacked contact. Phis is an intended violation of thedesign rules lowering the tunnelingvoltage.In a) the silicon structure is shown wherethe small gateactive overlap capacitance ensures charge transport between the floatinggate and the active. In b) the actual layout isshow, whi le the symbo! used is shown is c).

the edge of the polysil icon and increasea l inearly withthe leng th of the edge.In Car ley ' s exper iments a MOS t r ans i s to r wi t h t h e

wel l connected together wi th the source/drain act ivearea i s used. Al though no expe r imen tal resul ts wereshown, Car ley ment ions the rathe r remarkable fact tha tthe wel l -potential d id n ot af fect the tun nel ing mecha-nism of the M OS st ruc ture for voltages less than 20V.Th i s observat ion i s suppor t i ng t he assum pt i on t ha t t hef ield enhancement i s happening along the edges. Themajo r charge t ransp or t goes between the act ive and thepolysil icon ga te due to th e sourc e/drain - gate over lap .Vir tually no charge is t ransp or ted between t he wel l an dt he ga t e .

A close to perfect tunnel ing s t ructure can be madeas a MOS-device in the sub st rate . E l iminat ing the wellmakes the s t ructure smal l wi th v i r tual ly no coupl ingcapac i t ance (on ly t h e sou rce / d ra i n- ate over lap) . Inorder to make our s t ructure as smal l as possible wi thmaximum edge, a ' s tacked contact ' was added on topof the gate. Although th is 'hack' is not al lowed ac-cording to the design-rules , i t i s known to work wi th apossible threshold shift during annealing of the metal-con t ac t s . Th e t unnel i ng s t ruc t u re is shown i n f igu re2 and as shown in figure 3 a l r eady a t 14 - 15V sig-nificant tu nne ling occurs leaving good ma rgins for theest imated breakdown vol tage of 28 V between activeand subs t r a t e . These r esu l t s a r e better t han expec tedand c annot only be explained by the increase poly-edgelength . Disregarding the f ield-enhancement in the cor-ners we end up wi th the s tacked contact as a possibleexplan at ion. T he threshold-shi f t in t roduce d i s actu-

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00

0

Figure 3. The output current as a function ofthe applied voltage over the tunneling structure. A constant programming puls of onesecond duration was used.

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Figure 4. A ratiologic style high voltagedriver is realized in standard digital CMOSwith a Ntype LDD MOS transistor as pulldown and a lateral PNP bipolar transistor aspullup.

ally enhancing our tunneling-str ucture. The se effectsshould be careful ly s tudied, but extend the scope ofthis article.capac itor is implemented by a well-poly

(gate) capacitor w here the well is on the driven side. Asignificant load cap acitanc e is adde d to the driving s ideby the well-substrate capacita nce, bu t the fil teringeffect is attr act ive avoiding silicon dioxide degrad ation.

T h e

3: The high-voltage driversBefore we proceed to the the analog memory ci r-

cuit , we need voltage-drivers giving at least 20V out-put . Lazzaro e t a l . [8]a re us ing both P - type and N-type LDD (Light ly Doped Drain) MOS s t ruc tures in across-quad arrangem ent. We are using a simpler struc-

Figure5. The IV characteristicsof the N ypeLDD MOS.

t u r e as shown in figure 4. As suggested by Lazzarowe are using a pul ldown N-type LDD MOS t rans is torwith the heavy doped drain sub s t i tuted by a l ightlydoped well increasing th e drain resistance of the MOS-transistor. A lightly doped dra in-ma terial will add as ignif icant output-res is tance to the device, but leadsto good high-voltage properties. It is not possible tomake small LDD MOS devices since there is no self-a l ignment . Both theoret ical s tudies and pract ical ex-periments confirm the high-voltage properties of thisL D D MOS s t ructure handl ing 60V without breakingdown [6].

In a digital CM OS process no lightly doped diffusionis available within a well ( th e PBA SE layer in M OSISis not cons idered to be a s ta nda rd feature) . An al ter-nat ive is to apply a la teral PNP bipolar wi th the wel las base and two act ive areas as col lector and emit ter .Al though this s t ructure has a low gain (2 - 4) a n d asignificant base-current, we achieve a resistive pullup-element by applying a suitable base-voltage.

Measured character is t ics of t he N- type LDD MOSare shown in figure 5while the PNP bipolar charac-teristics are shown in figure 6. Although the la teralbipolar is working properly the power consumption ishigher th an des i red through a fairly high base-current.Oth er s t r uctur es us ing wel l -res is tors might be cons id-ered.In figure 7 the output of the high-voltage buffer ismeasured as a function of t h e 5 V input pulse . As ex -pected the switching character is t ics are not excellent(7b and 7c) , but in this context a sloppy flank is desir-able avoiding overshoot and silicondioxide 'wear-out ' .

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3,5 10I I

2 --0 1 5 -

' 2 4 6 8 10 12 14 16 18 20VEC (V )

Figure 6. The I V characteristics of the lateralbipolar.

Figure7. In a) the measured highvoltage output is shown as afunction of a 5V input pulse.In b)and c) the ris ing and falling edges of thehighvol tage pulse are shown.

Iloating-iasFigure8. Th e complete analog memory structure consist of two highvoltage drivers connected to the Ctunnel nd the Cleve[.The readout transistor is a Ptype MOS device with acurrent mirror amplifying the cur rent with afactor of 100.

4:The complete analog memoryAs shown in figure 8the an alog memory ci rcui t con-ta ins two high-voltage drivers connected t o th e Ctunne[and the Cleve,capacitors . Th e s tored an alog value maybe read by a MO S-trans is tor (f loat ing-gate) . In ord erto avoid tunnel ing in the readout t rans is tor , both thesource and th e drain poten t ia ls must be higher thanthe subs tra te vol tage (Gnd) . A well transistor withsource connected to V d d i s adequate and the s toredvol tage may be read out as a current s ink. A typical

working vol tage on the f loat ing gate is appro ximatelyone diode-offset (% 0 . 7 V ) below V d d . In order to shif tthe drain-po tent ia l of the readout t ran s is tor , an ext rabias-transistor is inser ted between reado ut transisto rand the diode-load in the current-m irror . This bias-transistor is also used as a current-limiter when thestored analog value is close to Gnd. T h e o u t p u t ofthe circuit is a current amplif ied w i th a n ampli f icat ionfactor of 100 t h rough the cur ren t -mi rror .Th e programming is 'inverted-digital' with V d d t oboth the ' t une -up ' and the ' t une -down ' knobs as t h einitial state. Applying Gnd t o the ' t une -up ' i nputadd s charge to th e f loating gate whi le apply ing Gnd t othe ' tune-down' input removes charge from the f loat -ing gate . By adding a simple switch to t he d iode inthe current-mirror (see f igure 8) ' the readout currentmy b e ' la tched ' or s tored whi le th e f loating gate is pro-gramm ed. In this way the output-cu rrent is alwaysvalid (a l though samp led).In figure 9both tun ing-up and tun ing-down of t h e

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5: Conclusions

Figure 9. Since the intended application i ssmall currents, programming of the analogmemory is shown for subthreshold currents .One second programming pulses are applied to the knobs. The measurements arescaled down by the amplification actor in thecurrent mirror showing a close to exponentialdependence over six orders of magnitude

ana log memory a re shown. W i th a n es t ima ted po ten-tial of 4 . 3 V o n t h e f l o at in g g a t e t u n i n g u p t h e g a t erequired 17 .5V while tuning down only requiredE 14 .5V . At th e moment th i s a symmet ry i s no t ful lyunders tood. For each applied pulse , th e current wasmeasured showing a close to exponent ia l increase incurrent as a function of the number of pulses applied.The aimed appl icat ion was subthreshold c i rcui ts andas expected we achieved a measured dynamic range ofmore tha n s ix orders in current .

Th e ci rcuit should work properly above threshold aswell . Al though we have not done any experim ents oncharge re tent ion of the f loat ing gate , the thicker gate-oxide compared to the ul t ra thin oxide used in EEP-ROMs should give a charge loss of less than 0.1% inten years [4]. The s tacked contact may reduce the re-tent ion t ime, but this i s not known at t he mom ent ofwri t ing. E ven with a reduced re t en t ion t ime th e mem-ory s t ructure is usable in neural network configura-tions where 'forgetting-dynamics ' is required. Anotherdisadvantage of this s imple memory s t ru ctu re mightbe the low programm ing speed. Fas ter programmingcould be achieved with a higher programming vol tages ince th e tunnel ing current wil l increase exponent ia l lywith th e appl ied vol tage.

A s imple analog f loat ing gate memory is shown towork in s tandard digi ta l CMOS. A novel layout utiliz-in g th e thin gate-oxide between the sourcejdrain di f-fus ion an d the polysi l icon ga te proves a usable tunnel-ing s t ruc ture . High-vol tage drivers are des igned with aLDD MOS pul ldown and a la teral PNP bipolar . Thenew s t ru ctu re should f ind useful appl icat ions in mod ernanalog an d m ixed-s ignal VLSI sys tems.Fu ture work should improve th e high-vol tage driversand inves t igate furthe r the fun dam ental physical mech-anisms involved in th e novel tunn el ing s t ruc ture pre-sented.6: Acknowledgements

Chris Diorio at California Institute of Technologyhas contr ibuted with valuable correct ions and ProfessorCarver Mead at CalTech pointed out th e problem of theleaky metal -contacts and threshold shif t ing. We wouldl ike to th ank the research council of Norway a nd th eOffice of International Affairs (OIA) at T h e O h i o S t a t eUnivers ity for suppo rt ing this work. Also thank s toA. M otamed for his help in preparing t he f inal vers ionof th e paper .References

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An Analog Floating Gate Memory in a Standard Digital Technology