AN 916: JESD204C Intel and ADI AD9081/AD9082 MxFE* …1. JESD204C Intel ® FPGA IP and ADI AD9081/AD9082 MxFE * Hardware Checkout Report for Intel ® Stratix ® 10 E-Tile Devices

AN 916: JESD204C Intel® FPGA IPand ADI AD9081/AD9082 MxFE*Interoperability Report for Intel®Stratix® 10 E-Tile Devices

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Contents

1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware CheckoutReport for Intel® Stratix® 10 E-Tile Devices.............................................................. 31.1. Hardware Requirements......................................................................................... 41.2. Hardware Setup.................................................................................................... 41.3. JESD204C Intel FPGA IP and ADC Hardware Checkout................................................ 6

1.3.1. ADC Hardware Checkout Methodology.......................................................... 61.3.2. JESD204C Intel FPGA IP and ADC Configurations........................................... 91.3.3. ADC Test Results....................................................................................... 91.3.4. ADC Test Result Comment.........................................................................11

1.4. JESD204C Intel FPGA IP and DAC Hardware Checkout.............................................. 111.4.1. DAC Hardware Checkout Methodology........................................................ 111.4.2. JESD204C Intel FPGA IP and DAC Configurations..........................................121.4.3. DAC Test Results......................................................................................131.4.4. DAC Test Result Comment.........................................................................14

1.5. Document Revision History for AN 916: JESD204C Intel FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel Stratix 10 E-Tile Devices.................. 14

1.6. Appendix............................................................................................................ 15

Contents

AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE*Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082MxFE* Hardware Checkout Report for Intel® Stratix® 10E-Tile Devices

The JESD204C Intel® FPGA IP is a high-speed point-to-point serial interfaceintellectual property (IP).

TheJESD204C Intel FPGA IP has been hardware-tested with selected JESD204C-compliant analog-to-digital converter (ADC) and digital-to-analog converter (DAC)device.

This report highlights the interoperability of the JESD204C Intel FPGA IP with theAD9081 MxFE evaluation board AD9081-FMCA-EBZ from Analog Devices. The followingsections describe the hardware checkout methodology and test results. The AD9082MxFE evaluation board is also supported.

The AD9081 MxFE evaluation board is provided by Analog Devices with bring up andconfiguration support from Analog Devices.

The AD9081 and AD9082 are high integration devices with the following features:

• AD9081:

— 16-bit, 12 GSPS maximum sample rate radio frequency (RF) DAC core.

— 12-bit, 4 GSPS rate RF ADC core.

— 16-lane, 24.75 Gbps JESD204C or 15.5 Gbps JESD204B data transceiver port.

— On-chip clock multiplier.

— Digital signal processing capability targeted at single- and dual-band direct-to-RF radio applications.

• AD9082:

— 16-bit, 12 GSPS maximum RF DAC core.

— 12-bit, 6 GSPS rate RF ADC core.

— 16-lane, 24.75 Gbps JESD204C or 15.5 Gbps JESD204B data transceiver port.

— On-chip clock multiplier.

— Digital signal processing capability targeted at multiband direct-to-RF radioapplications.

For more information about the AD9081 and AD9082, refer to AD9081 Datasheet andProduct Info and AD9082 Datasheet and Product Info.

Related Information

• JESD204C Intel FPGA IP User Guide

• AD9081 Datasheet and Product Info

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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

ISO9001:2015Registered

https://www.intel.com/content/www/us/en/programmable/documentation/zom1549251863154.html#exh1550505239571

https://www.analog.com/media/en/technical-documentation/data-sheets/AD9081.pdf


https://www.intel.com/content/www/us/en/quality/intel-iso-registrations.html



• AD9082 Datasheet and Product Info

1.1. Hardware Requirements

The hardware checkout test requires the following hardware and software tools:

• Intel Stratix® 10 TX Signal Integrity (SI) Development Kit (Production Rev BEdition) with Intel Stratix 10 1ST280EY2F55E1VG (transceiver E-tile) device

• Analog Devices AD9081 MxFE AD9081-FMCA-EBZ

• Mini-USB cable

• SMA cables

• Pulse generator

Related Information

Intel Stratix 10 TX Signal Integrity Development Kit

1.2. Hardware Setup

An Intel Stratix 10 TX SI Development Kit (Production Rev B Edition) is used with theAnalog Devices AD9081 daughter card module installed to the FMC+ connector of thedevelopment board.

• The AD9081 EVM derives power from the FMC+ pins.

• The FPGA reference clock is supplied by a pulse generator through an SMA cable.

• The pulse generator provides device clock to the MxFE on the AD9081 EVBthrough an SMA cable.

1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report forIntel® Stratix® 10 E-Tile Devices

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https://www.analog.com/media/en/technical-documentation/data-sheets/AD9082.pdf

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kits-s10-tx-si.html


Figure 1. Hardware Setup

Intel DUT

Intel Stratix 10 TX Signal Integrity Development Kit

FPGA clock from pulse generator

Sampling clock from pulse generator

The following system-level diagram shows how the different modules connect in thisdesign.


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Figure 2. System Diagram

Avalon Streaming[M*N*S*WIDT

H_MULP]

frame_clk

frame_clk

link_clk

mgmt_clk

Intel Stratix 10 TX SIDevelopment Kit

Top-level RTL(intel_j204c_ed_rx_tx.sv) Top-level Platform

Designer System(j204c_rx_tx_ss.qsys)

Intel Stratix 10 Device (1ST280EY2F55E2VG)FMC+

AD9081

Oscillator100 MHz

Avalon Streaming[M*N*S*WIDT

H_MULP]PatternChecker

DAC

ADC

Lane 0 - 7, Lane Rate 24.75 Gbps

global_rst_n

User I/OPBO

JESD204CInterface

PatternGenerator

JESD TXIP Core

JESD RXIP Core

JESD204CIntel FPGA IP

(j204c_rx_tx_ip.qsys)

Core PLL

SPI Master

SMA PortJ3, J4

SMA PortJ30, J32

AD9081 EVM

SMASPI Slave

link_clk

frame_clk

Pulse Generator

device_clk3000 MHz

TransceiverReference Clock

375 MHzCLK1p, CLK1n Si53311 CLKIN

375 MHz

Core PLLReference Clock375 MHz

SMA PortJ1, J2

Si53311

In this setup, where LMF = 882, the data rate of the transceiver lanes is 24.75 Gbps.The pulse generator is used to provide reference clock to the clock generator Si53311.The core PLL reference clock and the transceiver reference clock is generated by theclock generator Si53311.

For FCLK_MULP=2, the core PLL generates 187.5 MHz link clock and 375 MHz frameclock. The pulse generator also provides the AD9081 device clock of 3000 MHz. TheSPI master in the FPGA programs the AD9081 registers through the 4 wire SPIinterfaces via FMC pins. The converters operate in a single JESD link in allconfigurations with a maximum of 8 lanes.

1.3. JESD204C Intel FPGA IP and ADC Hardware Checkout

1.3.1. ADC Hardware Checkout Methodology

The following section describes the test objectives, procedure, and the passingcriteria. The test covers the following areas:

• Receiver data link layer

• Receiver transport layer

1.3.1.1. Receiver Data Link Layer

This test area covers the test cases for sync header alignment (SHA) and extendedmultiblock alignment (EMBA).


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The JESD204C RX IP will start link operation after rx_rst_n is deasserted. In atypical user application, all run-time registers should be configured when the Avalon®

memory-mapped configuration space is out of reset, and before the link and transportlayers are out of reset. Upon rx_rst_n deassertion, the JESD204C RX IP will performSHA and EMB alignment.

1.3.1.1.1. Sync Header Alignment

Table 1. SHA Test Cases

Test Case Objective Description Passing Criteria

SHA.1 Check if Sync HeaderLock is asserted afterthe completion ofreset sequence.

The following signals in<ip_variant_name>_base.v aretapped:• j204c_rx_rst_n

• j204c_rx_sh_lock

• j204c_rx_int

The rxlink_clk is used as the samplingclock for the Signal Tap.

• The j204c_rx_sh_lock isasserted after the deassertion ofj204c_rx_rst_n.

• The j204c_rx_int signal shouldstay low if there is no error.

SHA.2 Check Sync HeaderLock status aftersync header lock isachieved (or duringthe EMBA phase) andstable.

The following signals in<ip_variant_name>_base.v aretapped:• j204c_rx_sh_lock

• j204c_rx_int


• The j204c_rx_sh_lock shouldremain asserted.(1)

• The j204c_rx_int signal shouldstay low if there is no error.(2)

1.3.1.1.2. Extended Multiblock Alignment (EMBA)

Table 2. EMBA Test Cases


EMBA.1 Check if extendedmultiblock lock isasserted only after theassertion of syncheader lock.

The following signals in<ip_variant_name>_base.v are tapped:• j204c_rx_emb_lock

• j204c_rx_int

• The j204c_rx_emb_lock isasserted after assertion ofj204c_rx_sh_lock.


EMBA.2 Check if extendedmultiblock lock statusis stable (afterextended multiblocklock or until elastic

The following signals in<ip_variant_name>_base.v are tapped:• j204c_rx_emb_lock

• j204c_rx_int


• The j204c_rx_emb_lock shouldremain asserted.(3)

• The j204c_rx_int signalshould stay low if there is noerror.

continued...

(1) The j204c_rx_sh_lock signal should remain asserted after 12 hours.

(2) The j204c_rx_int signal should not be asserted after 12 hours.

(3) The j204c_rx_emb_lock signal should remain asserted after 12 hours.


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buffer is released)along with no invalidmultiblock.

EMBA.3 Check the lanealignment.

The following signals in<ip_variant_name>_base.v are tapped:• j204c_rx_dev_lane_align

• j204c_rx_int


• Thej204c_rx_dev_lane_align isasserted after the assertion ofj204c_rx_emb_lock and nextLEMC event.


1.3.1.2. Receiver Transport Layer

To check the data integrity of the data stream through the JESD204C receiver IP coreand transport layer, the ADC is configured to output the ramp test data pattern. TheADC is also set to operate with the same configuration as set in the JESD204C IP core.The ramp checker in the FPGA fabric checks data integrity for 12 hours.

This figure shows the conceptual test setup for data integrity checking.

Figure 3. Data Integrity Check Using RAMP Pattern Checker

Ramp Generator TX Transport Layer

RAMP Checker

RX PHY and Link Layer

RX JESD204C Intel FPGA IP PHY

and Link LayerRX Transport Layer

FPGA

ADC

Table 3. RX Transport Layer Test Cases


RXTL.1 Check the transportlayer mapping of thedata channel usingramp test pattern.

The following signals in<ip_variant_name>_base.v aretapped:• j204c_rx_avst_valid

• j204c_rx_avst_ready

• j204c_rx_avst_data[(M*S*WIDTH_MULP*N)-1:0](4)(5)(6)(7)

• rx_patchk_data_error_int

• The j204c_rx_avst_valid isasserted.

• The j204c_rx_avst_ready isasserted.

• The rx_patchk_data_error_intshould stay low if there is no error.

(4) M is the number of converters.


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The rxframe_clk is used as thesampling clock for the Signal Tap.The rx_patchk_data_error_intsignal indicates a pass or fail for the rampchecker.

1.3.2. JESD204C Intel FPGA IP and ADC Configurations

The JESD204C Intel FPGA IP parameters (L, M, and F) in this hardware checkout arenatively supported by the AD9081 device configuration registers. The transceiver datarate, sampling clock frequency, and other JESD204C parameters comply with theAD9081 operating conditions.

The hardware checkout testing implements the JESD204C Intel FPGA IP with thefollowing parameter configurations.

Global setting for below configuration:

• E = 1

• CF = 0

• FCLK_MULP = 2

• WIDTH_MULP = 4

• Subclass = 0

• SH_CONFIG = CRC-12

• FPGA Management Clock (MHz) = 100

Table 4. Parameter Configuration

Mode LMF N/N’ S E DecimationMode

ADCRate

(Msps)

DataRate

(Msps)(8)

LaneRate

(Mbps)(9)

FPGADeviceClock

(MHz)(10)

FPGALinkClock(MHz)

(11)

FPGAFrameClock(MHz)

(11)

DataPattern

1 882 16 1 1 2x1 3000 1500 24750 375 187.5 375 Ramp

1.3.3. ADC Test Results

The following table contains the possible results and their definition.

(5) S is the number of transmitted samples per converter per frame.

(6) WIDTH_MULP is the data width multiplier between the application and transport layers.

(7) N is the number of conversion bits per converter.

(8) Data rate = ADC rate x decimation factor.

(9) Lane rate = (M/L) x N' x (66/64) x data rate.

(10) The FPGA device clock is used to clock the core PLL and the transceiver.

(11) The link clock and the frame clock are derived from the device clock using the core PLL.


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Table 5. Results Definition

Result Definition

PASS The device under test (DUT) was observed to exhibit conformant behavior.

PASS with comments The DUT was observed to exhibit conformant behavior. However, an additional explanation of thesituation is included (example: due to time limitations, only a portion of the testing wasperformed).

FAIL The DUT was observed to exhibit non-conformant behavior.

Warning The DUT was observed to exhibit behavior that is not recommended.

Refer to comments From the observations, a valid pass or fail could not be determined. An additional explanation ofthe situation is included.

The following table shows the results for test cases SHA.1, SHA.2, EMBA.1, EMBA.2,EMBA.3, and RXTL.1 with subclass 0, and FCLK_MULP = 2.

Table 6. Result for Test Cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, and RXTL.1

Test No. L M F E Lane Rate(Mbps)

ADC Rate(Msps)

Link Clock(MHz)

Result

1 8 8 2 1 24750 3000 187.5 PASS

The following figure shows the Signal Tap waveform of the ramp pattern data receivedat output of FPGA receiver transport layer.

Figure 4. Ramp Data Pattern Diagram

The following figure shows the result of the ramp pattern checker at output data ofFPGA receiver transport layer.

Figure 5. Ramp Pattern Checker Result


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1.3.4. ADC Test Result Comment

In receiver test case, the JESD204C receiver IP core successfully locked at syncheader alignment phase and EMB alignment phase, no data integrity issue is observedby the ramp checker.

1.4. JESD204C Intel FPGA IP and DAC Hardware Checkout

1.4.1. DAC Hardware Checkout Methodology

This section describes the test objectives, procedures, and passing criteria. The testcovers the following areas:

• Transmitter data link layer

• Transmitter transport layer

1.4.1.1. Transmitter Data Link Layer

This test area covers the test cases for tx_rst_n. The JESD204C TX IP will start linkoperation after tx_rst_n is deasserted. In a typical user application, all run-timeregisters should be configured when the Avalon memory-mapped configuration spaceis out of reset, and before the txlink_clk and txframe_clk are out of reset.

1.4.1.1.1. TX_RST

Table 7. TXRST Test Case


TXRST.1 Check if j204c_tx_rst_n isdeasserted after thecompletion of reset sequence.

The following signals in<ip_variant_name>_base.v aretapped:• j204c_tx_rst_n

• j204c_tx_int

The txlink_clk is used as thesampling clock for the Signal Tap.

• The j204c_tx_rst_n isdeasserted after power on.

• The j204c_tx_int signalshould stay low if there is noerror.

• AD9081 0x55E[6:4] statusregister returns 0x6 (LockState) when the register is read.

1.4.1.2. Transmitter Transport Layer

To verify the data integrity of the data stream through the transmitter (TX) JESD204CIntel FPGA IP and transport layer, the DAC JESD core is configured to check the PRBStest pattern that is transmitted from the test pattern generator of the FPGA. PRBSpattern checker is used to check the data integrity of DAC transport layer.

This figure shows the conceptual test setup for data integrity checking.


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Figure 6. Data Integrity Check Using PRBS Pattern Checker

PRBS Generator TX Transport Layer

PRBS Checker

TX JESD204C Intel FPGA IP PHY

and Link Layer

RX PHY and Link Layer

RX Transport Layer

DAC

FPGA

The Signal Tap logic analyzer monitors the operation of the TX transport layer.

Table 8. TX Transport Layer Test Cases


TXTL.1 Check the transport layermapping of the data channelusing PRBS test pattern.

The following signals in<ip_variant_name>_base.v are tapped:• j204c_tx_avst_valid

• j204c_tx_avst_ready

• j204c_tx_avst_data[(M*S*WIDTH_MULP*N)-1:0]

The txframe_clk is used as the samplingclock for the Signal Tap.Check the following in the DAC:• PRBS test status

• Thej204c_tx_avst_validandj204c_tx_avst_readysignals are asserted.

• The PRBS test status inDAC register 0x2064and 0x2065 does notshow an error.

1.4.2. JESD204C Intel FPGA IP and DAC Configurations

The JESD204C Intel FPGA IP parameters (L, M, and F) in this hardware checkout arenatively supported by the AD9081 device configuration registers. The transceiver datarate, sampling clock frequency, and other JESD204C parameters comply with theAD9081 operating conditions.

The hardware checkout testing implements the JESD204C Intel FPGA IP with thefollowing parameter configurations.

Global setting for below configuration:

• E = 1

• CF = 0

• FCLK_MULP = 2

• WIDTH_MULP = 4


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• Subclass = 0

• SH_CONFIG = CRC-12

• FPGA Management Clock (MHz) = 100

Table 9. Parameter Configuration

Mode LMF N/N’ S E InterpolationMode

DACRate

(Msps)

DataRate

(Msps)(12)

LaneRate

(Mbps)(13)

FPGADeviceClock(MHz)

(14)

FPGALinkClock(MHz)

(15)

FPGAFrameClock(MHz)

DataPattern

1 882 16 1 1 2x1 1939.39394

969.69697

16000 242.424242

121.212121

242.424242

PRBS23

1.4.3. DAC Test Results

The following table shows the results for test cases TXRST.1 and TXTL.1 with subclass0 and FCLK_MULP = 2.

Table 10. Result for Test Cases TXRST.1 and TXTL.1

Test No. L M F E Lane Rate (Mbps) DAC Rate (Msps) Link Clock(MHz)

Result

1 8 8 2 1 16000 1939.39394 121.212121 PASS

The following figure shows the Signal Tap waveform of the PRBS pattern datatransmitted to FPGA transmitter transport layer.

Figure 7. PRBS Data Pattern Diagram

The following figure shows the result of the pattern checker at output data of DACtransport layer.

(12) Data rate = DAC rate x interpolation factor.

(13) Lane rate = (M/L) x N' x (66/64) x data rate.

(14) The FPGA device clock is used to clock the core PLL and the transceiver.

(15) The link clock and frame clock are derived from the device clock using the core PLL.


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Figure 8. DAC PRBS Checker Result

1.4.4. DAC Test Result Comment

In transmitter test case, the JESD204C transmitter IP successfully sends PRBS datathrough the transport, link and physical layers. The value of register 0x55E[6:4] is6, which means JESD204C link in DAC is locked, and no data integrity issue isobserved by the DAC PRBS checker.

1.5. Document Revision History for AN 916: JESD204C Intel FPGAIP and ADI AD9081/AD9082 MxFE* Interoperability Report forIntel Stratix 10 E-Tile Devices

DocumentVersion

Changes

2020.06.22 Initial release.


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1.6. Appendix

Device Used and Quartus Tool Version

The Intel Stratix 10 1ST280EY2F55E1VG device (transceiver speed grade -1 device) isused.

Intel Quartus® Prime Pro Edition software version 19.3.0 Build 219 is used forcompilation of designs.

Supported Device Data rate

The MxFE version of the DAC provided was specified to a maximum data rate of 16Gbps while ADC was 24.75 Gbps.

Summary

This report shows validation of the Intel FPGA JESD204C IP core and PHY electricalinterface with the AD9081 or AD9082 devices up to 16 Gbps for DAC and 24.75 Gbpsfor ADC. The complete configuration and hardware setup are shown to provideconfidence in interoperability and performance of the two devices.


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Documents

AN 916: JESD204C Intel and ADI AD9081/AD9082 MxFE* …1. JESD204C Intel ® FPGA IP and ADI AD9081/AD9082 MxFE * Hardware Checkout Report for Intel ® Stratix ® 10 E-Tile Devices