AN 849: Ultra Low Latency Ethernet 10G Reference Design ... · Test Case The simulation test case performs the following steps: 1. Configures the MAC, TX and RX FIFO buffers, and

AN 849: Ultra Low Latency Ethernet10G Reference Design for Intel®Stratix® 10 Devices

Updated for Intel® Quartus® Prime Design Suite: 18.0

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Contents

Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices.............. 3Features..................................................................................................................... 3Hardware and Software Requirements............................................................................ 3Functional Description.................................................................................................. 4

Design Components............................................................................................ 5Clocking and Reset Scheme..................................................................................6

Simulation.................................................................................................................. 6Procedure.......................................................................................................... 6Testbench.......................................................................................................... 7Test Case...........................................................................................................8

Hardware Testing....................................................................................................... 12Hardware Setup................................................................................................12Test Procedure..................................................................................................13

Interface Signals........................................................................................................18Configuration Registers and Status Registers..................................................................19Document Revision History for AN 849: Ultra Low Latency Ethernet 10G Reference

Design for Intel Stratix 10 Devices...................................................................... 22

Contents

AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices2

Ultra Low Latency Ethernet 10G Reference Design forIntel® Stratix® 10 Devices

The Ultra Low Latency Ethernet 10G reference design demonstrates Low Latency 10GEthernet solution for Intel® Stratix® 10 devices.

This Ethernet solution is developed using Low Latency (LL) Ethernet 10G (10GbE)Media Access Controller (MAC) Intel FPGA IP core and Intel Stratix 10 H-tileTransceiver Native PHY with small form-factor pluggable plus (SFP+) transceivermodule. This reference design, which uses 10GBASE-R PHY with IEEE 1588v2 mode, iscapable to achieve a lower round-trip latency, 171.0 nanoseconds (ns) compared to10GBASE-R Ethernet design example for Intel Stratix 10 devices (246.5 ns).

Related Information

Low Latency Ethernet 10G MAC Intel Stratix 10 FPGA IP Design Example User GuideProvides more information on 10GBASE-R Ethernet design example for Intel Stratix10 devices.

Features

• Single-channel LL 10GbE Intel FPGA IP core and Transceiver Native PHY, which isoperating at 10 Gbps.

• 171.0 ns round-trip latency in simulation.

• Support for sequential random burst test in the hardware test and configurablenumber of packets, payload-data pattern, and packet length of each burst.

• Support for Ethernet packet transmission and reception through external SFP+loopback path.

• Support for packet monitoring on both TX and RX data paths.

• Support for packet statistics report on both MAC transmitter (TX) and MACreceiver (RX).

• Support for System Console user interface. Users can make use of this TCL-basedinterface to dynamically configure and monitor any registers in this referencedesign.

Hardware and Software Requirements

The reference design requires and uses the following software and hardware tools:

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Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

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• Software:

— Intel Quartus® Prime Pro Edition software version 18.0

— Platform Designer

— System Console

— ModelSim*-SE simulator version 10.6c

• Hardware:

— Intel Stratix 10 GX H-tile Transceiver Signal Integrity (SI) Development Board(1SG280HU2F50E2VGS1)

— Intel FPGA Download Cable

— SFP+ optical transceiver module, which supports 10GBASE-R

— Fiber optic loopback cable

Related Information

Getting Started with the Design Store

Functional Description

The reference design consists of various components.

Figure 1. System Architecture OverviewThis figure shows the high-level block diagram of the design's system architecture.

Input Clock Reset

Avalon-STAdapterLL 10GbE

MAC

PHY

Transceiver ResetController

TX/RXSerialData

PLL ResetSynchronizer

Design Example

Adapter

Adapter

(altera_eth_10g_mac_base_r)

altera_eth_10g_mac_base_r_wrap

Generated with Platform DesignerGenerated with IP Catalog

S

SAvalon-MM Avalon-MMMasterS M

Address Decoder

FIFO

TrafficController

ATX PLL

Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

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Design Components

Table 1. Design Components

Component Description

LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration:• Speed: 10G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable 10GBASE-R register mode: Selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• TX and RX datapath Reset/Default To Enable: Selected• Use legacy XGMII Interface: Not selected• Use legacy Avalon Memory-Mapped Interface: Selected• Use legacy Ethernet 10G MAC Interfaces: Not selected

PHY The L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP configured for the10GBASE-R protocol. The 10GBASE-R 1588 mode preset sets the PHY's TX FIFO MODEand RX FIFO MODE to Phase Compensation.

Transceiver Reset Controller The Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP core. Resets the transceiver.

Address decoder Decodes the addresses of the components such as traffic controller, LL 10GbE MAC, andPHY.

Reset Synchronizer Synchronizes the reset of all design components.

ATX PLL Generates a TX serial clock for the Intel Stratix 10 10G transceiver.

Adapter A dual clock FIFO adapter, which converts 32-bit Avalon®-ST interface of MAC to 64 bit.

FIFO Avalon Streaming (Avalon-ST) single-clock FIFO, which is used to buffer the RX and TXdata between the MAC IP core and the client

Traffic Controller The traffic controller consists of:• Traffic generator: Generates burst packets to the MAC for transmission.• Traffic monitor: Receives burst packets from MAC.

Related Information

Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for IntelStratix 10 Devices


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Clocking and Reset Scheme

Figure 2. Clocking and Reset SchemeThis figure shows the clocking and reset scheme for this reference design. In this design’s top level, there aretwo external clock sources, ref_clk_clk (644.53125 MHz) and csr_clk (125 MHz). There is one active-lowand asynchronous master reset signal, master_reset_n in the top-level of this reference design. The masterreset signal is used to reset all modules in the reference design.

Generator andChecker

reset_n clk

FIFO

rx_sc_fifo_clk_reset_reset tx_sc_fifo_clk_reset_reset

rx_sc_fifo_clk_clk tx_sc_fifo_clk_clk

Adapteravalon_st_rx_clk_312avalon_st_rx_312_reset_n

avalon_st_tx_clk_312avalon_st_tx_312_reset_n

avalon_st_rx_clk_156avalon_st_rx_156_reset_n

avalon_st_tx_clk_156avalon_st_tx_156_reset_n

LL 10GbE MAC

csr_clkcsr_rst_n rx_rst_n

tx_xcvr_clk

tx_rst_n PHY

reconfig_clkrx_cdr_refclk0reconfig_reset

tx_serial_clktx_clkoutrx_clkout

Address Decodertx_xcvr_half_clk_clksync_tx_half_rst_reset_n

clk_csr_clkcsr_reset_n

rx_xcvr_clk_clksync_rx_rst_reset_n

tx_xcvr_clk_clksync_tx_rst_reset_n

ResetController

reset clock

Synchronizer

fPLL

csr_clk125 MHz

ref_clk_clk644.53125 MHz

master_reset_n

ATX PLL

outclk_div1

tx_serial_clk

rx_xcvr_clk

Simulation

Procedure

1. Download the reference design from Design Store and restore the design usingIntel Quartus Prime software.

2. Launch the Intel Quartus Prime software and open the project file (top.qpf).

3. Before running the design compilation, click Assignments ➤ Settings. SelectAlways regenerate design files for IP cores and Generate IP simulationmodel when generating IP under IP Settings category.

4. To compile the design, click Processing ➤ Start Compilation.

5. Ensure that QUARTUS_ROOTDIR environment variable is pointing to theinstallation path of the Intel Quartus Prime software.

6. Launch the ModelSim-SE 10.6c and change the directory to<project_directory>/simulation/ed_sim/mentor.

7. Run the following command to set up the required libraries, compile the functionalsimulation model, and exercise the simulation model with the provided testbench:

do tb_run.tcl


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Testbench

Figure 3. TestbenchTestbench

Avalon-ST TransmitFrame Generator

Avalon-ST ReceiveFrame Generator

avalon_bfm_wrapper.sv

Avalon Driver

LL 10GbE MAC PHY

Ethernet PacketMonitor

Ethernet PacketMonitor

XGMII

TX Data

RX Data

Serialloopback

DUT

Avalon-MMControl Register

Table 2. Component Description


Device under test (DUT) Components of the design that is tested in this simulation. This DUT consists ofMAC and PHY.

Avalon driver Consists of Avalon-ST master bus functional models (BFMs). This driver formsthe TX and RX paths. This driver also provides access to the Avalon-MM interfaceof the DUT.

Ethernet Packet Monitor Monitors TX and RX datapaths, and displays the frames in the simulator console.

Table 3. Testbench File DescriptionsThe testbench files below are needed to perform the simulation and these files are located in<project_directory>/simulation/ed_sim/models.


avalon_bfm_wrapper.sv Wrapper for Avalon BFM that is used by the Avalon_driver.sv.

avalon_driver.sv SystemVerilog HDL driver that uses the BFMs to form the transmit and receivepath and access the Avalon-MM interface.

avalon_if_param_pkg.sv SystemVerilog HDL testbench that contains parameters to configure the BFMs.The configuration is specific to DUT. As such, the content of this file should notbe changed.

avalon_st_eth_packet_monitor.sv

SystemVerilog HDL testbench that monitors the Avalon-ST transmit and receiveinterfaces.

eth_register_map_params_pkg.sv

SystemVerilog HDL package that maps addresses to Avalon-MM control registers.

default_test_params_pkg.sv SystemVerilog HDL package that defines the test parameters for MACconfiguration and Ethernet packet generation.

eth_mac_framce.sv SystemVerilog HDL testbench that handles the creation of Ethernet framecontent.

continued...


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tb_run.tcl TCL scripts that starts a simulation session of the DUT and other logic blocks.

tb_top.sv Top-level testbench file that consists of the DUT and other logic blocks.

wave.do Signal tracing macro script that the ModelSim simulator uses to displaytestbench signals.

Test Case

The simulation test case performs the following steps:

1. Configures the MAC, TX and RX FIFO buffers, and Ethernet packet generator.

2. Ethernet packet generator generates and transmits 32 packets with 66 bytes andrandom payload to the Avalon-ST TX path.

3. Waits until all the packets are loopback and received on Avalon-ST RX path.

4. At the end of the simulation, the transcript window displays the number of goodand bad packets, which monitored by Ethernet packet monitor (refer to Figure 4on page 9), and the values of the MAC statistic counters (refer to Figure 5 onpage 10 and Figure 6 on page 11). The transcript window also displays"Simulation PASSED" if all statistics error counters are zero and the RX MACstatistics counters are equal to the TX MAC statistics counters.

Note: The simulation of this design requires approximately 404800 ns tocomplete.

5. In the simulation waveform window (refer to Figure 7 on page 11), themeasurement cursors indicates the roundtrip latency for serial loopback to showthat time taken to transmit the first data from Avalon-ST TX datapath to theAvalon-ST RX datapath.


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Figure 4. Status of Ethernet Packet Monitor


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Figure 5. TX Statistics Counter


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Figure 6. RX Statistics Counter

Figure 7. Simulation Waveform

Latency value


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Hardware Testing

Related Information

Getting Started with the Design Store

Hardware Setup

Before you run the design, you need to set up the development board as shown in thefollowing figures:

Figure 8. SFP+ External Loopback Hardware Test Setup

Intel Stratix 10 Transceiver Signal Integrity Development Board

JTAG TAPController

SystemController

Ethernet Frame Generation& Monitoring (Master) Ethernet Channel 0

Ethernet Frame Generation& Monitoring (Slave)

Ethernet Channel 1

Ethernet Frame Generation& Monitoring Ethernet Channel n - 1

Ethernet Frame Generation& Monitoring

Ethernet Channel n

Intel Stratix 10 FPGA

Intel SystemConsole

Software

PC

(1)

(2)

(1)(2)

Use this type of loopback to test IEEE 1588v2 features.Use this type of loopback to test features other than IEEE 1588v2. This loopback is different than the loopback usedfor simulating multiple channels.


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Figure 9. SFP+ External Loopback Hardware Test Setup in Lab

SFP+ transceiver module and optical loopback cable

master_reset_nblock_lock_ntx_ready_export_n

rx_ready_export_natx_pll_locked_n

core_pll_locked_n

Test Procedure

1. Download the reference design from Design Store and restore the design usingIntel Quartus Prime software.

2. Launch the Intel Quartus Prime software and open the project file (top.qpf).

3. Before running the design compilation, go to Assignments ➤ Settings. Under IPSettings category, select Always regenerate design files for IP cores andGenerate IP simulation model when generating IP.

4. Click Processing ➤ Start Compilation to compile the design.

Note: You may experience timing violations after running compilation for thedesign. To resolve these timing violations, you must launch the DesignSpace Explorer II in the Intel Quartus Prime software (Tools ➤ DesignSpace Explorer II) and perform seed sweep to get the best quality of fit.

5. After the design is compiled successfully, a programming file (top.sof) isgenerated and located in <project_directory/output_files>.

6. Set up the Intel Stratix 10 GX H-Tile Signal Integrity (SI) Development Board.

a. Connect the programming cable to the JTAG connection port (CN1).

b. Connect the board to the power supply input (J103).

c. Connect the 10G SFP+ transceiver module along with optical loopback cable toSFP+ port (J29).

7. In the Intel Quartus Prime software, select Tools ➤ Programmer to launch theprogrammer.


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8. Configure the Intel Stratix 10 GX H-Tile SI development board using the generatedprogramming file (altera_eth_top.sof).

9. Reset the Ethernet design by using the push button (USER_PB0).

Note: The design must be reset whenever you begin a new test.

10. In the Intel Quartus Prime software, click Tools ➤ System Debugging Tools andlaunch the system console.

11. In the System Console command shell, change the directory toproject_directory/hwtesting/system_console.

You can now run the predefined hardware tests using the provided test commandslisted in Table 4 on page 14.

Table 4. Test Command

Test Case Test Command Description

SFP+ external loopback source gen_conf.tcl The generator generates and sends about 100 000 packetswith random bytes (maximum packet length = 1518 bytes).Wait 1 minutes for it to complete its tasks.

sourcemonitor_conf.tcl

The monitor checks the number of good and bad packetsreceived.

source show_stats.tcl This script displays the values of the statistics counters

Avalon-ST reverse loopback sourceloopback_conf.tcl

This command enables the Avalon-ST loopback. This test isused with an external tester such as Spirent tester

The following diagrams show excerpts of the output, which shows that the Ethernetpacket generator configuration, the Ethernet packet monitor status, and the TX andRX statistics counters.


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Figure 10. Sample Test Output—Ethernet Packet Generator Configuration

100000 packets generated inAvalon-ST TX interface (TX client)

Figure 11. Sample Test Output—Ethernet Packet Monitor Status

100000 packets generated inAvalon-ST RX interface (RX client)


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Figure 12. Sample Test Output—TX Statistics Counter

100000 packets transmittedon MAC TX datapath without errors


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Figure 13. Sample Test Output—RX Statistics Counter

100000 packets transmittedon MAC RX datapath without errors


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Interface Signals

Table 5. Clock and Reset Signals

Signal Direction Width Description

clk_clk Input 1 Configuration clock for the Avalon-MM interfaceand core logics. Frequency is 125 MHz.

ref_clk_clk Input 1 Reference clock for the ATX PLL and fPLL.Frequency is 644.53125 MHz.

tx_xcvr_clk Output 1 322.265625 MHz clock for the TX datapath. Thisclock is output from tx_clkout of PHY.

rx_xcvr_clk Output 1 322.265625 MHz clock for the RX datapath. Thisclock is output from rx_clkout of PHY.

outclk_div1 Output 1 161.1328125 MHz clock for components such asaddress decoder, traffic controller, FIFO, andadapter. This clock is generated from fPLL.

tx_serial_clk Output 1 The high-speed serial clock generated by the ATXPLL that drives the Native PHY. Frequency is5.15625 GHz.

rx_cdr_refclk0 Input 1 The reference clock source for PHY’s RX CDR PLL.This clock is sourced from ref_clk_clk.

master_reset_n Input 1 Assert this asynchronous and active-low signal toreset the whole design example.

csr_rst_n Input 1 Active-low reset signal for the Avalon-MM interface.

tx_rst_n Input 1 Active-low reset signal for the TX datapath.

rx_rst_n Input 1 Active-low reset signal for the RX datapath.

Table 6. Avalon-MM Interface Signals

Signal Direction Description

csr_write

avl_mm_write

Input Assert this signal to request a write.

csr_read

avl_mm_read

Input Assert this signal to request a read.

csr_address

avl_mm_baddress

Input Use this bus to specify the register address you want toread from or write to.

csr_readdata

avl_mm_readdata

Output Carries the data read from the specified register.

csr_writedata

avl_mm_writedata

Input Carries the data to be written to the specified register.

csr_waitrequest

avl_mm_waitrequest

Output Asserted when IP core is busy and not ready to accept anyread or write request.

Table 7. PHY Interface Signals


rx_serial_data Input 1 RX serial input data to PHY.

tx_serial_data Output 1 TX serial input data from PHY.


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Table 8. Status Signals


block_lock Output 1 Asserted when the link synchronization issuccessful.

rx_ready_export Output 1 Asserted when the RX channel is ready for datatransmission.

tx_ready_export Output 1 Asserted when the TX channel is ready for datatransmission.

atx_pll_locked Output 1 Asserted when the TX PLL is locked.

core_pll_locked Output 1 Asserted when the fPLL is locked.

Related Information

• Low Latency Ethernet 10G MAC Intel FPGA IP User GuideDescribes the interface signals of the Low Latency Ethernet 10G MAC IntelFPGA IP core.

• Intel Stratix 10 L- and H-Tile Transceiver PHY User GuideDescribes the interface signals of the Stratix 10 H-Tile Transceiver PHY.

Configuration Registers and Status Registers

Table 9. System Register Map

Base Address Block

0x0000_0000 LL 10GbE Intel FPGA IP core

0x0000_8000 L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP

0x0000_d400 RX SC FIFO

0x0000_d600 TX SC FIFO

0x0000_0C00 Traffic Controller

Table 10. Traffic Controller Configuration Registers Map

Byte Offset Name Width R/W HW ResetValue

Description

0x00 number_packet 32 RW 0x00 Used to specify the number ofpackets to be generated.

0x04 random_length 32 RW 0x00 Specifies the type of packetlength.• Bit [0]—0 or 1

— 0 = fixed length— 1 = random length

• Bit [31:1]—Reserved

0x08 randam_payload 32 RW 0x00 Specifies the data pattern forthe packet.• Bit [0]—0 or 1

— 0 = incremental datapattern

— 1 = random datapattern

• Bit [31:1]—Reserved

continued...


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Description

0x14 source_addr0 32 RW 0x00 Used to specify 6-bytes sourceor destination MAC address.source_addr0/destination_addr0 = lastfour bytes of the address• Bits [15:0] of source_

addr1/destination_addr1—first two bytes of theaddress

• Bits [31:16] of source_addr1/destination_addr1—unused

• For example, if the sourceMAC address is00-1C-23-17- 4A-CB, youget the followingassignments:— source_addr0 =

0x17231C00— source_addr1 =

0x0000CB4A

0x18 source_addr1 32 RW 0x00

0x01C destination_addr0 32 RW 0x00

0x020 destination_addr1 32 RW 0x00

0x024 packet_tx_count 32 RO 0x00 This register keeps track thenumber of packets that thegenerator transmittedsuccessfully. This registerclears if the packet generationis triggered.

0x028 rand_seed0 32 RW 0x5EED0000 • The lower 32 bits of therandom seed.

• Occupies bits 31:0 of thePBRS generator when youset the data pattern torandom (Setrandom_payload registerto 1).

0x02C rand_seed1 32 RW 0x5EED0001 • The middle 32 bits of therandom seed.


0x030 rand_seed2 32 RW 0x00025EED • The upper 32 bits of therandom seed.


continued...


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Description

0x034 pkt_length 32 RW 0x00 • Bits [13:0]—Specifies thefixed packet length and thevalid values are between 24to 9600 bytes. It isapplicable only when youset the random_lengthregister to 0.

• Bit [31:14]—Reserved.

0x400 number_packet 32 RO 0x00 Total number of packets thatthe monitor expects to receive.

0x404 good_pkts 32 RO 0x00 Total number of received goodpackets.

0x408 bad_pkts 32 RO 0x00 Total number of receivedpackets with errors.

0x40C byte_rx_count_0 32 RO 0x00 • 64-bit counter that keepstrack of the total number ofbytes received.

• byte_rx_count_0represents the lower 32bits.

• byte_rx_count_1represents the upper 32bits.

• Read byte_rx_count_0followed bybyte_rx_count_1 in thesubsequent cycle to get anaccurate count.

0x410 byte_rx_count_1 32 RO 0x00

0x414 cycle_rx_count_0 32 RO 0x00 • 64-bit counter that keepstrack of the total number ofcycles the monitor takes toreceive all packets.

• cycle_rx_count_0represents the lower 32bits.

• cycle_rx_count_1represents the upper 32bits.

• Read cycle_rx_count_0followed bycycle_rx_count_1 in thesubsequent cycle to get anaccurate count.

continued...


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Description

0x418 cycle_rx_count_1 32 RO 0x00

0x41C mon_csr 32 RW/RO 0x00 • Bit 0—Set this bit to 1 totrigger packets reception.This bit clears after packetreception is started.

• Bit 2—A value of 1 indicatesthat the packet monitor hasreceived the total numberof packets specified in thenumber_packet register.

• Bit 3—A value of 1 indicatesthat the current packetreceived by monitor hasCRC error.

• Bits [9:4]—Receive errorstatus. The behavior ofrx_err signal in LowLatency Ethernet 10G MACIntel FPGA IP core ismapped to this register.

• Bits [31:10]—Reserved

0x800 avalon_st_loopback_ena 32 RW 0x00 Bit 0 – Set this bit to 1 toenable loopback betweenAvalon-ST TX interface andAvalon-ST RX interface intraffic controller.

Related Information

Low Latency Ethernet 10G MAC Intel FPGA IP User GuideDescribes the MAC configuration register space of the Low Latency Ethernet 10GMAC Intel FPGA IP core.

Document Revision History for AN 849: Ultra Low Latency Ethernet10G Reference Design for Intel Stratix 10 Devices

Document Version Intel QuartusPrime Version

Changes

2018.06.12 18.0 Initial release.


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Documents

AN 849: Ultra Low Latency Ethernet 10G Reference Design ... · Test Case The simulation test case performs the following steps: 1. Configures the MAC, TX and RX FIFO buffers, and