Alveo U50 Data Center Accelerator Card User Guide - Xilinx · 2019-12-18 · V i v a d o D e s i g n F l o w. This section provides a starting point for expert HDL developers using

Alveo U50 Data CenterAccelerator Card

User Guide

UG1371 (v1.2) December 18, 2019

https://www.xilinx.com

Revision HistoryThe following table shows the revision history for this document.

Section Revision Summary12/18/2019 Version 1.2

Card Features Added a note about HBM pseudo channels.

FPGA Configuration Updated the clock rate for FPGA_CCLK.

UltraScale+ FPGA Added a note about HBM pseudo channels.

Maintenance Connector Interface Added a tip about the Alveo Programming Cable.

SFP-DD Module Connectors Added a note about the supported interfaces.

Status LEDs Updated the tables and added a new table.

10/31/2019 Version 1.1

General updates. Updated to the Vitis unified software platform throughout.

Chapter 1: Introduction • Removed HBM2 bandwidth from first paragraph.• Updated figure.• Updated description of card interfaces.

Card Features • Removed bullets about HBM2 memory.• Added note about power rails.

Board Support Files for the Alveo U50 Card Added link for Xilinx Board Store to introductory paragraph.

Card Power System • Updated paragraph with power rail information.• Added tip about monitoring power system telemetry.

Appendix B: Regulatory and Compliance Information Added safety, EMC, and other compliance information.

09/10/2019 Version 1.0.1

General updates. Editorial updates only. No technical content updates.

08/02/2019 Version 1.0

Initial release N/A

Revision History

UG1371 (v1.2) December 18, 2019 www.xilinx.comAlveo U50 Accelerator Card User Guide 2Send Feedback


https://www.xilinx.com/about/feedback/document-feedback.html?docType=User_Guides&docId=UG1371&Title=Alveo%20U50%20Data%20Center%20Accelerator%20Card&releaseVersion=1.2&docPage=2

Table of ContentsRevision History...............................................................................................................2

Chapter 1: Introduction.............................................................................................. 5Card Features...............................................................................................................................7Block Diagram..............................................................................................................................7Design Flows................................................................................................................................ 9

Chapter 2: Vivado Design Flow..............................................................................10Board Support Files for the Alveo U50 Card.......................................................................... 10Creating an RTL Project Based on the U50 Board File.......................................................... 11Creating an MCS File and Programming the Alveo Card..................................................... 12

Chapter 3: Card Installation and Configuration......................................... 14Standard ESD Measures........................................................................................................... 14Installing Alveo Data Center Accelerator Cards in Server Chassis......................................15FPGA Configuration...................................................................................................................15

Chapter 4: Card Component Description........................................................ 16UltraScale+ FPGA....................................................................................................................... 16Quad SPI Flash Memory........................................................................................................... 16Maintenance Connector Interface.......................................................................................... 17PCI Express Endpoint................................................................................................................17SFP-DD Module Connectors.....................................................................................................18I2C Bus........................................................................................................................................18Status LEDs.................................................................................................................................18Card Power System................................................................................................................... 19

Appendix A: Xilinx Design Constraints (XDC) File...................................... 21

Appendix B: Regulatory and Compliance Information........................... 22Safety Compliance.....................................................................................................................22EMC Compliance........................................................................................................................22CE Directives.............................................................................................................................. 23




CE Standards..............................................................................................................................23Compliance Markings............................................................................................................... 24Other Compliance Statements................................................................................................ 24

Appendix C: Additional Resources and Legal Notices............................. 28Xilinx Resources.........................................................................................................................28Documentation Navigator and Design Hubs.........................................................................28References..................................................................................................................................28Please Read: Important Legal Notices................................................................................... 30




Chapter 1

IntroductionThe Xilinx® Alveo™ U50 Data Center accelerator cards are peripheral component interconnectexpress (PCIe®) Gen3 x16 compliant and Gen4 x8 compatible cards featuring the Xilinx 16 nmUltraScale+™ technology. The Alveo U50 card offers 8 GB of HBM2 to provide high-performance, adaptable acceleration for memory-bound, compute-intensive applicationsincluding database, analytics, and machine learning inference.

The following table lists the specifications for the engineering sample (ES3) and production (PQ)versions of the Alveo U50 accelerator cards.

Table 1: Alveo Card Specifications

Specification ES3 Version PQ VersionProduct SKU A-U50DD-P00G-ES3-G A-U50-P00G-PQ-G

Network interface 2xSFP-DD 1XQSFP

Qualified for deployment No Yes




The Alveo™ U50 card is available in a passive cooling configuration only and is designed forinstallation into a data center server where controlled air flow provides direct cooling to the card.The following figure shows the Alveo U50 accelerator card with half-height bracket installed. Thecard includes the following interfaces:

1. A PCI Express® card connector.

2. One QSFP interface.

Note: For ES3 cards, two SFP-DD interfaces are available.

3. Maintenance Connector.

Figure 1: Alveo U50 Data Center Accelerator Card

Maintenance Connector

QSFP28Interface

PCIe Connector

X22929-101519

CAUTION! Alveo accelerator cards are designed to be installed into a data center server, where controlled airflow provides direct cooling. If the cooling enclosure is removed from the card and the card is powered-up,external fan cooling airflow MUST be applied to prevent over-temperature shut-down and possible damage tothe card electronics. Removing the cooling enclosure voids the board warranty.

See Appendix C: Additional Resources and Legal Notices for references to documents, files, andresources relevant to the Alveo U50 accelerator cards.

Chapter 1: Introduction




Card FeaturesThe Alveo U50 accelerator card features are listed below. Detailed information for each feature isprovided in Chapter 4: Card Component Description.

• UltraScale+™ XCU50 FPGA

• Two 4 gigabyte (GB) HBM memory stacks (8 GB total)

○ 32 channels of 256 MB

Note: The xilinx_u50_xdma_201920_2 platform allows a maximum of 30 of the 32 available HBMpseudo channels to be used. Using more will generate errors during hardware build. Xilinxrecommends using pseudo-channels 0:29 because pseudo channels 30 and 31 need to route acrossfabric resources shared with the static region possibly resulting in lower performance.

• One gigabit (Gb) quad SPI flash memory for configuration

• Ethernet networking interfaces

○ Two SFP-DD connectors support 4x10/25 GbE (ES3 card)

○ One QSFP28 connector supporting 100 GbE, 40 GbE, or 4x10/25 GbE (PQ card)

• JTAG and UART access through the maintenance connector

• 16-lane integrated Endpoint block for PCI Express connectivity

○ Gen3 x16 supporting to x1, x2, x4, x8, x16 lane configurations

○ Single or dual Gen4 x8

• I2C bus

• Status LEDs

• Power management with system management bus (SMBus) voltage, current, and temperaturemonitoring

• 75W PCIe slot power only

Note: The Alveo U50 card has separate power rails for FPGA fabric and HBM memory. Developers mustensure their designs do not draw too much power for each rail. More information can be found in theKnown Issues table of the Alveo U50 Data Center Accelerator Card Installation Guide (UG1370).

Block DiagramBlock diagrams of the Alveo U50 card with two SFP-DD interfaces (ES3 card) and one QSFPinterface (PQ card) are shown in the following figures.



https://www.xilinx.com/cgi-bin/docs/bkdoc?k=accelerator-cards;d=ug1370-u50-installation.pdf



Figure 2: Card Block Diagram with SFP-DD Interface

XilinxXCU50

QSPI

SatelliteController

HBM4 GB

U50

GTY x4

EP GTY x16

Single QSPIConfig Flash

HBM4 GB

UART

PCIe(Gen3 x16 or two Gen4 x8)

SFP-DD2x 25 Gb/s

SFP-DD2x 25 Gb/s

SMBus

X22932-072919

Figure 3: Card Block Diagram with QSFP Interface

XilinxXCU50

QSPI

SatelliteController

HBM4 GB

U50

GTY x4

EP GTY x16

Single QSPIConfig Flash

HBM4 GB

UART

PCIe(Gen3 x16 or two Gen4 x8)

QSFP284 GTY

SMBus

100 GbE40 GbE4x 10 GbE

X22939-072919





Design FlowsThe preferred optimal design flow for targeting the Alveo Data Center accelerator card uses theVitis™ unified software platform. However, traditional design flows, such as RTL or HLx are alsosupported using the Vivado® Design Suite tools. The following figure shows a summary of thedesign flows.

Figure 4: Alveo Data Center Accelerator Card Design Flows

High complexity

Slowest

High

Simplicity

Time to Market

Hardware Expertise Required

Complexity abstracted

Fastest

Low

RTL Flow HLx Flow (IP integrator)

Traditional Flows

Target Platform

Vitis

X22272-020419

Requirements for the different design flows are listed in the following table.

Table 2: Requirements to Get Started with Alveo Data Center Accelerator Card DesignFlows

RTL Flow HLx Flow VitisFlow documentation UG9491 UG8952 UG14163

Vivado tools support Board support XDC Board support XDC N/A

Programming the FPGA Vivado Hardware Manager Vivado Hardware Manager UG13704

Notes:1. UltraFast Design Methodology Guide for the Vivado Design Suite (UG949).2. Vivado Design Suite User Guide: System-Level Design Entry (UG895). See “Using the Vivado Design Suite Platform Board

Flow” in Chapter 2 and Appendix A.3. Vitis Accelerated Flow in the Vitis Unified Software Platform Documentation (UG1416).4. Alveo U50 Data Center Accelerator Card Installation Guide (UG1370).



https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug949-vivado-design-methodology.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug895-vivado-system-level-design-entry.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?t=vitis+doc;v=2019.2;d=kme1569523964461.html




Chapter 2

Vivado Design FlowThis section provides a starting point for expert HDL developers using the RTL flows, ordevelopers who want to customize in HLx beyond the standard support in the Vivado® tools.

Board Support Files for the Alveo U50 CardPrior to creating an RTL project based on the Alveo™ U50 card, update the board supportrepository to include the Alveo U50 card by following the steps listed below. Board support filescan also be downloaded from the Xilinx Board Store.

1. Launch Vivado tools.

2. Download the latest board files by selecting Tools → Download Latest Boards….

3. Click Download in the Download Latest Boards dialog box. This will download all the latestboard support files including those for the Alveo U50 card. The download may take severalminutes to complete.

Chapter 2: Vivado Design Flow


https://github.com/Xilinx/XilinxBoardStore/tree/2019.1/boards/Xilinx



Creating an RTL Project Based on the U50Board File

For designers using RTL flow, use the following steps to create an RTL project using the U50board file.

1. Launch Vivado tools.

2. Create a new project by clicking on File → Project → New. Click Next.

3. Add a project name and click Next.

4. Select RTL Project as the Project Type and click Next.

5. Within the Default Part window, select Boards and enter u50 in the search tab. Select theU50 card and click Next as shown in the following figure.

This will create a new RTL project based on the Alveo U50 accelerator card.





Creating an MCS File and Programming theAlveo Card

For custom RTL flow, this section outlines the procedures to do the following:

• Create an MCS file (PROM image)

• Flash program through the maintenance connector

Create an MCS File (PROM Image)

To ensure that the PROM image is successfully loaded onto the Alveo accelerator card at poweron, the starting address must be set to 0x01002000 and the interface set to spix4 whencreating the MCS file. Details on adding this to the MCS file can be found in the UltraScaleArchitecture Configuration User Guide (UG570).

The Alveo accelerator card's Quad SPI configuration flash memory contains a protected region,with the factory base image at the 0x00000000 address space. This base image points to thecustomer programmable region at a 0x01002000 address space offset.

In addition, the following code must be placed in the project XDC file to correctly configure theMCS file.

# Bitstream Configuration# ------------------------------------------------------------------------set_property CONFIG_VOLTAGE 1.8 [current_design]set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]set_property CONFIG_MODE SPIx4 [current_design]set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]# ------------------------------------------------------------------------

Once the XDC file has been updated, generate the MCS file using the following command (notethe quotations are required):

write_cfgmem -force -format mcs -interface spix4 -size 1024 -loadbit "up 0x01002000<input_file.bit>" -file "<output_file.mcs>"

Where:

• <input_file.bit> is the filename of the input .bit file

• <output_file.mcs> is the MCS output filename



https://www.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug570-ultrascale-configuration.pdf



Program the Alveo Card

After the MCS file is created, use the following steps to flash the Alveo Data Center acceleratorcard using the Vivado hardware manager through the debug and maintenance board (DMB).Details on connecting to the Alveo card through the maintenance connector are provided in theAlveo Programming Cable User Guide (UG1377). Detailed steps for programming the FPGA areoutlined in the chapter Programming the FPGA Device in the Vivado Design Suite User Guide:Programming and Debugging (UG908).

RECOMMENDED: Programming through JTAG maintenance port must be from a separate machine to avoidPCIe downlink causing the server to reboot during programming. Alternatively, the PCIe link can be manuallydisabled through software and rescanned after programming is complete.

1. Connect to the Alveo U50 Data Center accelerator card using the Vivado hardware managerthrough the DMB.

2. Select Add Configuration Device and select the mt25qu01g-spi-x1_x2_x4 part.

3. Right-click the target to select Program the Configuration Memory Device.

a. Select the MCS file target.

b. Select Configuration File Only.

c. Click OK.

4. After programming has completed, disconnect the card in the hardware manager, anddisconnect the USB cable from the Alveo accelerator card.

5. Perform a cold reboot on the host machine to complete the card update.

IMPORTANT! If you are switching between an Alveo Data Center accelerator card target platform and acustom design, revert the card to the golden image before loading an alternate image into the PROM. See AlveoU50 Data Center Accelerator Card Installation Guide (UG1370) for more information.



https://www.xilinx.com/cgi-bin/docs/bkdoc?k=accelerator-cards;d=ug1377-alveo-programming-cable-user-guide.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug908-vivado-programming-debugging.pdf




Chapter 3

Card Installation and Configuration

Standard ESD MeasuresCAUTION! ESD can damage electronic components when they are improperly handled, and can result in totalor intermittent failures. Always follow ESD-prevention procedures when removing and replacing components.

To prevent ESD damage:

• Attach a wrist strap to an unpainted metal surface of your hardware to prevent electrostaticdischarge from damaging your hardware.

• When you are using a wrist strap, follow all electrical safety procedures. A wrist strap is forstatic control. It does not increase or decrease your risk of receiving electric shock when youare using or working on electrical equipment.

• If you do not have a wrist strap, before you remove the product from ESD packaging andinstalling or replacing hardware, touch an unpainted metal surface of the system for aminimum of five seconds.

• Do not remove the device from the antistatic bag until you are ready to install the device inthe system.

• With the device still in its antistatic bag, touch it to the metal frame of the system.

• Grasp cards and boards by the edges. Avoid touching the components and gold connectors onthe adapter.

• If you need to lay the device down while it is out of the antistatic bag, lay it on the antistaticbag. Before you pick it up again, touch the antistatic bag and the metal frame of the system atthe same time.

• Handle the devices carefully to prevent permanent damage.

Chapter 3: Card Installation and Configuration




Installing Alveo Data Center AcceleratorCards in Server Chassis

For hardware and software installation procedures, see the Alveo U50 Data Center AcceleratorCard Installation Guide (UG1370).

Because each server or PC vendor's hardware is different, for physical board installationguidance, see the manufacturer’s PCI Express® board installation instructions.

FPGA ConfigurationThe Alveo U50 accelerator card supports two UltraScale+™ FPGA configuration modes:

• Quad SPI flash memory

• JTAG (through maintenance port)

The FPGA bank 0 mode pins are hardwired to M[2:0] = 001 master SPI mode with pull-up/downresistors.

At power up, the FPGA is configured by the QSPI NOR flash device (MicronMT25QU01GBB8E12-0SIT) with the FPGA_CCLK operating at a clock rate of up to 85 MHzusing the master serial configuration mode.

If the JTAG cable is plugged in, QSPI configuration might not occur. JTAG mode is alwaysavailable independent of the mode pin settings.

For complete details on configuring the FPGA, see the UltraScale Architecture Configuration UserGuide (UG570).

Table 3: Configuration Modes

Configuration Mode M[2:0] Bus Width CCLK DirectionMaster SPI 001 x1, x2, x4 FPGA output

JTAG Not applicable – JTAG overrides x1 Not applicable

Chapter 3: Card Installation and Configuration






Chapter 4

Card Component DescriptionThis chapter provides a functional description of the components of the Alveo™ U50 DataCenter accelerator card.

UltraScale+ FPGAThe Alveo U50 accelerator card is populated with the 16 nm UltraScale+™ XCU50 FPGA.

This UltraScale+ HBM device incorporates two 4 GB high-bandwidth memory (HBM) stacksadjacent to the device die. Using SSI technology, the device communicates to the HBM stacksthrough memory controllers that connect through the silicon interposer at the bottom of thedevice. Each XCU50 FPGA contains two 4 GB HBM stacks, resulting in up to 8 GB of HBM perdevice. The device includes 32 HBM AXI interfaces used to communicate with the HBM. Theflexible addressing feature that is provided by a built-in switch allows for any of the 32 HBM AXIinterfaces to access any memory address on either one or both of the HBM stacks. This flexibleconnection between the device and the HBM stacks is helpful for floorplanning and timingclosure.

Note: The xilinx_u50_xdma_201920_2 platform allows a maximum of 30 of the 32 available HBM pseudochannels to be used. Using more will generate errors during hardware build. Xilinx recommends usingpseudo-channels 0:29 because pseudo channels 30 and 31 need to route across fabric resources sharedwith the static region possibly resulting in lower performance.

Quad SPI Flash MemoryThe Quad SPI device provides 1 Gb of nonvolatile storage.

• Part number: MT25QU01GBBB8E12-0AAT (Micron)

• Supply voltage: 1.8V

• Datapath width: 4 bits

• Data rate: variable

Chapter 4: Card Component Description




For configuration details, see the UltraScale Architecture Configuration User Guide (UG570). Thedetailed FPGA and Flash pin connections for the feature described in this section aredocumented in the Alveo U50 accelerator card XDC file, referenced in Appendix A: Xilinx DesignConstraints (XDC) File.

Maintenance Connector InterfaceThe Alveo U50 accelerator card provides access to the FPGA through the JTAG interface using adebug and maintenance board (DMB) connected to the 30-pin maintenance connector. Theconnector pinout supports three UART debug interfaces: PMBus, FPGA JTAG, and satellitecontroller JTAG. The following figure shows the maintenance connector interface. For moreinformation, see Alveo Programming Cable User Guide (UG1377).

Figure 5: Maintenance Connector

MaintenanceConnector

2x15

SatelliteControllerMSP432

JTAG1

SC_UART_RXD/TXD

FPGA_TXD/RXD_MSP

XLT

XLT

Control from SC

JTAG0

UART0

X22955-072919

XCU50FPGA

TIP: The Alveo Programming Cable is not provided with the U50 (QSFP) production card. This cable can bepurchased at the following link: https://www.xilinx.com/products/boards-and-kits/alveo/accessories.html.

PCI Express EndpointThe Alveo U50 accelerator card implements a 16-lane PCI Express edge connector that performsdata transfers at the rate of 2.5 giga-transfers per second (GT/s) for Gen1, 5.0 GT/s for Gen2, 8.0GT/s for Gen3 applications, and 16.0 GT/s for Gen4 applications.





https://www.xilinx.com/products/boards-and-kits/alveo/accessories.html



The detailed FPGA connections for this feature are documented in the Alveo U50 acceleratorcard Xilinx Design Constraints (XDC) file, referenced in Appendix A: Xilinx Design Constraints(XDC) File.

SFP-DD Module ConnectorsThe Alveo U50 accelerator cards host two small form-factor pluggable (SFP-DD) connectors thataccept an array of optical modules. Each connector is housed within a single cage assembly andare accessible through the I2C interface.

Access from the FPGA to SFP-DD modules and support for miscellaneous SFP-DD signals isprovided through the satellite controller. For more information about the SFP-DD module, see SFP-DD Specification.

• MGTREFCLK0 is from SI5394 with programmable output frequencies

• Maximum SFP-DD power is 3.5W per port

• The target for SFP-DD channel length is 4 inches maximum

Note: The Alveo U50 card that includes one QSFP interface is production qualified for deployment. TheAlveo U50DD ES3 card that supports two SFP-DD interfaces is not recommended for deployment.

Detailed FPGA connections for this feature are documented in the Alveo U50 accelerator cardXDC file, referenced in Appendix A: Xilinx Design Constraints (XDC) File.

I2C BusThe Alveo U50 accelerator cards implement an I2C bus network.

Status LEDsThe U50 has two set of LEDs:

1. Card status LEDs

2. Ethernet status LEDs

Card status LEDs are visible through a cutout in the PCIe end bracket and are defined in thefollowing table. Production cards will not have board status LEDs.



http://sfp-dd.com/specification/



Table 4: Card Status LEDs

Reference DesignatorDescription

ES ProductionDS1 When FPGA is configured, LED is blue, otherwise it remains Off

DS2 System healthy when green1 Not populated

DS3 Warning or alarm when orange1 Not populated

DS4 Power fault when red Not populated

Notes:1. Functionality is not yet defined.

Ethernet status LEDs are located on the top-left, front panel above the SFP-DD modules. TheLED definitions are given in the following tables.

Table 5: ES Ethernet Status LEDs

Reference Designator DescriptionSFPDD_0_ACT Dedicated to Activity and is only green1

SFPDD_0_STA Dedicated to Link and is yellow/green1

SFPDD_1_ACT Dedicated to Activity and is only green1

SFPDD_1_STA Dedicated to Link and is yellow/green1


Table 6: PQ Ethernet Status LEDs

Reference DescriptionQSFP_0_ACT Dedicated to Activity and is only green1

QSFP_0_STA Dedicated to Link and is yellow/green1


Card Power SystemThe Alveo U50 card has separate power rails for FPGA fabric and HBM memory. Developersmust ensure their designs do not draw too much power for each rail. More information can befound in the Known Issues table of the Alveo U50 Data Center Accelerator Card Installation Guide(UG1370). To monitor, limited power system telemetry is available through the I2C IP. I2C IP isinstantiated during the FPGA design process which begins after the Alveo Data Centeraccelerator card is selected from the Vivado Design Suite Boards tab. Refer to Design Flows formore information.






TIP: For accelerated flows, you can use xbutil query to monitor power system telemetry.





Appendix A

Xilinx Design Constraints (XDC) FileRTL users can reference the Vivado Design Suite User Guide: Using Constraints (UG903) for moreinformation. The Alveo accelerator card XDC files are available for download from theirrespective websites along with this user guide.

Note: Bitstream constraints are not available for download because they are user-generated.


https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug903-vivado-using-constraints.pdf



Appendix B

Regulatory and ComplianceInformation

This product is designed and tested to conform to the European Union directives and standardsdescribed in this section.

Safety ComplianceThe following table shows the safety standards that apply to the Alveo U50 and U50DD cards.

Table 7: Safety Standards

Safety Standard Alveo U50 Alveo U50DDIEC 62368-1:2014 (Second Edition) ✓ ✓CSA C22.2 No. 60950-1-07, 2nd Edition, 2014-10-14 (Information Technology Equipment- Safety - Part 1: General Requirements)

✓

EN 60950-1:2006+A11:2009+A1:2012+A12:2011+A2:2013 (European Union) ✓IEC 60950-1:2005 (2nd Edition); Am 1:2009 (International) ✓EU LVD Directive 2014/35/EC ✓ ✓

EMC ComplianceThe following tables show the EMC standards that apply to the Alveo U50 and U50DD cards.

Class A Products

Table 8: EMC Standards

Standard Alveo U50 Alveo U50DDFCC Part 15 – Radiated & Conducted Emissions (USA) ✓CAN ICES-3(A)/NMB-3(A) – Radiated & Conducted Emissions (Canada) ✓CISPR 32 – Radiated & Conducted Emissions (International) ✓

Appendix B: Regulatory and Compliance Information




Table 8: EMC Standards (cont'd)

Standard Alveo U50 Alveo U50DDEN55032: 2015 – Radiated & Conducted Emissions (European Union) ✓ ✓EN55024: 2010 +A1:2001+A2:2003 – Immunity (European Union) ✓ ✓EMC Directive 2014/30/EC ✓ ✓VCCI (Class A)– Radiated & Conducted Emissions (Japan) ✓CNS13438 – Radiated & Conducted Emissions (Taiwan) ✓CNS 15663 - RoHS (Taiwan) ✓AS/NZS CISPR 32 – Radiated and Conducted Emissions (Australia/New Zealand) ✓Article 58-2 of Radio Waves Act, Clause 3 (Korea) ✓

Regulatory Compliance MarkingsThe following table shows the product certification markings that are provided, when required,with the Alveo U50 and U50DD cards.

Table 9: Product Certification Markings

Product Certification Markings Alveo U50 Alveo U50DDUL Listed Accessories Mark for the USA and Canada ✓CE mark ✓ ✓FCC markings ✓VCCI marking ✓Australian C-Tick mark ✓Korea MSIP mark ✓Taiwan BSMI mark ✓

CE Directives2014/35/EC, Low Voltage Directive (LVD)

2014/30/EC, Electromagnetic Compatibility (EMC) Directive

CE StandardsEN standards are maintained by the European Committee for Electrotechnical Standardization(CENELEC). IEC standards are maintained by the International Electrotechnical Commission (IEC).





Electromagnetic CompatibilityEN:55032:2015, Information Technology Equipment Radio Disturbance Characteristics – Limits andMethods of Measurement

EN:55024:2015, Information Technology Equipment Immunity Characteristics – Limits and Methodsof Measurement

This is a Class A product. In a domestic environment, this product can cause radio interference, inwhich case the user might be required to take adequate measures.

Compliance MarkingsThe information in this section only applies to Alveo U50DD cards.

In August of 2005, the European Union (EU) implemented the EU Waste Electricaland Electronic Equipment (WEEE) Directive 2002/96/EC and later the WEEE RecastDirective 2012/19/EU. These directives require Producers of electronic andelectrical equipment (EEE) to manage and finance the collection, reuse, recyclingand to appropriately treat WEEE that the Producer places on the EU market afterAugust 13, 2005. The goal of this directive is to minimize the volume of electricaland electronic waste disposal and to encourage re-use and recycling at the endof life.Xilinx has met its national obligations to the EU WEEE Directive by registering inthose countries to which Xilinx is an importer. Xilinx has also elected to join WEEECompliance Schemes in some countries to help manage customer returns atend-of-life.If you have purchased Xilinx-branded electrical or electronic products in the EUand are intending to discard these products at the end of their useful life, pleasedo not dispose of them with your other household or municipal waste. Xilinx haslabeled its branded electronic products with the WEEE Symbol to alert ourcustomers that products bearing this label should not be disposed of in a landfillor with municipal or household waste in the EU.

This product complies with Directive 2002/95/EC on the restriction of hazardoussubstances (RoHS) in electrical and electronic equipment.

Other Compliance StatementsThe following sections only apply to Alveo U50 cards.





FCC Class A User InformationThe Class A products listed above comply with Part 15 of the FCC Rules. Operation is subject tothe following two conditions:

1. This device may not cause harmful interference.

2. This device must accept any interference received, including interference that may causeundesired operation.

IMPORTANT! This equipment has been tested and found to comply with the limits for a Class A digital device,pursuant to Part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmfulinterference when the equipment is operated in a commercial environment. This equipment generates, uses, andcan radiate radio frequency energy and, if not installed and used in accordance with the instructions, may causeharmful interference to radio communications. Operation of this equipment in a residential area is likely tocause harmful interference, in which case the user will be required to correct the interference at his or her ownexpense.

IMPORTANT! Cet équipement a été testé et jugé conforme à la Class A digital device, conformément à la règle15 du standard FCC. Ces limites sont conçues pour fournir des protections contre des interférences nuisibleslorsque l'équipement est utilisé dans un environnement commercial. Cet équipement génère, utilise et peutémettre des énergies de radio-fréquence et, s'il n'est pas installé et utilisé conformément aux instructions, peutnuire aux communications radio. L'exploitation de cet équipement dans une zone résidentielle est susceptible decauser des interférences nuisibles, auquel cas auquel cas l'utilisateur peut être tenu de prendre des mesuresadéquates à ses propres frais.

WICHTIG! Dieses Gerät wurde getestet und entspricht den Grenzwerten für digitale Geräte der Klasse Agemäß Teil 15 der FCC-Bestimmungen. Diese Grenzwerte bieten einen angemessenen Schutz gegen schädlicheInterferenzen, wenn das Gerät in einer gewerblichen Umgebung betrieben wird. Dieses Gerät erzeugt undverwendet Hochfrequenzenergie und kann diese abstrahlen. Wenn es nicht gemäß den Anweisungen installiertund verwendet wird, kann dies Funkstörungen verursachen. Der Betrieb dieses Geräts in einem Wohngebietkann schädliche Interferenzen verursachen. In diesem Fall muss der Benutzer die Interferenz auf eigene Kostenbeheben.

CAUTION! If the device is changed or modified without permission from Xilinx, the user may void his or herauthority to operate the equipment.

ATTENTION! Si l'appareil est modifié sans l'autorisation de Xilinx, l'utilisateur peut annuler son abilité à utiliserl'équipement.

VORSICHT! Wenn das Gerät ohne Erlaubnis von Xilinx geändert wird, kann der Benutzer seine Berechtigungzum Betrieb des Geräts verlieren.

Canadian Compliance (Industry Canada)CAN ICES-3(A)/NMB-3(A)





VCCI Class A Statement

KCC Notice Class A (Republic of Korea Only)

BSMI Class A Notice (Taiwan)

Manufacturer Declaration European Community

Manufacturer Declaration

Xilinx declares that the equipment described in this document is in conformance with therequirements of the European Council Directive listed below:

• Low Voltage Directive 2014/35/EU

• EMC Directive 2014/30/EU

• RoHS Directive 2011/65/EU, 2015/863

These products follow the provisions of the European Directive 2014/53/EU.

Dette produkt er i overensstemmelse med det europæiske direktiv 1999/5/EC.





Dit product is in navolging van de bepalingen van Europees Directief 1999/5/EC.

Tämä tuote noudattaa EU-direktiivin 1999/5/EC määräyksiä.

Ce produit est conforme aux exigences de la Directive Européenne 1999/5/EC.

Dieses Produkt entspricht den Bestimmungen der Europäischen Richtlinie 1999/5/EC.

Þessi vara stenst reglugerð Evrópska Efnahags Bandalagsins númer 1999/5/EC.

Questo prodotto è conforme alla Direttiva Europea 1999/5/EC.

Dette produktet er i henhold til bestemmelsene i det europeiske direktivet 1999/5/EC.

Este produto cumpre com as normas da Diretiva Européia 1999/5/EC.

Este producto cumple con las normas del Directivo Europeo 1999/5/EC.

Denna produkt har tillverkats i enlighet med EG-direktiv 1999/5/EC.

This declaration is based upon compliance of the Class A products listed above to the followingstandards:

EN 55032 (CISPR 32 Class A) RF Emissions Control.EN 55024:2010 (CISPR 24) Immunity to Electromagnetic Disturbance.EN 60950-1:2006/A11:2009A1:2010/A12:2011 Information Technology Equipment- Safety-Part 1: General Requirements.EN 50581:2012 - Technical documentation for the assessment of electrical and electronicproducts with respect to the restriction of hazardous substances.

CAUTION! In a domestic environment, Class A products may cause radio interference, in which case the usermay be required to take adequate measures.

ATTENTION! Dans un environnement domestique, les produits de Classe A peuvent causer des interférencesradio, auquel cas l'utilisateur peut être tenu de prendre des mesures adéquates.

VORSICHT! In einer häuslichen Umgebung können Produkte der Klasse A Funkstörungen verursachen. Indiesem Fall muss der Benutzer möglicherweise geeignete Maßnahmen ergreifen.

Responsible Party

Xilinx, Inc.2100 Logic Drive, San Jose, CA 95124United States of AmericaPhone: (408) 559-7778





Appendix C

Additional Resources and LegalNotices

Xilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see XilinxSupport.

Documentation Navigator and Design HubsXilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, andsupport resources, which you can filter and search to find information. To open DocNav:

• From the Vivado® IDE, select Help → Documentation and Tutorials.

• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.

• At the Linux command prompt, enter docnav.

Xilinx Design Hubs provide links to documentation organized by design tasks and other topics,which you can use to learn key concepts and address frequently asked questions. To access theDesign Hubs:

• In DocNav, click the Design Hubs View tab.

• On the Xilinx website, see the Design Hubs page.

Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.

ReferencesThese documents provide supplemental material useful with this guide:

Appendix C: Additional Resources and Legal Notices


https://www.xilinx.com/support

https://www.xilinx.com/support

https://www.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs

https://www.xilinx.com/cgi-bin/docs/rdoc?t=docnav



Product Websites

The most up-to-date information related to the Alveo™ U50 card and documentation is availableon the following websites:

Alveo U50 Data Center Accelerator Card

Supplemental Documents

The following Xilinx document provide supplemental material useful with this guide.

• UltraFast Design Methodology Guide for the Vivado Design Suite (UG949)

• Vivado Design Suite User Guide: System-Level Design Entry (UG895)

• Getting Started with Alveo Data Center Accelerator Cards (UG1301)

• Alveo U50 Data Center Accelerator Card Installation Guide (UG1370)

• Alveo Programming Cable User Guide (UG1377)

• UltraScale Architecture Configuration User Guide (UG570)

• Vivado Design Suite User Guide: Programming and Debugging (UG908)

• Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)

• UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)

• Vivado Design Suite User Guide: Using Constraints (UG903)

• UltraScale Architecture PCB Design User Guide (UG583)

Additional Links

The following links provide supplemental material useful with this guide.

• Xilinx, Inc: https://www.xilinx.com

• Micron Technology: http://www.micron.com

• Si5394 Data Sheet: https://www.silabs.com/documents/public/data-sheets/si5395-94-92-a-datasheet.pdf

• Future Technology Devices International, Ltd.: http://www.ftdichip.com

(FT4232HQ)

• SFP-DD module: SFP-DD Specification



https://www.xilinx.com/products/boards-and-kits/alveo/u50.html

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug949-vivado-design-methodology.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug895-vivado-system-level-design-entry.pdf

https://www.xilinx.com/cgi-bin/docs/bkdoc?k=accelerator-cards;v=2019.2;d=ug1301-getting-started-guide-alveo-accelerator-cards.pdf




https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug908-vivado-programming-debugging.pdf

https://www.xilinx.com/cgi-bin/docs/ndoc?t=data_sheets;d=ds923-virtex-ultrascale-plus.pdf

https://www.xilinx.com/cgi-bin/docs/ipdoc?c=ultrascale_memory_ip;v=latest;d=pg150-ultrascale-memory-ip.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug903-vivado-using-constraints.pdf

https://www.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug583-ultrascale-pcb-design.pdf


http://www.micron.com

https://www.silabs.com/documents/public/data-sheets/si5395-94-92-a-datasheet.pdf

https://www.silabs.com/documents/public/data-sheets/si5395-94-92-a-datasheet.pdf

http://www.ftdichip.com

http://sfp-dd.com/specification/



Please Read: Important Legal NoticesThe information disclosed to you hereunder (the "Materials") is provided solely for the selectionand use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials aremade available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES ANDCONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TOWARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANYPARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, includingnegligence, or under any other theory of liability) for any loss or damage of any kind or naturerelated to, arising under, or in connection with, the Materials (including your use of theMaterials), including for any direct, indirect, special, incidental, or consequential loss or damage(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of anyaction brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinxhad been advised of the possibility of the same. Xilinx assumes no obligation to correct anyerrors contained in the Materials or to notify you of updates to the Materials or to productspecifications. You may not reproduce, modify, distribute, or publicly display the Materialswithout prior written consent. Certain products are subject to the terms and conditions ofXilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms containedin a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe orfor use in any application requiring fail-safe performance; you assume sole risk and liability foruse of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which canbe viewed at https://www.xilinx.com/legal.htm#tos.

AUTOMOTIVE APPLICATIONS DISCLAIMER

AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOTWARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONSTHAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS ASAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USINGOR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TESTSUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATIONWITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TOAPPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCTLIABILITY.



https://www.xilinx.com/legal.htm#tos





Copyright

© Copyright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex,Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the UnitedStates and other countries. OpenCL and the OpenCL logo are trademarks of Apple Inc. used bypermission by Khronos. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used underlicense. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex, PrimeCell, Mali, andMPCore are trademarks of Arm Limited in the EU and other countries. All other trademarks arethe property of their respective owners.



