altmult accum Megafunction User Guide - Intel...1–2 Altera Corporation altmult_accum Megafunction User Guide March 2007 Features Features The altmult_accum megafunction implements

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altmult_accum Megafunction

User Guide

Document Version: 3.2Software Version: 7.0Document Date: March 2007

http://www.altera.com

Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks andservice marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrantsperformance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to makechanges to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-plication or use of any information, product, or service described herein except as expressly agreed to in writing by AlteraCorporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-formation and before placing orders for products or services.

ii Altera Corporationaltmult_accum Megafunction User Guide Preliminary March 2007

UG-MF9904-3.2

Altera Corporation

Contents

About this User Guide ............................................................................. vRevision History ........................................................................................................................................ vHow to Contact Altera .............................................................................................................................. vTypographic Conventions ...................................................................................................................... vi

Chapter 1. About this MegafunctionDevice Family Support ......................................................................................................................... 1–1Introduction ............................................................................................................................................ 1–1Features ................................................................................................................................................... 1–2General Description ............................................................................................................................... 1–2

Common Applications .................................................................................................................... 1–4Resource Utilization and Performance ............................................................................................... 1–4

Chapter 2. Getting StartedSoftware and System Requirements ................................................................................................... 2–1MegaWizard Plug-In Manager Customization ................................................................................. 2–1MegaWizard Page Descriptions .......................................................................................................... 2–2

Inferring Megafunctions from HDL Code .................................................................................. 2–18Instantiating Megafunctions in HDL Code ..................................................................................... 2–19Identifying a Megafunction after Compilation ............................................................................... 2–19Simulation ............................................................................................................................................. 2–19

Quartus II Simulation .................................................................................................................... 2–19EDA Simulation .............................................................................................................................. 2–20

SignalTap II Embedded Logic Analyzer .......................................................................................... 2–20Design Example: Basic Serial FIR Filter ............................................................................................ 2–21

Design Files ..................................................................................................................................... 2–21Example ........................................................................................................................................... 2–21Generate a Multiplier-Accumulator ............................................................................................ 2–21Implement the Multiplier-Accumulator ..................................................................................... 2–32Functional Results—Simulate the Multiplier-Accumulator in Quartus ................................ 2–34Functional Results—Simulate the 8-bit Multiplier Design in ModelSim-Altera .................. 2–36

Conclusion ............................................................................................................................................ 2–37

Chapter 3. SpecificationsPorts and Parameters ............................................................................................................................ 3–1

Ports and Parameters for the altmult_accum Megafunction ..................................................... 3–1

iii

Contents

iv Altera Corporationaltmult_accum Megafunction User Guide

Altera Corporation March 2007

About this User Guide

Revision History The table below shows the revision history for this User Guide.

How to Contact Altera

For the most up-to-date information about Altera® products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below.

Date/Version Changes Made Summary of Changes

March 2007v3.2

Added Cyclone® III to list of supported devices. Updated for Quartus® II version 7.0 by adding support for Cyclone III device.

December 2006v3.1

Added Stratix® III device information.

December 2006v3.0

Updated for Quartus® II 6.1 version software.

May 2006v2.0

Updated for Quartus II 6.0 version software, including updated GUI and project examples, and new ModelSim simulation section

January 2006v1.1

Ports and Parameters updated for Quartus II 5.1 version software.

September 2004v1.0

Initial release.

Information Type USA and Canada All Other Locations

Technical support www.altera.com/mysupport/ altera.com/mysupport/

(800) 800-EPLD (3753)(7:00 a.m. to 5:00 p.m. Pacific Time)

(408) 544-7000 (1)(7:00 a.m. to 5:00 p.m. Pacific Time)

Product literature www.altera.com www.altera.com

Altera literature services [email protected] (1) [email protected] (1)

Non-technical customer service

(800) 767-3753(7:00 a.m. to 5:00 p.m. Pacific Time)

(408) 544-7000 (7:30 a.m. to 5:30 p.m. Pacific Time)

FTP site ftp.altera.com ftp.altera.com

Note to table:(1) You can also contact your local Altera sales office or sales representative.

valtmult_accum Megafunction User Guide

http://www.altera.com/mysupport/

http://www.altera.com/mysupport/



mailto:[email protected]

mailto:[email protected]

ftp://ftp.altera.com

ftp://ftp.altera.com


http://www.altera.com/mysupport

Typographic Conventions

Typographic Conventions

This document uses the typographic conventions shown below.

Visual Cue Meaning

Bold Type with Initial Capital Letters

Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.

bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.

Italic Type with Initial Capital Letters

Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design.

Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.

Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu.

“Subheading Title” References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: “Typographic Conventions.”

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.

1., 2., 3., anda., b., c., etc.

Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.

■ ● • Bullets are used in a list of items when the sequence of the items is not important.

v The checkmark indicates a procedure that consists of one step only.

1 The hand points to information that requires special attention.

c A caution calls attention to a condition or possible situation that can damage or destroy the product or the user’s work.

w A warning calls attention to a condition or possible situation that can cause injury to the user.

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

vi Altera Corporationaltmult_accum Megafunction User Guide March 2007


Chapter 1. About thisMegafunction

Device Family Support

The altmult_accum megafunction supports the following target Altera device families:

■ Stratix® III ■ Stratix II■ Stratix II GX ■ Stratix■ Stratix GX■ Cyclone® III■ Cyclone II■ Cyclone■ HardCopy® II■ HardCopy Stratix■ MAX® II■ MAX 7000AE■ MAX 7000B■ MAX 7000S■ MAX 3000A■ ACEX 1K®

■ APEX™ II■ APEX 20KC■ APEX 20KE■ FLEX 10K®

■ FLEX® 10KA■ FLEX 10KE■ FLEX 6000

Introduction As design complexities increase, use of vendor-specific intellectual property (IP) blocks has become a common design methodology. Altera provides parameterizable megafunctions that are optimized for Altera device architectures. Using megafunctions instead of coding your own logic saves valuable design time. Additionally, the Altera provided functions may offer more efficient logic synthesis and device implementation. The megafunction’s size is scaled by setting parameters.

1–1altmult_accum Megafunction User Guide

Features

Features The altmult_accum megafunction implements a multiplier-accumulator and offers three additional features, which include:

■ Performing either signed or unsigned operations■ Support for pipelining with parameterized output latency■ Active high asynchronous clear and clock enable control inputs

General Description

The altmult_accum megafunction is one of the arithmetic megafunctions supported in the Quartus® II software MegaWizard® Plug-In Manager. The altmult_accum megafunction allows you to implement a multiplier-accumulator. A multiplier-accumulator accepts a pair of inputs, multiplies the two inputs together, and feeds their result into an accumulator to be added to or subtracted from its previous registered result. This function is expressed as:

In this equation, N is the number of cycles of data that has entered into the accumulator. Figure 1–1 illustrates a basic multiplier-accumulator with 2-bit inputs.

Figure 1–1. Basic 2-Bit Multiplier-Accumulator

y 1±( )

i 0–

N 1–

∑ Ai Bi××=

A0[1..0]

B0[1..0]

Y[4..0]p[1..0]D

CLRN

Q

DFF

1–2 Altera Corporationaltmult_accum Megafunction User Guide March 2007

About this Megafunction

Variations of the multiplier-accumulator include:

■ Switching between addition and subtraction operations■ Using signed or unsigned data representation■ Implementing input shift register chains■ Including additional input■ Implementing output and pipelined registers, controlling

asynchronous clear■ Implementing synchronous load of the accumulator■ Sizing the data width of the inputs and output

Figure 1–2 shows a multiplier-accumulator with these variations.

Figure 1–2. Multiplier-Accumulator with Optional Features

The altmult_accum megafunction implements the multiplier-accumulator in dedicated digital signal processing (DSP) block circuitry, logic elements (LEs), or adaptive logic modules (ALMs). The altmult_accum megafunction accepts data input widths of up to 18 bits.

Additional features include dynamically changing add and subtract operations in the accumulator, dynamically changing signed or unsigned data support, and setting up data shift register chains.

P Accumuator

PRN

CLRN

D Q

SET

CLR

D Q

Q

Sign B

Synchronous Load

Sign A

Add/Sub 0

A

B

Shift Register A

Shift Register B

SET

CLR

D Q

QPRN

CLRN

D Q

PRN

CLRN

D Q

PRN

CLRN

D Q

SET

CLR

D Q

Q

Sign A

Sign BSET

CLR

D Q

Q

SET

CLR

D Q

Q

SET

CLR

D Q

Q

SET

CLR

D Q

Q

SET

CLR

D Q

Q

SET

CLR

D Q

Q

SET

CLR

D Q

Q

DFF

DFF

DFF

PRN

CLRN

D Q

DFF

DFF

Altera Corporation 1–3March 2007 altmult_accum Megafunction User Guide

Resource Utilization and Performance

Common Applications

Multiplier-accumulator applications include serial finite impulse response (FIR) filters, fast Fourier transforms (FFTs), and other designs that require a serial summation of products. Altera recommends that you use the altmult_accum megafunction when implementing a multiplier accumulator in Altera devices because the megafunction takes advantage of the performance that the dedicated multiplier circuitry offers.

The altmult_accum megafunction is implemented in the regular logic resources or with DSP blocks, which are available in Stratix III, Stratix II, Stratix, and Stratix GX devices. In Cyclone II devices, the multiplier is implemented in the embedded multiplier and the accumulator is implemented in LEs. If you are using Cyclone devices, the entire multiplier-accumulator is implemented in LEs.

f For more information about the multiply-accumulate mode of Stratix DSP blocks, refer to the Using the DSP Block in Stratix & Stratix GX Devices chapter in volume 2 of the Stratix Handbook.

For more information about using the multiply-accumulate mode of Stratix DSP blocks in DSP applications, refer to the Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices chapter in volume 2 of the Stratix Handbook.

For more information about the multiply-accumulate mode of the Stratix II DSP blocks, refer to the DSP Blocks in Stratix II Devices chapter of the Stratix II Handbook.

For more information about the multiply-accumulate mode of the Stratix III DSP blocks, refer to the DSP Blocks in Stratix III Devices chapter of the Stratix III Handbook.

For more information on using embedded multipliers in Cyclone II devices, refer to the Embedded Multipliers in Cyclone II Devices chapter of the Cyclone II Handbook.


In Stratix III, Stratix II, Stratix, and Stratix GX devices the multiplier and the accumulator of the altmult_accum megafunction are placed in the DSP block circuitry. The DSP blocks use the 18-bit × 18-bit input multiplier to process data with widths of up to 18 bits. The registers and extra pipeline registers for the following signals are also placed inside the DSP block: data input, signed/unsigned select, add/subtract select, synchronous load, and products of multipliers. In the case of the output result, the first register is placed in the DSP block. The extra latency registers are placed in logic elements outside the block.


About this Megafunction

f For more information on DSP blocks in Stratix and Stratix GX devices, refer to the Using the DSP Blocks in Stratix & Stratix GX Devices chapter in volume 2 of the Stratix Handbook.

For more information, refer to the DSP Blocks in Stratix II Devices chapter in volume 2 of the Stratix II Handbook.

Cyclone II devices have 18-bit × 18-bit embedded multiplier blocks. When the altmult_accum megafunction is implemented in a Cyclone II device, the multiplier is implemented in the embedded multiplier blocks, while the accumulator is put in logic elements LEs.

In Cyclone devices, both the multiplier and accumulator are placed in LEs.

f For more information on implementing multipliers using memory blocks in Altera FPGAs, refer to AN 306: Implementing Multipliers in Altera FPGAs.

For more information on implementing multipliers in FPGAs and memory-based multipliers, refer to the altmemmult Megafunction User Guide.

Table 1–1 summarizes the resource usage for an altmult_accum megafunction used to implement a multiplier-accumulator with its default settings.

Table 1–1. Resource Usage for an altmult_accum Megafunction (1)

Device Optimization Width Logic Usage

Stratix II Area 18 4 DSP blocks

Cyclone II Balanced 18 50 LEs; 2 DSP blocks

Stratix, Stratix GX Speed 18 4 DSP blocks

Cyclone Balanced 18 550 LEs

Note to Table 1–1:(1) You can get the performance information from the MegaWizard Plug-In Manager.

The information in this table is valid and accurate in Quartus II version 6.0 and later.





Chapter 2. Getting Started

Software and System Requirements

The instructions in this section require the following software:

■ For operating system support information, refer to:

http://www.altera.com/support/software/os_support/oss-index.html

■ Quartus® II software beginning with version 6.1

MegaWizard Plug-In Manager Customization

The MegaWizard® Plug-In Manager creates or modifies design files that contain custom megafunction variations which can then be instantiated in a design file. The MegaWizard Plug-In Manager provides a wizard that allows you to specify options for the altmult_accum megafunction. You can use the MegaWizard Plug-In Manager to set the altmult_accum megafunction features for each multiplier-accumulator in the design.

Start the MegaWizard Plug-In Manager in one of the following ways:

■ On the Tools menu, click MegaWizard Plug-In Manager.■ When working in the Block Editor, from the Edit menu, click Insert

Symbol as Block, or right-click in the Block Editor, point to Insert, and click Symbol as Block. In the Symbol dialog box, click MegaWizard Plug-In Manager.

■ Start the stand-alone version of the MegaWizard Plug-In Manager by typing the following command at the command prompt: qmegawizr

2–1altmult_accum Megafunction User Guide

MegaWizard Page Descriptions


This section provides descriptions of the options available on the individual pages of the altmult_accum MegaWizard Plug-In Manager.

Page 1 of the MegaWizard Plug-In Manager is shown in Figure 2–1.

Figure 2–1. MegaWizard Plug-In Manager [page 1]

You can choose to create, edit, or copy a custom megafunction variation. On page 2a of the altmult_accum wizard, specify the plug-in, family of device you want to use, type of output file to create, and the name of the output file (Figure 2–2). Choose AHDL (.tdf), VHDL (.vhd), or Verilog HDL (.v) as the output file type. You can also create a clear box instantiation for third-party EDA tools.


Getting Started

Figure 2–2. MegaWizard Plug-In Manager [page 2a]

On page 3 of the altmult_accum wizard, specify the number of multipliers to be created, the width of the input bus, and whether the input bus is to be signed, unsigned, or variable. You can also set options to configure signa and signb inputs (Figure 2–3).



Figure 2–3. MegaWizard Plug-In Manager—ALTMULT_ACCUM [page 3 of 10]

Table 1 shows the options available on page 3 of the altmult_accum MegaWizard Plug-In Manager.

Table 2–1. altmult_accum Plug-In Manager (Page 3) Options (Part 1 of 2)

Function Description

Currently selected device family Specify the family device you want to use.

What is the number of multipliers? Specify the number of multipliers.

All multipliers have similar configurations Specify if all the multipliers have the same configurations. This option is selected by default.

Add support for hardware saturation and rounding. This will force all inputs to be in Q1.15 format

Available when device is Cyclone® II, HardCopy® II,

Stratix® II or Stratix II GX. Select hardware saturation and rounding support. Default rounding for all input is set to Q1.15 format (fixed point arithmetic notation with 15-bits of precision).

How wide should the A input buses be? Specify the width of A input buses. If device is Cyclone II, HardCopy II, Stratix II, Stratix II GX or Stratix III, the width of A is fixed at 16 bits when hardware saturation and rounding is selected.


Getting Started

On page 4 of the altmult_accum wizard, specify which operation is performed on the first pair of multipliers Add/Sub and select the implementation type. Specify whether to use default or dedicated multiplier circuitry, or logic elements (Figure 2–4).

How wide should the B input buses be? Specify the width of B input buses. If device is Cyclone II, HardCopy II, Stratix II, Stratix II GX, or Stratix III, the width of A is fixed at 16 bits when hardware saturation and rounding is selected.

How wide should the 'result' output bus be? Specify the width of 'result' output buses.

In what format should the 'result' output bus be? Available when device is Cyclone II, HardCopy II, Stratix II, Stratix II GX, or Stratix III and if the hardware saturation and rounding option is selected. Specify the rounding format of 'result' output bus

Create a 4th asynchronous clear input option. This forces all registers to have an associated asynchronous clear input.

Select to create an asynchronous clear input.

Create an associated clock enable for each clock Select to create an associated clock enable for each clock.

Input Representation Specify the input representation format.

What is the representation format for A inputs? Specify the representation format for A inputs. When device is Cyclone II, HardCopy II, Stratix II, Stratix II GX, or Stratix III and if the hardware saturation and rounding option is selected, representation format for A inputs is default to 'signed'.

What is the representation format for B inputs? Specify the representation format for B inputs. When device is Cyclone II, HardCopy II, Stratix II, Stratix II GX, or Stratix III and if the hardware saturation and rounding option is selected, representation format for B inputs is default to 'signed'.

'signa' input controls the sign (1 signed/0 unsigned)

Available when representation format for A inputs is 'variable'. Specify the input register and/or pipeline register.

'signb' input controls the sign (1 signed/0 unsigned)

Available when representation format for B inputs is 'variable'. Specify the input register and/or pipeline register.






Table 2–2 shows the options available on page 4 of the altmult_accum MegaWizard Plug-In Manager.



Outputs Configuration Specify the output configurations.

Create a shiftout output from A input of the last multiplier

Select to create a shiftout output. When the device is Stratix III, 'More Options' is available for shiftout register configuration.

Create a shiftout output from B input of the last multiplier

Select to create a shiftout output. This option is not available when device is Stratix III.

Register output of the adder unit Select to create register to the output.

Adder operation Specify adder operation configurations.

What operation should be performed on outputs of the first pair of multiplier?

Specify the operation to be performed on the outputs of the first pair of multiplier.

What operation should be performed on outputs of the second pair of multipliers?

Specify the operation to be performed on the outputs of the second pair of multiplier. Only available when the number of multipliers is 4.


Getting Started

Page 5 of the altmult_accum wizard (Figure 2–5) is applicable for Stratix II devices if you chose Add support for hardware saturation and rounding on page 3 of the altmult_accum wizard. If you chose Stratix III devices, go to Figure 2–7 on page 2–10.

1 Stratix II and Stratix III devices have built-in circuitry in the DSP blocks to support the Q1.3 input format rounding and saturation.

On page 5 you can also customize the rounding options and enable saturation handling for the multiplier and accumulator outputs. They can be set to be always on, never on, or variable.

Figure 2–5. Figure 5 MegaWizard Plug-In Manager—ALTMULT_ACCUM [page 5 of 10]

Implementation Specify implementation configurations.

Which multiplier-adder implementation should be used?

Specify which implementation to use for the multiplier-adder. 'Use dedicated multiplier circuitry' is only available on devices which have DSP block support. 'Use logic elements' is not available for the Stratix III device.





Table 2–3 shows the options available on page 5 of the altmult_accum MegaWizard Plug-In Manager for a Stratix II device with saturation and rounding support.

On page 6 of the altmult_accum wizard, specify the rounding configurations for the multiplier (Figure 2–6).

Table 2–3. altmult_accum Plug-In Manager (Page 5) Options


Saturation Specifies saturation configurations for the multiplier and accumulator.

Saturation operations on outputs of the first pair of multipliers

Specifies the saturation operations for the first pair of multipliers. Values are Enabled, Disabled, and Variable.

'mult_saturation' input controls the operation (1 enable/0 disable)

When the saturation operation on outputs of the multiplier is set to “Variable”, the “mult_saturation” register can be configured.

Create a saturation overflow output for the multiplier mult_is_saturated is created and PORT_MULT_IS_SATURATED is “USED”. This option is available for Stratix II devices.

Saturation operations on output of the accumulator Specifies the saturation operations for the output of the accumulator. Values are Enabled, Disabled, and Variable.

'accum_saturation' input controls the operation (1 enable/0 disable)

When the saturation operation on output of the accumulator is set to “Variable”, 'accum_saturation' register can be configured.

Create a saturation overflow output for the accumulator accum_is_saturated is created and PORT_ACCUM_IS_SATURATED is 'USED'. This option is available for Stratix II devices.


Getting Started


Table 2–4 shows the options available on page 6 of the altmult_accum MegaWizard Plug-In Manager for Stratix II device with rounding configurations.



Rounding operations on output of each of the first pair of multipliers

Specifies the rounding operations for the first pair of multipliers. Values are Enabled, Disabled, and Variable.

'mult_rounding' input controls the operation (1 enable/0 disable)

When the rounding operations on outputs of the multiplier is set to “variable”, you can configure the mult_rounding register.

Rounding operation on the accumulator Specifies the rounding operations for the accumulator. Values are Enabled, Disabled, and Variable.

'accum_rounding' input controls the operation (1 enable/0 disable)

When the rounding operation on the accumulator is set to “Variable”, you can configure the accum_rounding register.



On page 5 of the altmult_accum wizard, specify the chainout, shift, loopback, and accumulator configurations for all the multipliers. (Figure 2–7). This page and the following pages are available for Stratix III devices only.

Figure 2–7. MegaWizard Plug-In Manager—ALTMULT_ACCUM [page 5 of 11] for Stratix III

Table 2–5 shows the options available on page 5 of the altmult_accum MegaWizard Plug-In Manager for Stratix II device with chainout, shift, loopback and accumulator configurations.

Table 2–5. altmult_accum Plug-In Manager (Page 5 of 11) Options (Part 1 of 2)


Enable the chainout adder Select to enable chainout adder. This option is only available if there are more than 2 multipliers selected on page 3.

Register output of the chainout adder unit Select to register output of the chainout adder unit. More options are available for the register configurations.

Use the 'zero_chainout' input Select to use the zero_chainout input port. More options are available for the port configurations.


Getting Started

On page 6 of the altmult_accum wizard, specify the saturation configurations for all the multipliers (Figure 2–8). This page is available for Stratix III devices only.


What is the type of the operation? Specifies shift or rotate operation. Values are None, Left, Right, Rotate, or Variable.

shift_right' input controls the shift operation, when 'rotate' port is not asserted (1 shift right/0 shift left)

Specifies the configurations for shift_right.

'rotate' input controls the rotate operation (1 rotate/0 no rotation)

Specifies the configurations for rotate.

Enable the accumulator mode Select to enable the accumulator mode.

What is the accumulator operation type? Specifies the accumulator operation type. Values are Add or Subtract.

Use the 'accum_sload' input Select to use the accum_sload input. More options are available for the port configurations.





Table 2–6 shows the options available on page 6 of the altmult_accum MegaWizard Plug-In Manager for the Stratix II device with saturation configurations.

On page 7 of the altmult_accum wizard, specify the rounding configurations for all the multipliers (Figure 2–9). This page is available for Stratix III devices only.

Table 2–6. altmult_accum Plug-In Manager (Page 6 of 11) Options


What saturation operation type should be performed? Specifies which saturation operation to perform. Values are Symmetric and Asymmetric. The configuration applies to both output and chainout adders.

What is the saturation fractional width? Specifies the saturation fractional width. The configuration applies to both output and chainout adders.

Should saturation operation be performed at the output adder(s)?

Specifies if saturation operation should be performed at the output adder(s). Values are Enabled, Disabled, and Variable.

'output_sat' input controls the saturation operation (1 saturation/0 no saturation)

Specifies the configurations for output_sat.

Create a saturation overflow output for the output adder Select to create a saturation overflow output for the output adder.

Should saturation operation be performed at the chainout adder(s)?

Specifies if saturation operation should be performed at the chainout adder(s). Values are Enabled, Disabled, and Variable.

'chainout_sat' input controls the saturation operation (1 saturation/0 no saturation)

Specifies the configurations for chainout_sat.

Create a saturation overflow output for the chainout adder

Select to create a saturation overflow output for the chainout adder


Getting Started


Table 2–7 shows the options available on page 7 of the altmult_accum MegaWizard Plug-In Manager for the Stratix II device with rounding configurations.



What rounding operation type should be performed? Specifies which rounding operation to perform. Values are Nearest Even and Nearest Integer. The configuration applies to both output and chainout adders.

What is the rounding fractional width? Specifies the rounding fractional width. The configuration applies to both output and chainout adders.

Should rounding operation be performed at the output adder(s)?

Specifies if the rounding operation should be performed at the chainout adder(s). Values are Enabled, Disabled, and Variable.

'output_round' input controls the rounding operation (1 rounding/0 no rounding)

Specifies the configurations for output_round.



On page 7 of the altmult_accum wizard, specify the input and output for all the multipliers (Figure 2–10). From this page forward, it is applicable for all devices. The labeling of the page may differ.


Should rounding operation be performed at the chainout adder(s)?

Specifies if rounding operation should be performed at the chainout adder(s). Values are Enabled, Disabled, and Variable.

chainout_round' input controls the saturation operation (1 rounding/0 no rounding)

Specifies the configurations for chainout_round.




Getting Started

Table 2–8 shows the options available on page 7 of the altmult_accum MegaWizard Plug-In Manager for the Stratix II device with input and output configurations.

On page 8 of the altmult_accum wizard, specify configurations for the accumulator (Figure 2–11).



Input configuration Specifies the input configuration for all the multipliers.

Register input A of the multiplier Select to register input A of the multiplier. More options are available to specify the data A input configuration.

Register input B of the multiplier Select to register input B of the multiplier. More options are available to specify data B input configuration.

What is the input A of the multiplier connected to? Specifies what the input A of the multiplier is connected to. Values are Multiplier Input, Shiftin Input, and Variable.

Use the same signal to control the source for input A of all multipliers

Select to use the same signal to control the source for input A of all multipliers if there is more than one multiplier.

What is the input B of the multiplier connected to? Specifies what the input B of the multiplier is connected to. Values are Multiplier Input, Shiftin Input, and Variable.

Use the same signal to control the source for input B of all multipliers

Select to use the same signal to control the source for input B of all multipliers if there is more than one multiplier.

Output configuration Specifies the output configuration for all the multipliers.

Register output of the multiplier Select to register output of the multiplier. More options are available to specify configuration of the output register.




Table 2–9 shows the options available on page 8 of the altmult_accum MegaWizard Plug-In Manager for the Stratix II device with accumulator support.



Create an 'accum_sload' input port Select to create an accum_sload input port. More options are available to specify the configuration of the accum_sload.

Create an 'accum_sload_upper_data' input port Specify the number of bits for accum_sload_upper_data"input port. More options are available to specify the configuration of the port.

Create an 'overflow' output port Select to create an overflow output port.

Add extra latency to the multiplier output Specify the number of latency to be added to the multiplier output.


Getting Started

Page 9 of the altmult_accum wizard gives you information about the simulation model file(s) needed to properly simulate the generated design files (Figure 2–12).


On page 10 of the altmult_accum wizard, you specify the type of files to generate with the MegaWizard Plug-in Manager (Figure 2–13). You can specify Verilog (.v), AHDL (.tdf), VHDL (.vhd), Quartus II Block Symbol Files (.bsf), Instantiation template file (<function name>_inst.v), or Verilog 'Black Box' declaration file (<function name>_bb.v).

1 The Verilog HDL, VHDL, or AHDL wrapper type files are selected automatically according to your settings on page 2a of the MegaWizard Plug-In Manager.




Inferring Megafunctions from HDL Code

Synthesis tools, including Quartus II integrated synthesis, recognize certain types of HDL code and automatically infer the appropriate megafunction when a megafunction will provide optimal results. That is, the Quartus II software uses the Altera megafunction code when compiling your design—even though you did not specifically instantiate the megafunction. The Quartus II software infers megafunctions because they are optimized for Altera devices, so the area and/or performance may be better than generic HDL code. Additionally, you must use megafunctions to access certain Altera architecture-specific features—such as memory, DSP blocks, and shift registers—that generally provide improved performance compared with basic logic elements (LEs).

f For more information on specific megafunction coding styles, refer to Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.

The Quartus II Handbook is located on the Altera website (www.altera.com).


Getting Started

Instantiating Megafunctions in HDL Code

When you use the MegaWizard Plug-In Manager to set up and parameterize a megafunction, it creates either a VHDL or Verilog HDL wrapper file that instantiates the megafunction (a black-box methodology). For some megafunctions, you can generate a fully synthesizable netlist for improved results with EDA synthesis tools such as Synplify and Precision RTL Synthesis (a clear-box methodology). Both clear-box and black-box methodologies are described in the third party synthesis support chapters in the Synthesis section in volume 1 of the Quartus II Handbook.

Identifying a Megafunction after Compilation

During a Quartus II compilation, analysis and elaboration is performed to build the structure of your design. You can locate your megafunction in the Project navigator window by expanding the compilation hierarchy and locating the megafunction by its name.

Similarly, to search for node names within the megafunction (using the Node Finder), in the Look in box, click Browse and select the megafunction in the Hierarchy box.

Simulation The Quartus II Simulation tool provides an easy-to-use, integrated solution for performing simulations. The following sections describe the simulation options.

Quartus II Simulation

With the Quartus II Simulator, you can perform two types of simulations: functional and timing. A functional simulation in the Quartus II program enables you to verify the logical operation of your design without taking into consideration the timing delays in the FPGA. This simulation is performed using only your RTL code. When performing a functional simulation, you add only signals that exist before synthesis. You can find these signals with Registers: pre-synthesis, Design Entry (all names), or the pin filters in the Node Finder. The top-level ports of megafunctions are found using these filters.

In contrast, timing simulation in the Quartus II software verifies the operation of your design with annotated timing information. This simulation is performed using the post place-and-route netlist. When performing a timing simulation, you add only signals that exist after place and route. These signals are found with the Post-Compilation filter of the Node Finder. During synthesis and place and route, the names of your RTL signals change. Therefore, it might be difficult to find signals from your megafunction instantiation in the Post-Compilation filter. However, if you want to preserve the names of your signals during the synthesis and place and route stages, you must use the synthesis attributes keep or preserve. These are Verilog HDL and VHDL synthesis


SignalTap II Embedded Logic Analyzer

attributes that direct analysis and synthesis to keep a particular wire, register, or node intact. You can use these synthesis attributes to keep a combinational logic node so you can observe the node during simulation. More information on these attributes is available in the Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook.

f For information on using synthesis attributes, refer to the appropriate chapter in the Synthesis section in volume 1 of the Quartus II Handbook.

EDA Simulation

Depending on the third-party simulation tool you are using, refer to the appropriate chapter in the Simulation section in volume 3 of the Quartus II Handbook. The Quartus II Handbook chapters show you how to perform functional and gate-level timing simulations that include the megafunctions, with details on the files that are needed and the directories where those files are located.

SignalTap II Embedded Logic Analyzer

The SignalTap® II embedded logic analyzer provides you with a non intrusive method of debugging all of the Altera megafuntions instantiated within your design. With the SignalTap II embedded logic analyzer, you can capture and analyze data samples for the top-level ports of the megafunctions in your design while your system is running at full speed.

To monitor signals from your Altera megafunctions, you must first custom-configure the SignalTap II embedded logic analyzer in the Quartus II design environment, and then include the analyzer as part of your Quartus II project. The Quartus II software will then seamlessly place and route the analyzer along with your design in the target architecture.

f For more information on using the SignalTap II embedded logic analyzer, refer to the Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in volume 3 of the Quartus II Handbook.


Getting Started

Design Example: Basic Serial FIR Filter

A multiplier-accumulator is typically used to implement functions such as a FIR filter. This design example implements a serial FIR filter. To implement this filter with the multiplier in the accumulator, both the data and coefficient are shifted serially into the multiplier and then summed in the accumulator.

Design Files

The design files are available in the Quartus II Projects section on the Design Examples page at: http://www.altera.com/literature/lit-ug.jsp

Select the links below the altmult_accum Megafunction User Guide to download the design files.

Example

This design example uses the altmult_accum megafunction to create a multiplier-accumulator for devices with dedicated DSP circuitry. A multiplier-accumulator consists of a single multiplier feeding an accumulator.

In this example, you perform the following activities:

■ Create a serial FIR filter using the altmult_accum megafunction and the Megawizard Plug-in Manager

■ Implement and compile the design in the Quartus II software■ Simulate the design in the Quartus II software

Generate a Multiplier-Accumulator

1. Open the altmult_accum_DesignExample.zip file and extract serial_fir.qar. In the Quartus II software, open the serial_fir.qar project and restore the archive file into your working directory.

2. Open the top-level file serial_fir.bdf. This is an incomplete file that you will complete in the course of this example.

3. Double-click on a blank area in the Block Design File (.bdf).

4. In the Symbol window, click MegaWizard Plug-In Manager.

5. On page 1 of the MegaWizard Plug-In Manager, select Create a new custom megafunction variation.

6. Click Next. Page 2a appears.



7. On page 2a, in the Installed Plug-Ins list, expand the Arithmetic folder and select ALTMULT_ACCUM (MAC) (Figure 2–14).

Figure 2–14. MegaWizard Plug-In Manager [page 2a]

8. In the Which device family will you be using? list, select Stratix II.

9. Under Which type of output file do you want to create?, select Verilog HDL.

10. Specify the output file name as <project directory>\my_mac.

11. Click Next. Page 3 appears (Figure 2–15).


Getting Started

Figure 2–15. MegaWizard Plug-In Manager ALTMULT_ACCUM (MAC) [page 3 of 10]

12. Turn off Add support for hardware saturation and rounding. This will force all inputs to be in Q1.5 format

13. In the How wide should the A input buses be? list, select 16 bits.

14. In the How wide should the B input buses be? list, select 16 bits.

15. In the How wide should the B input buses be? list, select 33 bits.

16. Turn on Create a 4th asynchronous clear input option. This forces all registers to have an associated asynchronous clear input

17. Turn off Create an associated clock enable for each clock.

18. In the What is the representation format for A inputs? list, select Signed.

19. In the What is the representation format for B inputs? list, select Signed.





21. Turn off Create a shiftout output from A input of the last multiplier.

22. Turn off Create a shiftout output from B input of the last multiplier.

23. Under Outputs Configuration, click More Options. The Ouput Register Configuration dialog box appears.

24. In the What is the source for clock input? list, select Clock0. In the What is the source for asynchronous clear input? list, select Aclr3. In the Add extra latency to the output list, select 0 (Figure 2–17).


Getting Started

Figure 2–17. Output Register Configuration Dialog Box

25. Click Done.

26. Under Adder Operation, in the What operation should be performed on outputs of the first pair of multipliers? list, select Add.

27. Under Which multiplier-adder implementation should be used?, select Use the default implementation.









Getting Started


31. Turn on Register input A of the multiplier. Click More Options. The Data A Input Register Configuration—Multiplier dialog box appears.

32. In the What is the source for clock input? list, select Clock0 and in the What is the source for asynchronous clear input? list, select Aclr3 (Figure 2–21).

Figure 2–21. Data A Input Register Configuration Dialog Box

33. Click Done.



34. Turn on Register input B of the multiplier. Click More Options. The Data B Input Register Configuratin—Multiplier dialog box appears.


Figure 2–22. Data B Input Register Configuration Dialog Box

36. Click Done.

37. In the What is the input A of the multiplier connected to? and What is the input B of the multiplier connected to? lists, select Multiplier input.

38. Turn on Register output of the multiplier. Click More Options. The Output Register Configuration—Multiplier 0 dialog box appears.


Figure 2–23. Output Register Configuration Dialog Box

40. Click Done.

41. Click Next. Page 8 appears (Figure 2–24)


Getting Started


42. Turn on Create an 'accum_sload' input port. Click More Options. The 'accum_sload' Register Configuration dialog box appears.

43. Turn on Register 'accum_sload' input and Add an extra pipeline register.

44. Under Input Register and Pipeline Register in the What is the source for clock input? list, select Clock0.

45. Under Input Register and Pipeline Register in the What is the source for asynchronous clear input? list, select Aclr3 (Figure 2–25).



Figure 2–25. 'accum_sload' Register Confirmation Dialog Box

46. Click Done.

47. Turn off Create an 'accum_sload_upper_data' input port of and Create an 'overflow' output port.

48. In the Add extra latency to the multiplier output list, select 0.

49. Click Finish. Page 10 appears (Figure 2–26).


Getting Started


50. Verify the Quartus symbol file (.bsf), and Verilog ‘Black Box’ declaration file (my_mac_bb.v) are turned on. Leave the other file options as is.

51. Click Finish. The altmult_accum module is built.

52. At the Symbol window, click OK.

53. Move the mouse to place the my_mac symbol in between the input and output ports in the serial_fir.bdf file. Click the left mouse button to place the symbol.

54. You have now completed the design file as shown in Figure 2–27.

55. On the File menu, click Save to save the design.



Figure 2–27. Complete Design File

Implement the Multiplier-Accumulator

Next, assign the Stratix II EP2S15F484C5 device to the project and compile the project. Perform the following steps:

1. On the Assignments menu, click Settings. The Settings dialog appears (Figure 2–28).


Getting Started

Figure 2–28. Settings—filtref

2. In the Category list, select Device. In the Family list, select Stratix II.

3. In the Available devices list, select EP2S15F484C5.

4. Click OK.

5. On the Processing menu, click Start Compilation to compile the design.

6. When the compilation is complete, the Full Compilation was successful message appears. Click OK.



7. On the Assignments menu, click on Timing Closure Floorplan to view how the multiplier-accumulator is implemented in the Stratix II device.

Functional Results—Simulate the Multiplier-Accumulator in Quartus

Next, simulate the design to verify the results. Set up the Quartus II Simulator settings by performing the following steps:

1. On the Processing menu, click Generate Functional Simulation Netlist.

2. When the generation is finished, the Functional Simulation Netlist Generation was successful message appears. Click OK.

3. On the Assignments menu, click Settings. The Settings dialog box appears (Figure 2–29).


Getting Started

Figure 2–29. Settings—serial_fir

4. In the Category list, select Simulator Settings.

5. In the Simulation mode list, select Functional, and in the Simulation input list, select the serial_fir.wvf file. Click Open.

6. Under Simulation period, select Run simulation until all vector stimuli are used. Click OK to close the Settings dialog box.

7. On the Processing menu, click Start Simulation, Ctrl+I, or click the Simulation button in the toolbar to run the simulation.

8. When the simulation is complete, the Simulator was successful message appears. Click OK.



9. In the Simulation Report window, view the simulation output waveforms and verify the results. Figure 2–30 shows the expected simulation results for the serial FIR filter.

Figure 2–30. my_mac Simulation Report

Functional Results—Simulate the 8-bit Multiplier Design in ModelSim-Altera

Simulate the design in ModelSim to compare the results of both simulators. Note that this ModelSim design example is for the ModelSim-Altera (Verilog) version.

This User Guide assumes that you are familiar with using ModelSim-Altera before trying out the design example. If you are unfamiliar, please refer to http://www.altera.com/support/ software/products/modelsim/mod-modelsim.html, which is a support page for ModelSim-Altera. There are various links here to topics such as installation, usage, and troubleshooting.

Set up the ModelSim-Altera simulator by performing the following steps:

1. Unzip the altmult_accum_msim.zip file to any working directory on your PC.

2. On the File menu, click Change Directory.

3. Select the folder where you have unzipped your files and click OK.

4. On the Tools menu, click Execute Macro.

5. Select serial_fir.do and click Open. This is a script file for ModelSim which automates all the necessary settings for the simulation.

6. Verify the results by looking at the Waveform Viewer window. You may need to rearrange signals, remove redundant signals, and change the radix to suit the results in the Quartus II Simulator. Figure 2–31 shows the expected simulation results in ModelSim.


Getting Started

Figure 2–31. Simulation Results in ModelSim

Conclusion The Quartus II software provides parameterizable megafunctions ranging from simple arithmetic units, such as adders and counters, to advanced phase-locked loop (PLL) blocks, multipliers, and memory structures. These megafunctions are performance-optimized for Altera devices and therefore, provide more efficient logic synthesis and device implementation, because they automate the coding process and save valuable design time. Altera recommends using these functions during design implementation so you can consistently meet your design goals.


Conclusion



Chapter 3. Specifications

Ports and Parameters

This chapter describes the ports and parameters for the altmult_accum megafunction.

The parameter details are only relevant for users who bypass the MegaWizard® Plug-In Manager interface and use the megafunction as a directly parameterized instantiation in their design. The details of these parameters are hidden from MegaWizard Plug-In Manager interface users.

f Refer to the latest version of the Quartus® II Help for the most current information on the ports and parameters for this megafunction.

Ports and Parameters for the altmult_accum Megafunction

Table 3–1 shows the input ports, Table 3–2 shows the output ports, and Table 3–3 shows the parameters of the altmult_accum megafunction.

Table 3–1. altmult_accum Megafunction Input Ports (Part 1 of 3)

Port Name

Requ

ired?

Description Comments

accum_round No Enables accumulator rounding.

This port is active high. It is available when the ACCUMULATOR_ROUNDING parameter is set to

VARIABLE. This port is available for Stratix® II devices only.

accum_saturation No Enables accumulator saturation.

This port is available when the ACCUMULATOR_SATURATION parameter is set to VARIABLE.This port is available for Stratix II devices only.

accum_sload No Causes value on the accumulator feedback path to go to zero (0) or to accum_sload_upper_data when concatenated with 0.

If the accumulator is adding and the accum_sload port is high, the multiplier output is loaded into the accumulator. If the accumulator is subtracting, the opposite (negative value) of the multiplier output is loaded into the accumulator.

accum_sload_upper_data[]

No Input for accumulator upper data bits during a synchronous load.

Input port [WIDTH_UPPER_DATA-1 DOWNTO 0]

wide. The port is available for Cyclone® II and Stratix II devices only.

3–1Preliminaryaltmult_accum Megafunction User Guide


aclr0 No The first asynchronous clear input.

—

aclr1 No The second asynchronous clear input.

—

aclr2 No The third asynchronous clear input.

—

aclr3 No The fourth asynchronous clear input.

—

addnsub No Controls the functionality of the adder.

If the addnsub port is high, the adder performs an add function; if the addnsub port is low, the adder performs a subtract function.

clock0 No The first clock input, usable by any register in the megafunction.

—

clock1 No The second clock input, usable by any register in the megafunction.

—

clock2 No The third clock input, usable by any register in the megafunction.

—

clock3 No The fourth clock input, usable by any register in the megafunction.

—

dataa[] Yes Data input to the multiplier.

Input port [WIDTH_A-1 DOWNTO 0] wide.

datab[] Yes Data input to the multiplier.

Input port [WIDTH_B-1 DOWNTO 0] wide.

ena0 No Clock enable for clock0 port.

—


—


—


—

mult_round No Enables multiplier rounding.

This port is available when the MULTIPLIER_ROUNDING parameter is set to VARIABLE. This port is available for Stratix II devices only.


Port Name

Requ

ired?



Specifications

mult_saturation No Enables multiplier saturation.

This port is available when the MULTIPLIER_SATURATION parameter is set to VARIABLE. This port is available for Stratix II devices only.

scanina[] No Input for scan chain A. Input port [WIDTH_A-1 DOWNTO 0] wide. This port is available when the INPUT_SOURCE_A parameter is set to VARIABLE or SCANA. This port is available for Cyclone II and Stratix II devices only.

scaninb[] No Input for scan chain B. Input port [WIDTH_B-1 DOWNTO 0] wide. This port is available when the INPUT_SOURCE_B parameter is set to VARIABLE or SCANB. This port is available for Cyclone II and Stratix II devices only.

signa No Specifies the numerical representation of the dataa[] port.

If the signa port is high, the multiplier treats the dataa[] port as a signed two’s complement number. If the signa port is low, the multiplier treats dataa[] port as an unsigned number.

signb No Specifies the numerical representation of the datab[] port.

If the signb port is high, the multiplier treats the datab[] port as a signed two’s complement number. If the signb port is low, the multiplier treats the datab[] port as an unsigned number.

sourcea No Input source for scan chain A and dynamically controls whether the scanina[] and dataa[] ports are fed to the multiplier.

This port is available for Cyclone II, HardCopy® II, and Stratix II devices only.

sourceb No Input source for scan chain B.

This port is available for Cyclone II, HardCopy II, and Stratix II devices only.


Port Name

Requ

ired?




Table 3–2. altmult_accum Megafunction Output Ports

Port Name

Requ

ired?


accum_is_saturated No Signal that indicates when accumulator saturation occurs.

This port is available when the PORT_ACCUM_IS_ SATURATED parameter is set to USED. This port is available for Stratix II devices only.

mult_is_saturated No Signal that indicates when multiplier saturation occurs.

This port is available when the PORT_MULT_IS_ SATURATED parameter is set to USED. This port is available for Stratix II devices only.

overflow No Overflow port for the accumulator.

—

result[] Yes Accumulator output port.

Output port [WIDTH_RESULT-1 DOWNTO 0] wide.

scanouta[] No Output of the first shift register.

Output port [WIDTH_A-1 DOWNTO 0] wide. When instantiating the altmult_accum megafunction with the MegaWizard Plug-In Manager from the Tools menu, the MegaWizard Plug-In Manager renames the scanouta[] port to shiftouta port.

scanoutb[] No Output of the second shift register.

Output port [WIDTH_B-1 DOWNTO 0] wide. When instantiating the altmult_accum megafunction with the MegaWizard Plug-In Manager from the Tools menu, the MegaWizard Plug-In Manager renames the scanoutb[] port to shiftoutb port.

Table 3–3. altmult_accum Megafunction Parameters (Part 1 of 8)

Parameter Type

Requ

ired?

Comments

ACCUM_DIRECTION String No Specifies whether the accumulator performs an add or subtract function. Values are "ADD" and "SUB". When parameter is set to "ADD", the accumulator adds the product to the current accumulator value. When this parameter is set to "SUB", the accumulator subtracts the product from the current accumulator value. If omitted, the default is "ADD". The parameter is ignored if the addnsub port is used.

ACCUM_ROUND_ACLR String No Specifies the asynchronous clear port for the accum_round port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". This parameter is available for Stratix II devices only.


Specifications

ACCUM_ROUND_PIPELINE_ACLR

String No Specifies the asynchronous clear port for the “second stage” accum_round port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". This parameter is available for Stratix II devices only.

ACCUM_ROUND_PIPELINE_REG String No Specifies the clock port for the “second stage” accum_round port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is available for Stratix II devices only.

ACCUM_ROUND_REG String No Specifies the clock port for the accum_round port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is available for Stratix II devices only.

ACCUM_SATURATION_ACLR String No Specifies the asynchronous clear port for the accum_saturation port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". This parameter is available for Stratix II devices only.

ACCUM_SATURATION_PIPELINE_ACLR

String No Specifies the asynchronous clear port for the “second stage” accum_saturation port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". This parameter is available for Stratix II devices only.

ACCUM_SATURATION_PIPELINE_REG

String No Specifies the clock port for the “second stage” accum_saturation port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is available for Stratix II devices only.

ACCUM_SATURATION_REG String No Specifies the clock port for the accum_saturation port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is available for Stratix II devices only.

ACCUM_SLOAD_ACLR String No Specifies the asynchronous clear signal for the accum_sload port. Values are "ACLR0", "ACLR1", "ACLR2", and "ACLR3". If omitted, the default is "ACLR3". This parameter is ignored if the accum_sload port is unused.

ACCUM_SLOAD_PIPELINE_ACLR

String No Specifies the asynchronous clear port for the second register on the accum_sload port. Values are "ACLR0", "ACLR1", "ACLR2", and "ACLR3". If omitted, the default is "ACLR3". This parameter is available for Stratix II devices only.


Parameter Type

Requ

ired?

Comments



ACCUM_SLOAD_PIPELINE_REG String No Specifies the clock signal for the second register on the accum_sload port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is ignored if the accum_sload port is unused.

ACCUM_SLOAD_REG String No Specifies the clock signal for the accum_sload port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is ignored if the accum_sload port is unused.

ACCUM_SLOAD_UPPER_DATA_ACLR

String no Specifies the asynchronous clear port for the accum_sload_ upper_data port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". This parameter is available for Cyclone II and Stratix II Cyclone II devices only.

ACCUM_SLOAD_UPPER_DATA_PIPELINE_ACLR

String No Specifies the asynchronous clear port for the “second stage” accum_sload_upper_data port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and “CLOCK3“. This parameter is available for Cyclone II and Stratix II devices only.

ACCUM_SLOAD_UPPER_DATA_PIPELINE_REG

String No Specifies the asynchronous clear port for the “second stage” accum_sload_upper_data port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is available for Cyclone II and Stratix II devices only.

ACCUM_SLOAD_UPPER_DATA_REG

String No Specifies the clock port for the accum_sload_upper_data port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is “CLOCK0“. This parameter is available for Cyclone II and Stratix II devices only.

ACCUMULATOR_ROUNDING String No Specifies the accumulator rounding. Values are "NO", "YES", and "VARIABLE". If omitted, the default is "NO". This parameter is available for Stratix II devices only.

ACCUMULATOR_SATURATION String No Specifies the accumulator saturation. Values are "NO", "YES", and "VARIABLE". If omitted, the default is "NO". This parameter is available for Stratix II devices only.


Parameter Type

Requ

ired?

Comments


Specifications

ADDNSUB_ACLR String No Specifies the asynchronous clear for the addnsub port. Values are "ACLR0", "ACLR1", "ACLR2", and "ACLR3". If omitted, the default is "ACLR0". This parameter is ignored if the addnsub port is unused.

ADDNSUB_PIPELINE_ACLR String No Specifies the asynchronous clear for the second register on the addnsub port.Values are "ACLR0", "ACLR1", "ACLR2", and "ACLR3". If omitted, the default is "ACLR0". This parameter is ignored if the addnsub port is unused.

ADDNSUB_PIPELINE_REG String No Specifies the clock for the second register on the addnsub port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is ignored if the addnsub port is unused.

ADDNSUB_REG String No Specifies the clock for the addnsub port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is ignored if addnsub port is unused.

DEDICATED_MULTIPLIER_CIRCUITRY

String No Specifies whether to use dedicated multiplier circuitry. Values are "AUTO", "ON", and "OFF". If omitted, the default is "AUTO". This parameter is available for Cyclone II, HardCopy Stratix, Mercury™, Stratix, Stratix II and Stratix GX devices only.

DSP_BLOCK_BALANCING String No Specifies whether to use DSP block balancing. Values are "UNUSED", "Auto", "DSP blocks", "Logic Elements", "Off", "Simple 18-bit Multipliers", "Simple Multipliers", and "Width 18-bit Multipliers".

EXTRA_ACCUMULATOR_LATENCY

String No Adds the number of clock cycles of latency, specified by the OUTPUT_REG parameter, to the accumulator portion of the DSP block.

EXTRA_MULTIPLIER_LATENCY String No Specifies the number of clock cycles of latency for the multiplier portion of the DSP block. If the MULTIPLIER_REG parameter is specified, the specified clock port is used to add the latency. If the MULTIPLIER_REG parameter is set to "UNREGISTERED", the clock0 port is used to add the latency.

INPUT_ACLR_A String No Specifies the asynchronous clear port for dataa[] port. Values are "ACLR0", "ACLR1", "ACLR2", and "ACLR3". If omitted, the default is "ACLR3".


Parameter Type

Requ

ired?

Comments



INPUT_ACLR_B String No Specifies the asynchronous clear port for the datab[] port. Values are "ACLR0", "ACLR1", "ACLR2", and "ACLR3". If omitted, the default is "ACLR3".

INPUT_REG_A String No Specifies the clock port for the dataa[] port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0".

INPUT_REG_B String No Specifies the clock port for the datab[] port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0".

INPUT_SOURCE_A String No Specifies the input port for the dataa[] port. Values are "DATAA", "SCANA", and "VARIABLE". If omitted, the default is "DATAA". This parameter is available for Cyclone II and Stratix II devices only.

INPUT_SOURCE_B String No Specifies the input port for the datab[] port. Values are "DATAA", "SCANA", and "VARIABLE". If omitted, the default is "DATAA". This parameter is available for Cyclone II and Stratix II devices only.

INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes. Create the altmult_accum megafunction with the MegaWizard Plug-In Manager to calculate the value for this parameter.

LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".

LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.

MULT_ROUND_ACLR String No Specifies the asynchronous clear port for the mult_round port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "UNREGISTERED". This parameter is available for Stratix II devices only..

MULT_ROUND_REG String No Specifies the clock port for the mult_round port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is available for Stratix II devices only..

MULT_SATURATION_ACLR String No Specifies the asynchronous clear port for the mult_saturation port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "UNREGISTERED". This parameter is available for Stratix II devices only.


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MULT_SATURATION_REG String No Specifies the clock port for the mult_saturation port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is available for Stratix II devices only.

MULTIPLIER_ACLR String No Specifies the asynchronous clear signal for the register immediately following the multiplier. Values are "ACLR0", "ACLR1", "ACLR2", and "ACLR3". If omitted, the default is "ACLR3".

MULTIPLIER_REG String No Specifies the clock signal for the register immediately following the multiplier. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0".

MULTIPLIER_ROUNDING String No Specifies multiplier rounding. Values are "NO", "YES", and "VARIABLE". If omitted, the default is "NO". This parameter is available for Stratix II devices only.

MULTIPLIER_SATURATION String No Specifies multiplier saturation. Values are "NO", "YES", and "VARIABLE". If omitted, the default is "NO". This parameter is available for Stratix II devices only.

OUTPUT_ACLR String No Specifies the asynchronous clear signal for the registers on the outputs. Values are "ACLR0", "ACLR1", "ACLR2", and "ACLR3". If omitted, the default is "ACLR3".

OUTPUT_REG String No Specifies the clock signal for the registers on the outputs. Values are "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0".

PORT_ACCUM_IS_SATURATED String No Specifies whether to use the mult_is_saturated output port. Values are "UNUSED" and "USED". If omitted, the default is "UNUSED". This parameter is available for Stratix II devices only.

PORT_ADDNSUB String No Specifies the usage of the addnsub input port. Values are:"PORT_USED" = Port is treated as used"PORT_UNUSED" = Port is treated as unused"PORT_CONNECTIVITY" = Port usage is determined by checking the port connectivity

If omitted, the default is "PORT_CONNECTIVITY".

PORT_MULT_IS_SATURATED String No Specifies whether to use the accum_is_saturated output port. Values are "UNUSED" and "USED". If omitted, the default is "UNUSED". This parameter is available for Stratix II devices only.


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PORT_SIGNA String No Specifies the usage of the signa input port. Values are:"PORT_USED" = Port is treated as used"PORT_UNUSED" = Port is treated as unused"PORT_CONNECTIVITY" = Port usage is determined by checking the port connectivity


PORT_SIGNB String No Specifies the usage of the signb input port. Values are:"PORT_USED" = Port is treated as used"PORT_UNUSED" = Port is treated as unused"PORT_CONNECTIVITY" = Port usage is determined by checking the port connectivity


REPRESENTATION_[] String No Parameter [A,B]. Specifies the numerical representation of the corresponding data[] port. Values are "UNSIGNED" and "SIGNED". When this parameter is set to "UNSIGNED", the accumulator interprets the dataa input as an unsigned number. When this parameter is set to "SIGNED", the accumulator interprets the dataa input as a signed two's complement number. If omitted, the default is "UNSIGNED". This parameter is ignored if the signa port is used.

SIGN_ACLR_[] String No Parameter [A,B]. Specifies the asynchronous clear signal for the first register on the corresponding sign[] port. Values are "ACLR0", "ACLR1", "ACLR2", and "ACLR3". If omitted, the default is "ACLR3". This parameter is ignored if the corresponding sign[] port is unused.

SIGN_PIPELINE_ACLR_[] String No Parameter [A,B]. Specifies the asynchronous clear signal for the second register on the corresponding sign[] port. Values are "ACLR0", "ACLR1", "ACLR2", and "ACLR3". If omitted the default is ACLR3. This parameter is ignored if the corresponding sign[] port is unused.

SIGN_PIPELINE_REG_[] String No Parameter [A,B]. Specifies the clock signal for the second register on the corresponding sign[] port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is ignored if the corresponding sign[] port is unused.


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SIGN_REG_[] String No Parameter [A,B]. Specifies the clock signal for the first register on the corresponding sign[] port. Values are "UNREGISTERED", "CLOCK0", "CLOCK1", "CLOCK2", and "CLOCK3". If omitted, the default is "CLOCK0". This parameter is ignored if the corresponding sign[] port is unused.

WIDTH_A Integer Yes Width of the dataa[] port.

WIDTH_B Integer Yes Width of the datab[] port.

WIDTH_RESULT Integer Yes Width of the result[] port.

WIDTH_UPPER_DATA Integer No Width of accum_sload_upper_data[] port. This parameter is available for Cycone II and Stratix II devices only.


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Documents

altmult accum Megafunction User Guide - Intel...1–2 Altera Corporation altmult_accum Megafunction User Guide March 2007 Features Features The altmult_accum megafunction implements