ALTERA UP2Tutorial 1: The 15 Minute Design

Figure 1.1 The Altera UP 1 CPLD development board.

ALTERA UP2Tutorial 1: The 15 Minute Design

Design Compilation Simulation Verifcation

Graphical Entry

HDL Entry

Compiler

Timing Diagram

Timing Analysis

Program CPLD

UP 1 Development Board

Figure 1.2 Design process for schematic or VHDL entry.

ALTERA UP2Tutorial 1: The 15 Minute Design

Figures 2.1 The Altera UP 2 board.

FLEX_EXPAN_C

FLEX_10K

EPF10K20RC240-4 DAA239837

R

R

Mouse

25.175 MHzCLOCK

FLEX_EXPAN_AFLEX_PB1 FLEX_PB2

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

DC_IN FLEX_DIGIT

U1

JTAG_OUT

POWER TCK

MAX_SW1 MAX_SW2

EMP7128SLC84-7 BFD329837

R

R

VGAAdapter

P1

P2

P3P4

P9 P10P6P5

P7 P8

EPC

Figures 2.1 The Altera UP 2 board.

MAX FLEX

Table 2.1 UP 2 device selection jumpers for programming.

MSD LSD

a

b

c

d

e

fg

dp

a

b

c

d

e

fg

dp

Figure 2.3 MAX and FLEX seven-segment LED display segment names.

Pin Name Pin Type Pin Function of Pin

MSD_dp OUTPUT PIN 14 Most Significant Digit of Seven-segment Display - Decimal Point Segment (0 = LED ON, 1 = LED OFF)

MSD_g OUTPUT PIN 13 MSD Display Segment G (0 = LED ON, 1 = LED OFF)

MSD_f OUTPUT PIN 12 MSD Display Segment F (0 = LED ON, 1 = LED OFF)

MSD_e OUTPUT PIN 11 MSD Display Segment E (0 = LED ON, 1 = LED OFF)

MSD_d OUTPUT PIN 9 MSD Display Segment D (0 = LED ON, 1 = LED OFF)

MSD_c OUTPUT PIN 8 MSD Display Segment C (0 = LED ON, 1 = LED OFF)

MSD_b OUTPUT PIN 7 MSD Display Segment B (0 = LED ON, 1 = LED OFF)

MSD_a OUTPUT PIN 6 MSD Display Segment A (0 = LED ON, 1 = LED OFF)

LSD_dp OUTPUT PIN 25 Least Significant Digit of Seven-segment Display - Decimal Point Segment (0 = LED ON, 1 = LED OFF)

LSD_g OUTPUT PIN 24 LSD Display Segment G (0 = LED ON, 1 = LED OFF)

LSD_f OUTPUT PIN 23 LSD Display Segment F (0 = LED ON, 1 = LED OFF)

LSD_e OUTPUT PIN 21 LSD Display Segment E (0 = LED ON, 1 = LED OFF)

LSD_d OUTPUT PIN 20 LSD Display Segment D (0 = LED ON, 1 = LED OFF)

LSD_c OUTPUT PIN 19 LSD Display Segment C (0 = LED ON, 1 = LED OFF)

LSD_b OUTPUT PIN 18 LSD Display Segment B (0 = LED ON, 1 = LED OFF)

LSD_a OUTPUT PIN 17 LSD Display Segment A (0 = LED ON, 1 = LED OFF)

FLEX_switch_1 INPUT PIN 41 FLEX DIP Switch Input 1 (1 = Open, 0 = Closed)

FLEX_switch_2 INPUT PIN 40 FLEX DIP Switch Input 2 (1 = Open, 0 = Closed)

FLEX_switch_3 INPUT PIN 39 FLEX DIP Switch Input 3 (1 = Open, 0 = Closed)

FLEX_switch_4 INPUT PIN 38 FLEX DIP Switch Input 4 (1 = Open, 0 = Closed)

FLEX_switch_5 INPUT PIN 36 FLEX DIP Switch Input 5 (1 = Open, 0 = Closed)

FLEX_switch_6 INPUT PIN 35 FLEX DIP Switch Input 6 (1 = Open, 0 = Closed)

FLEX_switch_7 INPUT PIN 34 FLEX DIP Switch Input 7 (1 = Open, 0 = Closed)

FLEX_switch_8 INPUT PIN 33 FLEX DIP Switch Input 8 (1 = Open, 0 = Closed)

PB1 INPUT PIN 28 Push-Button 1 (non–debounced, 0 = button depressed)

PB2 INPUT PIN 29 Push-Button 2 (non–debounced, 0 = button depressed)

Horiz_Sync OUTPUT PIN 240 VGA Video Signal - Horizontal Synchronization

Vert_Sync OUTPUT PIN 239 VGA Video Signal - Vertical Synchronization

Blue OUTPUT PIN 238 VGA Video Signal - Blue Video Data

Green OUTPUT PIN 237 VGA Video Signal - Green Video Data

Red OUTPUT PIN 236 VGA Video Signal - Red Video Data

PS2_CLK BIDIRECTIONAL 30 Clock line for PS/2 Mouse and Keyboard

PS2_DATA BIDIRECTIONAL 31 Data line for PS/2 Mouse and Keyboard

Clock INPUT PIN 91 25.175 MHz System Clock on low skew Global Clock Line

Table 2.4 UP 2 Board 10K20RC240 FLEXCHIP I/O pin assignments.

Pin Name Pin Type Pin Function of Pin

MSD_dp OUTPUT PIN 68 Most Significant Digit of Seven-segment Display Decimal Point Segment (0 = LED ON, 1 = LED OFF)

MSD_g OUTPUT PIN 67 MSD Display Segment G (0 = LED ON, 1 = LED OFF)

MSD_f OUTPUT PIN 65 MSD Display Segment F (0 = LED ON, 1 = LED OFF)

MSD_e OUTPUT PIN 64 MSD Display Segment E (0 = LED ON, 1 = LED OFF)

MSD_d OUTPUT PIN 63 MSD Display Segment D (0 = LED ON, 1 = LED OFF)

MSD_c OUTPUT PIN 61 MSD Display Segment C (0 = LED ON, 1 = LED OFF)

MSD_b OUTPUT PIN 60 MSD Display Segment B (0 = LED ON, 1 = LED OFF)

MSD_a OUTPUT PIN 58 MSD Display Segment A (0 = LED ON, 1 = LED OFF)

LSD_dp OUTPUT PIN 79 Least Significant Digit of Seven-segment Display Decimal Point Segment (0 = LED ON, 1 = LED OFF)

LSD_g OUTPUT PIN 77 LSD Display Segment G (0 = LED ON, 1 = LED OFF)

LSD_f OUTPUT PIN 75 LSD Display Segment F (0 = LED ON, 1 = LED OFF)

LSD_e OUTPUT PIN 76 LSD Display Segment E (0 = LED ON, 1 = LED OFF)

LSD_d OUTPUT PIN 74 LSD Display Segment D (0 = LED ON, 1 = LED OFF)

LSD_c OUTPUT PIN 73 LSD Display Segment C (0 = LED ON, 1 = LED OFF)

LSD_b OUTPUT PIN 70 LSD Display Segment B (0 = LED ON, 1 = LED OFF)

LSD_a OUTPUT PIN 69 LSD Display Segment A (0 = LED ON, 1 = LED OFF)

PB1 INPUT PIN * Push-Button 1 (non–debounced, 0 = button depressed)

PB2 INPUT PIN * Push-Button 2 (non–debounced, 0 = button depressed)

D1..D16 LEDs OUTPUT PIN *

16 Discrete LEDs - D1…D16

(0 = LED ON, 1 = LED OFF)

SW1 & SW2 INPUT PIN *

MAX DIP Switch Inputs - SWxS1...SWxS8

(1 = Open, 0 = Closed)

Clock INPUT PIN 83 25.175Mhz System Clock on low skew

Global Clock Line

Prototyping Header

Pins

INPUT, OUTPUT 1-84

Black Prototyping Headers next to MAX chip

Numbers are silk-screened on board.

Pins 12, 33, 54, 75, and 83 are not available.

* Jumper wires from the switch or LED to the MAX prototyping headers are required to use these devices.

Any available unused MAX header pin can be assigned to this device.

Note: A number of other pins are pre-assigned and required for programming, power, and ground connections.

Full Custom

Standard Logic

Progammable Logic (FPLDs) ASICs

Digital Logic

TTL 74xx

CMOS 4xxx

PLDs FPGAs

Gate Arrays

Microprocessor & RAM

Standard Cell

CPLDs

Figure 3.1 Digital logic technologies.

PLDs

ASICs

Full CustomVLSI Design

Speed,Density,Complexity,MarketVolumeneeded forProduct

Engineering Cost, Time to Develop Product

CPLDsFPGAs

Figure 3.2 Digital logic technology tradeoffs.

Figure 3.3 Using a PLA to implement a Sum of Products equation.

Figure 3.4 Examples of FPLDs and advanced high pin count package types.

Product-TermSelectMatrix

ClearSelect

Clock/EnableSelect

VCC

PRN

CLRN

ENA

D Q

GlobalClear

GlobalClock

To I/OControl

Block

To PIA

This respresents amultiplexercontrolled by theconfigurationprogram

ProgrammableRegister

36 Signalsfrom PIA

16 ExpanderProduct

Shared LogicExpanders

LAB Local Array

Parallel LogicExpanders(from othermacrocells)

Figure 3.5 MAX 7000 macrocell.

ALTERA MAX 7000 Architecture

Input/GCLK1Input/OE2/GCLK2

Input/OE1

LAB A

Macrocells1-166-

6-16

16

6-16

I/OControlBlock

6-16I/O Pins

3

LAB C

Macrocells33-486-

6-16

16

6-

I/OControlBlock

6-16I/O Pins

3

LAB B

LAB D

Macrocells17-32

Macrocells49-64

6-16

1

3

6-16

1

3

6-16I/O Pins

6-16I/O Pins

I/OControlBlock

I/OControlBlock

6

6

6

6

PIA

6 OutputInput/GCLRn

6 Output

6-

6-16

6-

6-

Figure 3.6 MAX 7000 CPLD architecture.

ALTERA MAX 7000 Architecture

Figure 3.7 FLEX 10K100 FPLD die photo, PIA interconnects are visible.

PRN

CLRN

ENA

D Q

Programmable Register

DATA1DATA2DATA3DATA4

LABCTRL1LABCTRL2

Chip-WideReset

LABCTRL3LABCTRL4

Look-UpTable(LUT)

CarryChain

CascadeChain

To FastTrackInterconnect

To LAB LocalInterconnect

Clear/PresetLogic

Clock Select

CarryOut

CascadeOut

Register BypassCarry

InCascade

In

Figure 3.8 FLEX 10K Logic Element (LE).

4 InputLUT

(16 x 1 RAM)

ABCD

F

A

B

C

D

F

RAM Contents Address Data

A B C D F 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1

Figure 3.9 Using a lookup table (LUT) to model a gate network.

LE1LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

Carry-In andCascade-In Column-to-Row

Interconnect

Row Interconnect

Dedicated Inputs &Global Signals

LogicBlockArray(LAB)

4

4

4

4

4

4

4

4

4

8

616

4

Carry-Out and Cascade-Out2

2

4

8 24

168

Figure 3.10 FLEX 10K Logic Array Block (LAB).

I/O Element(IOE)

IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE

IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOERow

LocalInterconnect

Logic Element(LE)

Logic ArrayBlock (LAB)

EAB

EAB

Logic Array

EmbeddedArray Block(EAB)2K Bits RAM

Row

Figure 3.11 FLEX 10K CPLD architecture.

Figure 3.12 Silicon wafer containing XC4010E 10,000 gate FPGAs.

XILINX 4000 Architecture– A LU Table FPGA

Figure 3.13 Single XC4010E FPGA die showing 20 by 20 array of logic elements and interconnect.

XILINX 4000 Architecture– A LU Table FPGA

Look-UpTable(LUT)

G4G3G2G1

Look-UpTable(LUT)

F4F3F2F1

Look-UpTable(LUT)

S/RControl

S/RControl

H1 DIN/H2 ECSR/H0

1

1

D

EC

SD

RD

Q

D

EC

SDQ

RD

RegisterBypass

RegisterBypass

ProgrammableRegister

ProgrammableRegister

YQ

Y

XQ

X

4C1 • • • C4

K(Clock)

Figure 3.14 Xilinx 4000 Family Configurable Logic Block (CLB).

DeviceProgrammingSimulationDevice

FittingTranslationDesign

EntryOptimization &

Synthesis

Figure 3.15 CAD tool design flow for Field Programmable Logic Devices (FPLDs).

Figure 4.1 The tutor2.gdf schematic.

Chapter 4: Tutorial II

Figure 4.2 8COUNT symbol online help file

Figure 4.3 Internal VHDL code for dec-7seg function.

Figure 4.4 Hierarchy display of the tutor2 design.

. Figure 4.5 Enlarged view of tutor2 design showing bus connections.

Figure 4.6 Timing analysis using Registered Performance option.

Figure 4.7 Oscilloscope display of pushbutton switch contact bounce.

Figure 4.8 Modified tutor2 design schematic.