Allegro Sigrity SI / PI Overview - Parallel Systems...Allegro Sigrity Signal Integrity Solutions –Allegro SI Base + Option Allegro Sigrity SI Base −Power-Aware SI Option −Serial

1 © 2012 Cadence Design Systems, Inc. All rights reserved.

Brad Griffin

Allegro Product Marketing

February, 2015

Allegro Sigrity SI / PI Overview


Agenda

Allegro Sigrity Signal Integrity Solutions – Allegro SI Base + Option

Allegro Sigrity SI Base

− Power-Aware SI Option

− Serial Link Analysis Option

− Package Assessment Option

Allegro Sigrity Power Integrity Solutions – Allegro PI Base + Options

Allegro Sigrity PI Base

− Signoff and Optimization Option




Allegro Sigrity Signal Integrity Solution Base + Option


• Allegro Sigrity SI Base product enables constraint driven design

• Options for detailed analysis, compliance and assessment


Allegro Sigrity SI – (Base)

Allegro Sigrity SI – PA 5700

• New product (PA5700) integrating Allegro and Sigrity technology for SI analysis of

PCB, IC Package or SiP designs

• Enables Constraint Driven Design− Layout floorplanning /editing, schematic-level topology exploration and TD SI simulation,

constraint development/capture, analysis model library management, design translators … SI related ERCs


Allegro Sigrity SI and Allegro PCB Editor - Integration


• Allegro Sigrity SI integrates with the same constraint manager used throughout the design process

• Drive electrical constraints into the design– Validate throughout the design process

Constraint-driven design streamlines final verification - Enables first-pass success

Logical Design Physical DesignHigh Speed Design


Impedance, Coupling, and Trace Reference Check Output

HTML reports, sortable

tables, various plots


Allegro Sigrity SI Summary:Integrated high-speed design and analysis

No manual translation is

required to analyze selected

signals from the physical board

or extract them into the

SigXplorer module. Analysis

results are reported in the

same constraint manager used

by Allegro PCB Editor.

Coupled differential pairs and

nets extended through discrete

components (x-nets) are

automatically identified,

analyzed, and/or extracted.

Summary: Allegro Sigrity SI


Allegro Sigrity SI BaseAllegro Sigrity SI Base

Power Aware Memory Interface Design and Analysis




Power Aware Memory Interface Design and Analysis

Key features of Allegro Sigrity Power-Aware SI Option

• Allegro Sigrity Power-Aware SI addresses the challenges associated with source

synchronous bus design

• Industry-leading interconnect extraction and power-aware IBIS modeling

technology includes the non-ideal power and ground effects

• Concurrent simulation of signal, power, and ground accurately determine Setup

and Hold margins

• Comprehensive, automated JEDEC-based measurements and post-processing

• Easy-to-use environment featuring popular memory interface compliance kits is

highly integrated with layout allowing engineers to efficiently close on memory interface

timing

Note: Package and Chipextraction technology sold separately from Allegro Sigrity Power-Aware SI Option


• PowerSI provides efficient PCB interconnect extraction

• Integrates with IC and Package– XtractIM Package models drop into topology canvas

– XcitePI IO Interconnect models drop into topology canvas

• MCP (Model Connection Protocol) connects signal, power, and ground across fabrics

System level power-aware SI analysis solution

Extraction Connection Simulation


Reflections, Xtalk, SSO Simulated Together

• Emulates your hardware


Automatic Setup & Hold Derating

• Slew rates measured

on each cycle

• Derating factor is

pulled from table

• Applied to setup/hold

margins each cycle


Automation

• Raw waveforms measured like a virtual oscilloscope

• Tabulated reports for:– Waveform quality

– Eye quality

– Setup & hold

– Delays & skews

• Criteria plots, waveforms, eye diagrams all linked to HTML reports


• Industry’s most complete timing analysis and timing documentation tool now reads interconnect delay directly from Cadence Sigrity Parallel Bus Analysis solution

– Automatically generate timing diagrams from power-aware Sigrity simulation results

– TimingDesigner available from EMA Design Automation

• Graphical timing spreadsheets show full interface timing relationships

• DDR Timing Spreadsheets enable confirmation of timing closure

• TimingDesigner and Allegro Sigrity Power Aware SI Option - the industry’s most complete timing analysis and timing reporting solution

TimingDesigner Integration with Sigrity


• DDR4/LPDDR4 is faster and lower voltage than its predecessor

• Analysis methodology for DDR4 differs from its predecessor– The Allegro Sigrity Power Aware SI solution

address these new requirements

• New features include – The ability to derive and evaluate DDR4 DQ

eye masks,

– Derive Vref level on-the-fly

– Bit error rate (BER) testing

– AMI models for equalization

DDR4/LPDDR4 Support in Power Aware SI Option / SystemSI PBA

DDR4 Spec

SystemSI-PBA



Multi-Gigabit Serial Link Design and Analysis




• Allegro Sigrity Serial Link SI is addressing the challenges associated with serial link design

• Industry-leading interconnect extraction technology provides an accurate and uniquely integrated solution for channel modeling, including non-ideal power effects

• Robust frequency and time domain simulation technology is combined with statistical techniques for advanced multi-gigabit channel analysis

• Industry-leading IBIS-AMI modeling expertise enables advanced channel simulation with algorithmic equalization modeling (ex. FFE, DFE ..)

• Automated eye diagram and bathtub generation for Bit Error Rate (BER) analysis

Multi-Gigabit Serial Link Design and Analysis


Allegro Sigrity Serial Link SI – Serial Link Analysis

• Provides a comprehensive environment for design and accurate

assessment of high speed serial links to ensure robust IC package and

PCB implementations


Sweep Manager

• Enables sweeping of key parameters:– Jitter/Noise settings

– Equalization parameters

– Channel interconnect models

– Subcircuit parameters


Interface Compliance Flow


Interface compliance Results

Eye Mask

Insertion Loss

Return Loss

Jitter tolerance

Printout ready

Hyperlinked to

curves for easy

access


Allegro Sigrity Serial Link Solution is Power Aware


• Compliance kits– USB 3.0 and MIPI-M

New compliance kits for popular Serial interfaces


• Adding HDMI 2.0 (up to 6Gbps) compliance kit to existing HDMI 1.4b version

• Adding support for “TP2” compliance checks

HDMI 2.0 Compliance Kit




Allegro Sigrity Package Assessment and Model Extraction – IC Package Design and Analysis



• Common environment between layout and analysis– Issues can be resolved easily

– All design data is available for analysis tools– No limitations that may exist translating from manufacturing data (ODB++)

Package Assessment and Model Extraction


• Package Analyze option enables XtractIM integration

Running XtractIM from Allegro Sigrity SI Base


• Package database is translated into SPD in ASI before running XtractIM

Automatic Translation to XtractIM (.mcm to .spd)


XtractIM Running from Allegro Sigrity SIEdits can be made in base tool and quickly investigated in XtractIM


Detailed Full Wave 3D Extraction FlowAutomated cutting of 3D regions with PowerSI 3D-EM


Solution AccuracyMeasurement Benchmark

Two long traces with via

stubs in a 28-layer board

S11

S12

Red : measurement

Blue : PSI-3D EM


PowerSI 3D EMLow Frequency Solution Stability and Accuracy

Resistance

Inductance


Package Partitioning Approach Accelerates the time to create full Package Models with 3D-EM

• XtractIM (Hybrid Solver) is

effective on multi-layer packages

with power and ground planes

• Lower cost packages may not be

“plane rich” but still require

accurate modeling

− 3D Full-wave can provide a full

package model by partitioning the

package and solving each partition

− Individual simulation results are

combined together to generate a whole

package RLC table and SPICE model.

Get each net’s strong neighbors

by Hybrid -Solver

Divide package to groups of SPD

files for 3DEM

3DEM-extraction for individual SPD

files

Combine individual result into

whole package RLC



Allegro Sigrity Signal Integrity Solution Base + Option





Agenda

Allegro Sigrity Power Integrity Solutions – Allegro PI Base + Options


− Signoff and Optimization Option


Allegro Sigrity Signal Integrity Solutions – Allegro SI Base + Option


− Power-Aware SI Option

− Serial Link Analysis Option



Allegro Sigrity Power Integrity Solution Base + Option


• Allegro Sigrity PI Base product enables constraint driven PI design

• Option for cost-performance optimization and detailed analysis


Allegro Sigrity PI – PA 5800

• New product (PA5800) integrating Allegro and Sigrity technology for

PI analysis of PCB, IC Package or SiP designs• Sigrity engines will be called for analysis

• IR Drop analysis (as part of PI Base license)

• OptimizePI (as part of Signoff & Optimization option)

• Enables Constraint Driven Design• Integrated solution for layout and analysis

• Target users• Mostly layout designers

• Some hardware engineers

• A few SI engineers

Allegro Sigrity PI – (Base)


• Constraint driven flow associated decoupling capacitors with components

• Constraint templates advise layout designer on capacitor placement

• IR Drop analysis provides feedback regarding plane design

Constraint Driven Power Integrity design for PCBs and IC Packages

For PCB Designers, IC Package Designers, and Power Integrity

engineers needing to perform a quick scan of a design for

potential power integrity issues

PI B

ase

New Power Integrity constraint-driven

flow guides the layout designer on

decoupling capacitor placement


Key Components of PI Base

Floorplanner DC Analysis

Constraint Manager

Power Feasibility Editor

• Allegro based editor for .brd, .mcm,

or .sip

• Layout editing and routing

• Sigrity technology

with cross-probing

to layout

• New unique constraint

driven DeCap flow


Industry’s First Complete F2B Constraint-Driven PI Design Process

Design Engineer

• Can start at BOM stage

• Uses new Power Feasibility Editor for DeCap selection and PI constraint definition

Layout Designer

• Can start at floorplanning stage

• First order analysis directly on layout

• Analyze, edit, re-analyze

• DeCap placement guidance and DRC

PI Engineer

• Can start at any stage

• Leverages setup and data from rest of team

• Signoff capable analysis


Allegro Sigrity PI Module

• An add-on module to Allegro / SiP Layout Designers

• Available through “Change Editor”

• Easy to use and integrated analysis for making on-the-fly changes to layout

based on PI Analysis

• An integrated foundation for Sigrity technologies - Launching of Sigrity products from

layout environment, automatically passing layout data and setup to Sigrity individual

products

• PI Experts may change the design, re-analyze with advance Sigrity PI tools, and

save a local copy of improved design

Main Functions :

• PCB IR drop analysis and current density checks for metal planes, vias and traces

• Power Feasibility Editor to allow specifications of decoupling capacitor needs and

constraints on decoupling capacitor placements for each IC components

• Interactive decoupling capacitor placement environment to facilitate layout engineers

to place capacitors within specified constraints


Allegro Sigrity Power Integrity Solution Optimization and Signoff Option


• Signoff option includes industry leading AC Analysis, DC Analysis,

and decoupling capacitor optimization


• PowerSI for AC analysis

• PowerDC for thermally-aware IR Drop analysis

• OptimizePI for decoupling capacitor cost/performance tradeoffs

• 3D-EM for 3D full-wave PDN extraction

New comprehensive Power Integrity Solution integrated with PCB and Package Layout

For Power Integrity engineers requiring AC and DC analysis

Reduce costs while maximizing PDN performance by selecting

the optimal decoupling capacitors placed in the best location

Sig

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ff and

Op

tim

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Op

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Integrated design and PI Analysis


Electrical / Thermal Co-Simulation Flow

Current density is

an input for heat

transfer analysis

Temperature is an

input for DC current

analysis

PowerDC

The first integrated and automated electrical /

thermal co-simulation tool in industry

Both electrical resistance and

leakage power dissipation

increase at higher temperatures

Joule and component

heating will change

temperature distribution

Iteration

Heat Transfer Analysis

temperature

DC Current Analysis

Current density


Power Integrity

Thermally-aware static IR Drop can be performed with an intuitive user interface.

Engineers can verify power delivery and signal quality with tools from a single vendor.


• Sigrity Power Integrity technology performs AC analysis– Integrated (no manual translation)

design and analysis environment helps optimize decoupling strategy

• Frequency domain simulation– Quantify the impedance of the power

delivery system across the frequency range of interest

• Time domain simulation

– Effectiveness of decoupling capacitor selection and placement can be verified by measuring and optimizing ripples in the voltages

Optimize power stability through AC power analysis

Note: SPEED2000 time domain simulation

technology sold separately from Allegro Sigrity

Optimization and Signoff Option


• Sigrity Power DC includes static IR drop analysis– Verifies the power distribution system will provide

stable and sufficient current to drive signals

– Considers trace neck-down, swiss-cheese planes, partial planes

– Considers all vias that connect multiple ground planes of the same net

– Results can be viewed graphically or in a text report– Users can also view relative and absolute voltage drop at any

point on the net

Optimize power delivery through DC power analysis


• SIGR011 Broadband SPICE

• SIGR021 T2B

• SIGR031 CAD Translators

• SIGR301 PowerSI

• SIGR311 3D-EM

• SIGR401 SPEED2000

• SIGR556 SystemSI – PBA II

Overview of Allegro Sigrity Options

Power Aware SI

Option


• SIGR051 OptimizePI

• SIGR201 PowerDC

• SIGR301 PowerSI

• SIGR311 3D-EM

•SIGR570 System Explorer

Serial Link SI

Option


• SIGR201 PowerDC

• SIGR311 3D-EM

• SIGR801 XtractIM

•SIGR570 System Explorer

Package Assessment and

Model Extraction Option

• SIGR011 Broadband SPICE

• SIGR021 T2B


• SIGR301 PowerSI

• SIGR311 3D-EM

• SIGR506 SystemSI – SLA II

Power Integrity

Option

Note: Each Option is a single user license. Only one of the products listed in each Option can be run at a time


• Allegro Sigrity SI – a unique full-featured SI solution– Power-aware Signal Integrity of high speed

memory interfaces is nicely integrated with the design environment

– Multi-gigabit serial link solution– Algorithmic transceiver model support

– Integrated full-wave 3D field solver

– High capacity simulation engine accurately predicts BER

• Allegro Sigrity PI – a unique full-featured PI solution– Integrated design and power integrity analysis

– Constraint driven flow

– Same environment for PCB designers and PI experts

Summary

One-of-a-Kind


Documents

Allegro Sigrity SI / PI Overview - Parallel Systems...Allegro Sigrity Signal Integrity Solutions –Allegro SI Base + Option Allegro Sigrity SI Base −Power-Aware SI Option −Serial