alighalehban.com-CompTIA A+ Lesson 5_Understanding Motherboards bus system

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CompTIA A+ Lesson 5 -Understanding Motherboards bussystem

This night Lesso n Topic is about Mother bus system f irst of all let we learn what is BUS .

A bus is the path t hrough which a device sends it s data so that it can communicate with the CPU and/or other devices. For example, a PCI device, such as an audio card, will send its data t hrough the PCI bus.Each device will have an access point t o the bus using a particular kind of interf ace. The word interface

ref ers not only to the physical port t he devices plug into , but to the electrical operating parameters and thecommunication f ormat as well. Typically, each bus has a uniquely shaped interf ace to prevent you f romdamaging your devices by plugging them into the wrong ports .

BUS ca n be f ound in 2 commo n parts :

Internal : The internal bus, also known as internal data bus, memory bus, s ystem bus or Front -Side-Bus,connects all the internal components of a computer, such as CPU and memory, to t he motherbo ard. Internaldata buses are also ref erred to as a local bus, because they are intended to connect to local devices. Thisbus is typically rather quick and is independent o f the rest of the computer operations .

External bus : The external bus, or expansion bus, is made up of the electro nic pathways t hat connect thedif f erent external devices, such as printer et c., to the computer.
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Common Motherboard Inte rnal BUS :

1. Front Side Bus (FSB) & Back side BUS (BSB)2. System & I/O BUS

3. AGP BUS

4. ISA & PCI BUS

5. USB BUS

6. Address bus

7. Control BUS

Front side BUS (FSB ) : The Front Side Bus is the interf ace between the CPU and the motherboard,specif ically the North Bridge/Memory Controller Hub


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Back Side Bus (BSB): The backside bus is the microprocessor bus that connects t he CPU to a Level 2cache. Typically, a backside bus runs at a f aster clock speed than the f ront side bus that connects the CPUto main memory. For example, the Pentium Pro microprocesso r actually consis ts of two chips o necont ains the CPU and the primary cache, and the seco nd contains the secondary cache. A backside busconnects t he two chips at the same clock rate as t he CPU itself (at least 200 MHz). In contras t, t hef ronts ide bus runs at only a fraction of the CPU clock speed.

Syste m & I/O BUS :

On older computers , the local bus, which was t he only bus, was used f or the CPU, RAMand I/O (input/output) components. All components on the local bus used the same clock speed. In the late80s we saw the separation o f the syst em bus f rom the I/O bus allowing them to run at dif f erent speeds.

The system bus (also called the f ront side bus, memory bus, local bus or host bus) is what connects t heCPU to main memory on the motherboard. I/O buses are those that connect the CPU and RAM with all other components, and the I/O buses branch of f of the sys tem bus. I/O buses operate on a speed which is lower than the sys tem bus speed. PCs of f er several types of I/O buses which include the ISA bus, PCI bus, AGPbus and USB bus.


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ISA & PCI BUS : Short f or Indust ry Standard Architect ure bus, the ISA bus architect ure was used in the IBMPC/XT and PC/AT. The AT version of the bus is called the AT bus and became a de facto indust ry st andard.Start ing in the early 90s , ISA began to be replaced by the PCI (Peripheral Component Interconnect) local busarchitecture. The PCI st andard was developed by Intel Corp. On modern PCs, t he PCI bus is the central (o r main) I/O bus. Its used f or connecting adapters s uch as hard disks, so und cards, network cards andgraphics cards (although now AGP is more common f or 3- D graphics). PCI is a 64-bit bus, though it isusually implemented as a 32-bit bus, and it can run at clock speeds o f 33 or 66 MHz. At 32-bits and 33 MHz,it yields a thro ughput rat e of 133 MBps (at 66 MHz 266 MBps). The vast majority o f to days PCs implementa PCI bus that runs at a maximum speed of 33 MHz.


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AGP Bus : Short f or Accelerated Graphics Port, an interf ace specif ication developed by Intel Corporation. AGP is based on PCI, but is designed especially f or the throughput demands o f 3-D graphics . Rather t hanusing the PCI bus f or graphics data, AGP intro duces a dedicated point- to -point channel so that thegraphics controller can directly access main memory. The AGP channel is 32- bits wide and runs at 66 MHz.This translates into a to tal bandwidth of 266 MBps, as opposed to the PCI bandwidth o f 133 MBps. AGPalso supports opt ional faster modes and allows 3- D textures to be sto red in main memoryrather than videomemory.

USB Bus : Short f or Universal Serial Bus, an external bus st andard that support s data transf er rates of 12Mbps. A single USB por t can be used to connect up to 127 peripheral devices, such as mice, modems, andkeyboards. USB also support s Plug-and-Playinstallation and ho t plugging.


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Address bus : is a computer bus (a series of lines connecting two o r more devices) that is used to s pecif ya physical address . When a process or or DMA-enabled device needs t o read or write t o a memory location,it specif ies that memory location on the address bus (the value to be read or written is sent on the databus). The width of the address bus determines the amount of memory a syst em can address . For example,a syst em with a 32-bit address bus can address 2 32 (4,294,967,296) memory locat ions . If each memoryaddress ho lds one byte, the addressable memory s pace is 4 GB.

Control BUS : contro l bus is (part of ) a computer bus, used by CPUs f or communicating with ot her devices within the computer. While the address bus carries the information o n which device the CPU iscommunicating with and the data bus carries t he actual data being processed, the control bus carriescommands f rom the CPU and returns st atus signals f rom the devices. For example if the data is being reador written to the device the appropriate line (read or write) will be active (logic zero).

Memory BUS : memory bus is the computer bus which connects the main memory to the memorycontroller in computer systems. Originally, general-purpose buses like VMEbus and the S-100 bus were

used, but to reduce latency, modern memory buses are designed to connect directly to DRAM chips, andthus are designed by chip standards bodies such as JEDEC. Examples are the various generations of SDRAM, and serial point- to -point buses like SLDRAM and RDRAM. An exception is t he Fully Buff ered DIMMwhich, despite being carefully designed to minimize the ef f ect, has been criticized f or its higher latency.

The dif f erences between computer busses break down into t hese categories:

Data width


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Cycle rate

Device management

Type

The data width and cycle rate are used to determine the bandwidth, or the to tal amount of data that t hebus can transmit. An 8-bit bus (1-byte data width) that operates at a cycle rate of 1,000 MHz (1,000,000times per second) can transf er 8 Mbps (1 MBps).

The device-management specif ication indicates the maximum number of supported devices and thedif f iculty of conf iguring them. There are two t ypes of bus communications, s erial and parallel. On a parallelbus, all devices have their own interf ace to t he bus, which is the norm. Serial devices are tied together in,well, a series; the last o ne has to t alk through the f irst o ne. This can cause obvious performanceproblems. These busses typically are used in conditions where data t hroughput isnt critical.

Bus conte ntion : in computer des ign, is an undesirable stat e of the bus in which more than one device onthe bus attempts to place values o n the bus at t he same time. Mos t bus architectures require their devicesf ollow an arbitration pro to col carefully designed to make the likelihoo d of content ion negligible. However,when devices on the bus have logic errors , manufacturing def ects or are driven beyond t heir design

speeds, arbitration may break down and contention may result. Contention may also arise on syst emswhich have a programmable memory mapping and when illegal values are writt en to the regis ters cont rollingthe mapping.

Content ion can lead to erroneous operation, and in unusual cases , damage to the hardwaresuch asf using of the bus wiring.Bus contention is sometimes countered by buf f ering the output o f memory-mapped devices. However, it has been noted t hat high impedance f rom one device will st ill interf ere with thebus values of ot her devices. Currently, no standard solution exists f or databus contention betweenmemory devices, such as EEPROM and SRAM.

Exte rnal Bus Inte rface , usually shortened to EBI, is a computer bus f or interf acing small peripheraldevices like f lash memory with the process or. It is used to expand the internal bus of the process or t oenable connection with external memories or other peripherals. EBI can be used to share I/O pins controllingmemory devices that are connected to t wo dif f erent memory cont rollers. Use of EBI reduces the to talnumber of syst em pins required causing the sys tem cost to come down. EBI manufacturers include Barco[1]and Freescale Semiconductor .

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