Alessandro Marras, Ilaria De Munari, Davide Vescovi, Paolo Ciampolini

Università di Parma

Performance Evaluation

of Ultrathin gate oxide

CMOS Circuits

Outline

Simulation models Designed circuit Circuit analysis

Conclusions

Power dissipation Logic Swing and Noise Margin Frequency

Technology

Starting technology LETI Minimum channel

length 50nm Supply voltage 1.5V Measurement performed

on Lot 6564 wafer12 in Udine University

Projected technologies Oxide thickness from

1.5nm down to 0.9nm Supply voltage from

1.5V down to 0.9V

Simulation model

Physical (DESSIS) simulation Projection to different

tox

comparison to ideal device

Circuit model EKV non-gate-

permeable core HDL correction blocks

Compact circuit model

Physical device model

Device model vs. measurements

0,0 0,5 1,0 1,5

0

10

20

30

40

5060

70

80

I G (

nA)

VG (V)

measurement simulation

VDS

0,0 0,5 1,0 1,5

0,0

0,5

1,0

1,5 measurement simulation

VDS

VG (V)

I D (

mA

)

Ring oscillator

101 stages Gate-current effects from reasonably-sized

devices (200nm X 10m) Gate current => CMOS architecture no

longer “ratioless” NAND gate: both static and dinamic analysis

tox (nm) P (W) LS (V) f (MHz)

1.5 8.4 1.488 28.7

1.3 14.7 1.486 45.0

1.1 20.0 1.486 54.2

0.9 23.6 1.486 55.8

Ideal circuit performance

Waveforms

Period shorteningVOH lowering

VOL rising

Power dissipation increase

Power consumption

P = <Preal> - <Pideal >

Ps = (IG,n + IG,p) · Vdd /2

Static Power consumption due to gate current

0,9 1,1 1,3 1,5

0,1

1

10

100

P Ps

P, P

s (

W)

tox

(nm)

VH

9

Power consumption

Power consumption increase, reduced by scaling down supply voltage

Solution: oxynitride / high–k dielectric

0,9 1,1 1,3 1,50,01

0,1

1

10

100

1000

0,01

0,1

1

10

100

1000

P I

G

I G (A

)

P (W

)

tox

(nm)

0,9 1,1 1,3 1,510

100

1000

10

100

1000

I G (A

)

Vdd (V)P

(W

)

P IG

Logic Swing degradation

Logic Swing degradation, reduced by scaling down supply voltage

0,9 1,1 1,3 1,510

-5

10-4

10-3

10-2

10-1

100

101

102

103

10-2

10-1

100

101

102

103

104

105

106

LS IG

I G (A

)

LS

(mV

)

tox (nm)

0,9 1,1 1,3 1,51E-5

1E-4

1E-3

0,01

0,1

1

1E-5

1E-4

1E-3

0,01

0,1

1

I G (

A)

Vdd (V)L

S (

V) LS

IG

Noise Margin Reduction

Logic Swing reduction

Noise Margin reduction

0,9 1,1 1,3 1,5300

400

500

600

700

ideal case real case

high NM

low NM

Noi

se M

argi

n (m

V)

tox

(nm)

Logic Swing degradation

VH

VL

0,9 1,1 1,3 1,51,301,321,341,361,381,401,421,441,461,481,50

tox

(nm)

LS

(V

) single stage chain

Frequency shift

Frequency shift, reduced by scaling down supply voltage

0,9 1,1 1,3 1,50,01

0,1

1

10

f (M

Hz)

tox

(nm)

0,9 1,1 1,3 1,51

2

3

4

5

6

Vdd (V)f

(M

Hz)

Frequency shift

Complex transient due to: Additional currents

tunneling through gate oxide

Reduced Logic Swing

Global effect observed: Frequency increase

Vi-1Vi Vi+1

IDp IGp

IGnIDn C

VL VH

Conclusions

Compact circuit model developed: Based on physical model Good fitting with measurements

Effects of direct-tunneling current investigated: Power consumption increase Logic swing and noise margin degradation Frequency shift

Circuit maintains its functionality, but with some non- negligible performance degradations

Within the investigated range, permeable-gate devices seems to be suitable for practical applications