Ajay Kumar Garg Engineering College

8/2/2019 Ajay Kumar Garg Engineering College

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AJAY KUMAR GARG ENGINEERING COLLEGE

27th Km Stone, Delhi-Hapur Bypass Road, Ghaziabad-201009

Phones :(0120)2765790,3251275-76 Fax:2767384

-: TECHNICAL SEMINAR REPORT ON :-

LDMOS TECHNOLOGY AND APPLICATIONS

BY:

PRAVEEN PATHAK

ECE-3th

YEAR

Roll No.-0902731074

[email protected]
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ACKNOWLEDGEMENT

I extend my sincere gratitude towards Prof. P.K.CHOPRA Head ofDepartment for giving us his invaluable knowledge and wonderful technical guidance.

I express my thanks to Dr. RANJIT SINGH our group tutor and also to our

staff advisor NAVNEET SIR for their kind co-operation and guidance for preparing

and presenting this seminar.

I also thank all the other faculty members of ECE department and my friends

for their help and support.
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ABSTRACT

LDMOS stands for lateral double-diffused MOSFET, the lateral version of

power MOSFET, DMOS. Although some vendors offer RF versions of DMOS,its vertical structure has serious problems with excessive parasitic capacitancestarting at around 500 MHz. LDMOS fares much better at higher frequencies,not least due to extensive technology development recent years. The firstcellular base stations used silicon BJTs, and many GaAs developers expected aneasy win as cell frequencies were going up, and linearity and efficiencyrequirements were getting tighter. This never happened , it was LDMOS thatinvaded the territory. LDMOS components with output power over 100 Watts at2.7 GHz are available at the moment of writing this. The frequency range islikely to extend further as Freescale has recently announced 3.5 GHz highpower LDMOS for coming WiMAX applications. If or when this happens, thehopes AlGaN developers had for exciting new markets might not come true,

just as those of GaAs folks a decade ago.High power LDMOS devices typically provide internal impedance matching forintended frequency band. The practical power limit for LDMOS withoutinternal matching is around 10 Watts at 2.5 GHz. This might leave a window ofopportunity for other materials in broadband power designs. Wide band gapmaterials offer higher output power per 1 pF of gate capacitance, which is anadvantage for broadband applications.
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CONTENTS

1. INTRODUCTION2. D EVELOPMENT OF HIGH VOLTAGE IC PLATFORM3. INTERMODULATION DISTORTION BEHAVIOR

4. APPLICATIONS5. CONCLUSION6. BIBLIOGRAPHY


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INTRODUCTION:

In many modern wireless systems, the linearity requirement put strong

restrictions on the power amplifiers used. It has been found that LDMOStransistors exhibit better intermodulation distortion (IMD) performancecompared to competing technologies [1, 2]. LDMOS transistors are thereforewidely used in power amplifiers at microwave frequencies in commercialapplications such as base-station transmitters.

A good understanding of the device characteristics isnecessary to take fulladvantage of the LDMOS technology when building amplifiers for optimizationof IMD performanceit is even crucial.The IMD behavior of MESFET poweramplifiers has been analyzed in [3]. However, since the LDMOS characteristicsare different from the MESFETs it is necessary to revise the analysis to predictmeasured IMD behavior.In this paper it is shown that the sharp turn-on of theLDMOS compared to MESFET plays an important role in explaining additionalIMD minima that appear in class B and AB [1]. This may also be a clue to thesuperior linearityof LDMOS transistors.

IMD measurements made at low frequency corresponding to differentclasses of operation are used to verify the analysis and give an overview of theLDMOS IMD behavior. Finally, measurements made on a 1.9 GHz LDMOSamplifier are used to examine how the IMD behave Lateral Double Diffused

MOSFET (LDMOS) was the first power MOSFET structurewhich is still usedto build output power stages in power management ICs. Asdiscussed in, alateral structure of power MOSFET is not adequate todesign switches for highcurrents, where a vertical transistor should be used instead.
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The technical issues inherent to a lateral MOSFET design, as shown in

Fig., \

have been alleviated by technical improvements shown

The high electric field spike occurring at the corner of the gate can be reducedby inserting a thicker oxide made by LOCOS oxidation, and the resistance of

the base region of the parasitic bipolar transistor can be reduced by anadditional implantation to increase the dopant concentration underneath thesource region. One of the remaining design issues is the fact that the lateraltransistor has to be created using the existing doping and mask steps in themanufacturing flow of the IC. As a result the on-resistance and the internalcapacitances of the LDMOS are not optimal.

To improve the current capability of the power MOSFET, a VerticalDoubleDiffused MOSFET structure (VDMOS) has been introduced in the early1980s.A basic VDMOS structure is shown in Fig A large area top electrode isthe source terminal. The current flows from the source region N+ to the channelunderneath of the lateral gate, and then into the N epitaxial layer where it isdiverted to the N+ substrate and finally reaches the drain electrode at the backof the die.

The main design issue inherent to the VDMOS structure is currentpinching between the two P-body regions as illustrated by Fig,.


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Current pinching called JFET effect takes place if the distance between the twoP-body regions is too small. This effect limits the ability to reduce the cell pitchin the design of a VDMOS structure. As mentioned before, reducing pitch is theeasies way to reduce the specific on-resistance of the transistor. The other wayis to make channel shorter, but this is limited by the danger of punch-through.Punchthrough occurs when the depletion induced by drain voltage penetrates

body region and reaches the source N+ region. Another issue is created by theoverlap of the gate on drain region between the P-body wells. The gate overlapleads to an increased Cgd capacitance which can not be minimized due to thepresence of the JFET effect. Thus, there is only a restricted chance of improvingFOM of the VDMOS design.
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Development of High Voltage IC Platform Technology :

Micro Device Division, Hitachi, Ltd. developed the following twotechnologies for High voltage IC platform suitable for measuring instruments,medical equipments and in-vehicle equipments. One is high performance P-channel LDMOS transistors on wide range rated voltage from 35 V to 200 VSOI LDMOS platform technology. The other is 300 V Field-MOS FETs forHigh Voltage switching IC's. These technologies will enable to integrate a lot ofdiscrete components and High Voltage Transistors on single chip. Thesetechnologies were developed to meet demands shown below.

Each transistor used in semiconductor integrated circuits has threeterminals called gate, drain and source. A transistor breaks when overvoltage isapplied. It is called breakdown voltage that the maximum voltage for a

transistor to be applied without breakdown. In conventional technology,transistors each having its own breakdown voltage between source and drainfrom 35 V to 200 V are made by their own manufacturing process. It is difficultto integrate a lot of discrete components and such types of transistors on a chip.Enabling these components and transistors to be integrated on a chip is the keyissue for miniaturization of instruments and equipments.

The technology that enables to integrate transistors on a chip with variousvalues of breakdown voltages between source and drain from 35 V to 200 V hasbeen developed. The technology uses transistors with various length inhorizontal direction but only with the same structure in depth direction (seeFigure 1). Then there is no need to use additional photo masks to make suchkind of transistors.

Figure 1. Schematic structureof P-channel LDMOS
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Figure 2. Breakdown voltage and on-resistanceof 35 V to 200 V LDMOS transistors

Through the optimization of the manufacturing process for the transistors

shown above, very low on-resistance was obtained with keeping high on/off-state breakdown voltages (see Figure 2).

Since the technology, mentioned above, enables components to beintegrated on a chip, then it will be able to miniaturize instruments andequipments by using the chip, and improve reliability by reducing the numberof components used in them.

In conventional technology, transistors with breakdown voltage over 200V between source and drain have not so high breakdown voltage between gate

and source. Therefore there must be the dedicated circuit for inputting highvoltage signal into gate terminal of a transistor. To eliminate such kind ofdedicated circuits and transistors is another key issue for minimizing chip-sizeand consumption power of chips.

The technology that enables to make transistors with breakdown voltageover 300 V between gate and source has been developed. The technologyadopts the LOCOS type oxide film for gate oxide of High voltage transistors(see Figure 3). The processes for making such kind of transistors wereoptimized using computer simulation (see Figure 4). Finally, proto-type

transistors have shown their breakdown voltage between gate and sourceterminals over 400 V in typical usage, that is to say, developed transistors havechances in various kinds of applications that require high reliability (see Figure5).

Figure 3. Schematic structure

of N-channel MOS
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Figure 5. On-state characteristicsof N-channel MOS

Figure 4. Device simulation of N-channel MOS

As a result, the dedicated circuit for inputting high voltage signal intogate terminal of a transistor can be eliminated, and the second demand was met.
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Intermodulation Distortion Behavior in LDMOS Transistor

Amplifiers:

Cellular radio telephone systems have been in use for 20 years with NMT-450introduction during 1981. Since then the systems evolved from analogue todigital modulation schemes for both speech and data transfer with muchincreased bandwidth. The ever-increasing market demand of digital basestationpower amplifiers in PCS, CDMA, and WCDMA systems requires a low cost,ease of use technology which can provide high power and better linearityperformance. LDMOS started replacing bipolar devices in basestationapplications 3-4 years ago and has become the leading technology forbasestation power amplifier applications because of the multiple reasons.LDMOS is a majority carrier device and thus has potentially higher cut-off

frequency than BJT. It also has a backside source contact whichsubstantially decreases the source inductance. As a result LDMOS has highgain. The grounded backside allows also use of cheaper packages with betterthermal properties in which the dies are directly soldered to the flange, insteadof older bipolar variety with toxic beryllium oxide isolator. Since the draincurrent has a negative temperature coefficient, LDMOS doesn't need ballastresistors and also has a better thermal uniformity compared to BJT. It alsoshows an excellent back-off linearity. In addition to the performance gainLDMOS technology has some practical advantages. The breakdown voltage

BVdss can be easily adjusted by layout to fit different application voltage. Ituses mature low cost technology and it's simple to integrate with CMOS. Thedevice size can be scaled with reasonable ease. However, there are somefundamental limits to LDMOS technology. Frequency response is limited bygate charging and transit time required through N- drift region, making LDMOSless suitable for operation over 3 GHz. It suffers also from excess efficiencydegradation with increasing frequency operation and due to hot electroninjection in the gate oxide we experience Idq drift.
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APPLICATIONS:

High-Frequency Operation:

The advantages for the LDMOS transistor in high-frequency operation are

mainly due to an easily achieved short channel. A short channel makesthe device operate in velocity saturation which gives a constant transcon-ductance, resulting in good linearity [35]. The use of LDMOS transistors athigh-frequencies has mainly been in the area of telecommunication where thefrequencies of operation are up to some GHz today, but they are increasing.The standard supply voltage in a base station is 28 V which needs deviceswith a breakdown voltage around 50-60 V. The output power density of thesedevices is about 0.5 W/mm at 2 GHz [21]. Normal operation of these devicesare class AB, and work on class E has shown that increasing supply voltagegives drastically increases output power [36]. It has also been shown, for dualdepletion layer LDMOS devices, that if the supply voltage is increased the ef-_ciency is increased and power densities up to 2 W/mm have been presentedat VD=70 V and 1 GHz [paper V]. Figure 3.1 shows the 20 mm gate widthdevice from the paper.

Other application areas that can utilize these devices are in lightning andheating, using micro-magnetrons. The LDMOS has also been shown to givecompetitive performance for low-voltage applications [paper II], with supplyvoltages at 5 V and breakdown voltages at 15-30 V.

When characterizing high-frequency devices there are several di_erent

key parameters. There are the basic DC-parameters such as on-resistance,transconductance and breakdown voltage. Then there are the small-signalparameters of which the cut-o_ frequencies fT and fMAX are the most com-mon. The current gain cut-o_ frequency, fT is the frequency at which thecurrent gain, H21, is 0 dB.

High Power LDMOS technology for wireless infrastructure systemsevolved from analogue to digital modulation schemes for both speech and datatransfer with much increased bandwidth. The ever-increasing market demand of

digital basestation power amplifiers in PCS, CDMA, and WCDMA systemsrequires a low cost, ease of use technology which can provide high power andbetter linearity performance. LDMOS started replacing bipolar devices inbasestation applications 3-4 years ago and has become the leading technologyfor basestation power amplifier applications because of the multiple reasons.LDMOS is a majority carrier device and thus has potentially higher cut-offfrequency than BJT. It also has a backside source contact which substantiallydecreases the source inductance. As a result LDMOS has high gain. Thegrounded backside allows also use of cheaper packages with better thermal

properties in which the dies are directly soldered to the flange, instead of
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older bipolar variety with toxic beryllium oxide isolator. Since the drain currenthas a negative temperature coefficient, LDMOS doesn't need ballast resistorsand also has a better thermal uniformity compared to BJT. It also shows anexcellent back-off linearity. In addition to the performance gain LDMOS

technology has some practical advantages. The breakdown voltage BVdss canbe easily adjusted by layout to fit different application voltage. It uses maturelow cost technology and it's simple to integrate with CMOS. The device sizecan be scaled with reasonable ease. However, there are some fundamental limitsto LDMOS technology. Frequency response is limited by gate charging andtransit time required through N- drift region, making LDMOS less suitable foroperation over 3 GHz. It suffers also from excess efficiency degradation withincreasing frequency operation and due to hot electron injection in the gateoxide we experience Idq drift.

II. DEVICE PROCESS

The latest generation of LDMOS transistors from Ericsson Microelectronics(GOLDMOS V), primarily intended for use in the 1.8-2.2 GHz frequency range,has a cross-section as shown in Fig.1. The transistor is built into a p+ substratewith a p-epi on top. It consists of alternating n+ drain and n+ source regionswhere the n+ drain is separated from the gate by an n- drift region. The p-typechannel dopant is diffused laterally in under the gate from its source side toform p-well. Deep p+ diffusion allows the current to pass from the n+ source tothe p+ substrate with minimal voltage drop by means of a metal jumper shortingthese regions to one another. This metal is wrapped around the gate to act as ashield between gate stack and drain metal, which reduces the feedbackcapacitance (Crss) significantly. A second metal layer fills two purposes. Themetal-2 conductor makes contact to the gate at regular intervals to reduce RCdelays. On the drain side metal-1 and metal-2 conductors are stacked todecreasethickness is 500 . The gate stack consists of n+ doped polysilicon and 2500

-

resulting in a typical breakdown voltage BVDSS of 75V, with the prerequisiteof a high enough p-type dopant concentration in the p-well region to avoid apremature punch-limited breakdown. This in turn results in a typical thresholdvoltage Vth of 4V. Both metal layers are gold with a TiW/TiW(N)/TiW barriermetal underneath. Nominal metal- metal-2 is 1.8
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III. DEVICE PERFORMANCE

Ericsson has developed GOLDMOS technologies for 3G base stationapplications. The 30W PEP (peak envelop power) single ended and the 120Wpush-pull devices WCDMA performance at 28V and 2.14GHz are summarizedin Table 1 and 2. The two-tone tests are done using 100kHz tone spacing. Thesingle carrier 3GPP WCDMA evaluation are done with 3 DPCH channels, ~ 9dB peak to average ratio, -45 dBc ACPR @ 5MHz and 3.84 MHz BW. LDMOStechnology shows excellent backed-off linearity compared to BJT and GaAsdevices. The 28V LDMOS benchmarking results showed > 5 dBc better IM3compared to 12V GaAs [1].
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LDMOS Transistors for cellular technologies and infrastructures:

LDMOS performance is continuously pushed to its limits realizing superbpower and efficiency levels at ever increasing frequencies. In parallel research

and development efforts are put into GaN technology. GaN has outstandingmaterial parameters and is therefore seen as the RF Power technology of thefuture. GaN is already used in niche applications and may gradually develop asthe technology to support advanced high efficiency power amplifier concepts.LDMOS is todays technology of choice for 3G applications, LTE, WiMaxBase stations, Broadcast applications, ISM, and radar applications. TodaysLDMOS technology is produced in deep submicron fabs with gate lengths downto 300 nm, utilizing advanced CMOS equipment. Three LDMOS technologiesare available for operation at supply voltages of 28V, 42V and 50V,

respectively. LDMOS devices are mostly used for class AB and TodaysLDMOS technology for cellular infrastructureDR. STEVEN THEEUWEN, NXP SEMICONDUCTORS
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CONCLUSIONS:

A behavioral analysis of the IMD in LDMOS amplifiers is presented andvalidated using measurements under various operating conditions. The analysis

relates the device characteristics such asIout(Vin), compression point, and turn-on knee to the measured IMD behavior. It has been shown that relativeabruptness of the turn-on region compared to other technologies may explainthe surprisingly linear nature of LDMOS transistors in power amplifierapplications. Differences between measurements made at 100 MHz and 1.9GHz highlight the importance of accurate device models, including non-linearcapacitances, for accurate prediction of IMD behavior also at higherfrequencies. Nevertheless, the existence of a bias-dependent IMD sweet-spotwas accurately predicted from the low frequency analysis. The results obtained

are important from an industrial point of view, since they explain how a linearclass AB power amplifier, based on LDMOS technology, can be designedto present high values of C/I. Thus showing an improvement compared toMESFET based designs where only class B or C could be used.
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BIBLIOGRAPHY:

[1] F. van Rijs, S.J.C.H. Theeuwen, Efficiency improvement of LDMOStransistors for base stations: towards the theoretical limit, IEDM2006,

pp. 205-208 (2006).[2] F. van Rijs, Status and trends of silicon LDMOS base station PAtechnologies to go beyond 2.5 GHz applications, RWS 2008, pp. 69-72(2008).[3] S.J.C.H. Theeuwen, H. Mollee, S-Band Radar LDMOS Transistors ,Proceedings of the 4rd european Microwave Integrated Circuits Conference,EuMIC 2009, pp. xx-xx (2009).[4] S.J.C.H. Theeuwen, W.J.A.M. Sneijers, J.G.E. Klappe, J.A.M. de Boet,High Voltage RF LDMOS Technology for Broadcast Applications,

Proceedings of the 3rd european Microwave Integrated Circuits Conference,EuMIC 2008, pp. 24-27 (2008)[5] Y. Tsividis, Operation and modeling of the MOS transistor, 2 ed. Boston:WCB/McGraw-Hill, 1999.[6] J.-J. Bouny, "Advantages of LDMOS in high power linear amplification,"

Microwave Engineering Europe, pp. 37-40, Apr. 1996.
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Ajay Kumar Garg Engineering College