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AIX and PowerVM Workshop
© 2013 IBM Corporation1
POWER5 POWER5+ POWER6 POWER7 POWER7+
Technology 130nm 90nm 65nm 45nm 32nm
Size 389 mm2 245 mm2 341 mm2 567 mm2 567 mm2
Transistors 276 M 276 M 790 M 1.2 B 2.1 B
Cores 2 2 2 8 8
Frequencies 1.65 GHz
1.9 GHz
4 - 5 GHz
3 – 4 GHz 3.6 – 4.4+ GHz
L2 Cache 1.9MB Shared 1.9MB Shared 4MB / Core 256 KBper Core
256 KBper Core
L3 Cache 36MB 36MB 32MB 4MB / Core 10MB / Core
Memory Cntrl 1 1 2 / 1 2 / 1 2 / 1
Architecture Out of Order Out of Order In Order Out of Order Out of Order
LPAR 10 / Core 10 / Core 10 / Core 10 / Core 20 / Core
Processor Designs – DROP POWER5 and add POWER8
AIX and PowerVM Workshop
© 2013 IBM Corporation2
2004 2001 2007 2010 Future
POWER4/4+180/130 nm
POWER5/5+130/90 nm
POWER6/6+65/65 nm
POWER7/7+45/32 nm
Dual Core Chip Multi ProcessingDistributed SwitchShared L2Dynamic LPARs (32)
Dual CoreEnhanced ScalingSMTDistributed Switch +Core Parallelism +FP Performance +Memory Bandwidth +Virtualization
Dual CoreHigh Frequencies Virtualization +Memory Subsystem +Altivec Instruction RetryDynamic Energy MgmtSMT +Protection Keys
Eight CoresOn-Chip eDRAM Power-Optimized CoresMemory Subsystem ++SMT++Reliability +VSM & VSXProtection Keys+
Power Processor Technology Roadmap – DROP POWER4, 5 and add POWER8 Jay Kruencke probably already has an updated slide (same for previous slide)
AIX and PowerVM Workshop
© 2013 IBM Corporation3
POWER7+32 nm
POWER7 POWER7+
POWER745 nm
POWER7+32 nm
Add any changes s needed, but this shows what the major change was from P6 to P7 cores
AIX and PowerVM Workshop
© 2013 IBM Corporation4
POWER7+32 nm
POWER7 POWER7+
POWER745 nm
POWER7+32 nm
Add additional Cache (L3) from 4MB to 10MB per core
AIX and PowerVM Workshop
© 2013 IBM Corporation5
POWER7+32 nm
POWER7 POWER7+
POWER745 nm
POWER7+32 nm
Add additional Cache
Add on Chip Accelerators
Random Number Generator
