A Fast Sequential Learning A Fast Sequential Learning Technique for Real Circuits Technique for Real Circuits

With Application to Enhancing With Application to Enhancing ATPG Performance ATPG Performance

A Fast Sequential Learning A Fast Sequential Learning Technique for Real Circuits Technique for Real Circuits

With Application to Enhancing With Application to Enhancing ATPG Performance ATPG Performance

Aiman H. El-MalehAiman H. El-Maleh

Department of Computer EngineeringDepartment of Computer Engineering

King Fahd University of Petroleum & MineralsKing Fahd University of Petroleum & Minerals

Aiman H. El-MalehAiman H. El-Maleh

Department of Computer EngineeringDepartment of Computer Engineering

King Fahd University of Petroleum & MineralsKing Fahd University of Petroleum & Minerals

2

OutlineOutlineOutlineOutline

MotivationMotivation Sequential learning technique Sequential learning technique Implication learningImplication learning Tie gate learningTie gate learning Enhancing ATPG performanceEnhancing ATPG performance Experimental resultsExperimental results ConclusionsConclusions

MotivationMotivation Sequential learning technique Sequential learning technique Implication learningImplication learning Tie gate learningTie gate learning Enhancing ATPG performanceEnhancing ATPG performance Experimental resultsExperimental results ConclusionsConclusions

3

MotivationMotivationMotivationMotivation

Learning can significantly enhance a search processLearning can significantly enhance a search process• Reduce the number of decision nodesReduce the number of decision nodes

• Identify conflicts sooner and reduce number of backtracksIdentify conflicts sooner and reduce number of backtracks

Learning used in CAD, most notably in ATPGLearning used in CAD, most notably in ATPG Learning typically performed in combinational logicLearning typically performed in combinational logic Sequential ATPG more complex than combinational Sequential ATPG more complex than combinational

ATPG due to signal dependencies across framesATPG due to signal dependencies across frames Density of encoding is a key factor of complexity of Density of encoding is a key factor of complexity of

sequential ATPG sequential ATPG

Learning can significantly enhance a search processLearning can significantly enhance a search process• Reduce the number of decision nodesReduce the number of decision nodes

• Identify conflicts sooner and reduce number of backtracksIdentify conflicts sooner and reduce number of backtracks

Learning used in CAD, most notably in ATPGLearning used in CAD, most notably in ATPG Learning typically performed in combinational logicLearning typically performed in combinational logic Sequential ATPG more complex than combinational Sequential ATPG more complex than combinational

ATPG due to signal dependencies across framesATPG due to signal dependencies across frames Density of encoding is a key factor of complexity of Density of encoding is a key factor of complexity of

sequential ATPG sequential ATPG

4

T0T0 T1T1 T2T2 T3T3

SSG2G2 G4G4 G6G6

G1G1 G3G3 G5G5

00 11 11

Sequential learning techniqueSequential learning techniqueSequential learning techniqueSequential learning technique

Identify fanout stemsIdentify fanout stems For each stemFor each stem

• Inject a logic 0 and propagate forward across framesInject a logic 0 and propagate forward across frames

• Inject a logic 1 and propagate forward across framesInject a logic 1 and propagate forward across frames

Identify fanout stemsIdentify fanout stems For each stemFor each stem

• Inject a logic 0 and propagate forward across framesInject a logic 0 and propagate forward across frames

• Inject a logic 1 and propagate forward across framesInject a logic 1 and propagate forward across frames

G1=1 G1=1 G2=0 G2=0 G3=0 G3=0 G4=1 G4=1 G5=1 G5=1 G6=1 G6=1

G3=0 at T=i G3=0 at T=i G2=0 at T=i-1 G2=0 at T=i-1

G5=1 at T=i G5=1 at T=i G2=0 at T=i-2 G2=0 at T=i-2

00

11

11 00 1111

00 11 00

5

Single-node learning: ExampleSingle-node learning: ExampleSingle-node learning: ExampleSingle-node learning: Example

l1l1

G8G8

G1G1

G2G2

F1F1

G3G3

G4G4

G5G5

G6G6

G7G7 F3F3

F4F4

G9G9

F2F2

F1=1 F1=1 F2=1 F2=1 F3=1 F3=1 F4=1 F4=1

00

11

11 11

11

11

11 11

00 00

00

00

00 00

00

G7=1 G7=1 F2=1 F2=1 G8=0 G8=0 F1=0F1=0

11 1111

00

11

6

S1S1 S2S2S1S1

T0T0 T1T1 T2T2 T3T3

G2G2 G5G5

G1G1

G4G4

G3G3S3S3

0000

00

Multiple-node learningMultiple-node learningMultiple-node learningMultiple-node learning

For each gate with multiple stems implying the same For each gate with multiple stems implying the same value on the gatevalue on the gate• Inject corresponding contrapositive values on the stemsInject corresponding contrapositive values on the stems

• Propagate values concurrently forward across time framesPropagate values concurrently forward across time frames

For each gate with multiple stems implying the same For each gate with multiple stems implying the same value on the gatevalue on the gate• Inject corresponding contrapositive values on the stemsInject corresponding contrapositive values on the stems

• Propagate values concurrently forward across time framesPropagate values concurrently forward across time frames

0000

G1=1 G1=1

G5=1 G5=1

1111 11 11 11

11

11 1111

7

Multiple-node learning: Example 1Multiple-node learning: Example 1Multiple-node learning: Example 1Multiple-node learning: Example 1

I1I1 F1F1

G1G1

G2G2

G3G3

G4G4

G5G5

G7G7

G6G6 F2F2

F3F3

G8G8

G9G9

YY

F2=1 F2=1 F3=1 F3=1

00

00

00

00

11

11

11

1111

11

11

11

00

I1=0I1=0 F2=0 at T=1 F2=0 at T=1 I1=0I1=0 F2=0 at T=2 F2=0 at T=2

00

00

00

00 00

00

00

I1=0I1=0 F2=0 at T=1 F2=0 at T=1

11

8

I1=0I1=0 G9=1 at T=1 G9=1 at T=1 I2=0I2=0 G9=1 at T=1 G9=1 at T=1

Multiple-node learning: Example 2Multiple-node learning: Example 2Multiple-node learning: Example 2Multiple-node learning: Example 2

G3G3

G2G2

G4G4

G5G5

F1F1

F3F3

F2F2

F4F4

F5F5

G6G6

G7G7

G8G8

G9G9

I1I1

I2I2

G1G1

G9=0 G9=0 F2=0 F2=0

00 11

11

11

11

11

11

11

1100 11

11 11 11

11 11

11 11

11

11

00

00 00

00

00

00

00

00

00

00

9

G7=1 G7=1 F3=1 F3=1

Use of gate equivalence in learningUse of gate equivalence in learningUse of gate equivalence in learningUse of gate equivalence in learning

I1I1

I3I3

G2G2

G3G3

G4G4

F1F1

F2F2

F3F3

G5G5

G6G6G8G8G1G1

G7G7

G2 is equivalent to G3G2 is equivalent to G3

00

00

00 00 0000

00

00 00

00

11

11 11

Gate equivalence enables value propagationGate equivalence enables value propagation Gate equivalence enables value propagationGate equivalence enables value propagation

11

10

Learning of tied gatesLearning of tied gatesLearning of tied gatesLearning of tied gates

Case 2: BasedCase 2: Based onon multiple-node learningmultiple-node learning Case 2: BasedCase 2: Based onon multiple-node learningmultiple-node learning

Case 1: Based on single-node learningCase 1: Based on single-node learning Case 1: Based on single-node learningCase 1: Based on single-node learning

II GG G is tied to 0G is tied to 0

G2 and G3 areG2 and G3 are tied to 0tied to 0

00 00

1100

00

11

11

00 00

00

00 00

00I1I1I2I2

G1G1

G2G2

G3G300

00

0011

11

Practical issuesPractical issuesPractical issuesPractical issues

Multiple clock domainsMultiple clock domains• Classify sequential elements based on driving clockClassify sequential elements based on driving clock

• Latches and FFs treated separatelyLatches and FFs treated separately

• Perform learning for each classPerform learning for each class

Set/Reset handlingSet/Reset handling• Set/Reset in a sequential element can invalidate the Set/Reset in a sequential element can invalidate the

propagated valuepropagated value

• Rules for value propagation across a sequential element:Rules for value propagation across a sequential element:• Propagate a 0 if there is no set linePropagate a 0 if there is no set line• Propagate a 1 if there is no reset linePropagate a 1 if there is no reset line

Multiple clock domainsMultiple clock domains• Classify sequential elements based on driving clockClassify sequential elements based on driving clock

• Latches and FFs treated separatelyLatches and FFs treated separately

• Perform learning for each classPerform learning for each class

Set/Reset handlingSet/Reset handling• Set/Reset in a sequential element can invalidate the Set/Reset in a sequential element can invalidate the

propagated valuepropagated value

• Rules for value propagation across a sequential element:Rules for value propagation across a sequential element:• Propagate a 0 if there is no set linePropagate a 0 if there is no set line• Propagate a 1 if there is no reset linePropagate a 1 if there is no reset line

12

G9=0 G9=0 F2=0 F2=0

G1G1

G3G3

G2G2

G4G4

G5G5

F1F1

F3F3

F2F2

F4F4

F5F5

G6G6

G7G7

G8G8

G9G9

I1I1I2I2

I3I3

I4I4

I5I5

I6I6

00

11__00

00

00

00

00

00

Known- vs. forbidden-value relationsKnown- vs. forbidden-value relationsKnown- vs. forbidden-value relationsKnown- vs. forbidden-value relations

Known-value implications eliminate decisionsKnown-value implications eliminate decisions Known-value implications eliminate decisionsKnown-value implications eliminate decisions

G9=0 G9=0 F2=F2= 11__

13

G1G1

G2G2

F1F1

F3F3

F2F2

F4F4

G5G5

G6G6

G4G4

I1I1I2I2

I4I4I3I3

I6I6

G3G3

I5I5

F4=1 F4=1 G4=1 G4=1

XXS0S0

11

0011

Extra requirements by implicationsExtra requirements by implicationsExtra requirements by implicationsExtra requirements by implications

Known-value implications can cause additional Known-value implications can cause additional unnecessary requirements unnecessary requirements

Known-value implications can cause additional Known-value implications can cause additional unnecessary requirements unnecessary requirements

00

1100__

00

F4=1 F4=1 G4=G4=00__

14

G1G1

G3G3

G2G2

G4G4

G5G5

F1F1

F3F3

F2F2

F4F4

F5F5

G6G6

G7G7

G8G8

G9G9

I1I1I2I2

I3I3

I4I4

I5I5

I6I6

00

11__

00

00

00

00

00

Suggested use of implicationsSuggested use of implicationsSuggested use of implicationsSuggested use of implications

Guide decision to inputs with forbidden non-Guide decision to inputs with forbidden non-controlling valuecontrolling value

Guide decision to inputs with forbidden non-Guide decision to inputs with forbidden non-controlling valuecontrolling value

G9=0 G9=0 F2=F2= 11__

15

Experimental resultsExperimental resultsExperimental resultsExperimental results

Benchmark circuitsBenchmark circuits• ISCAS 89 and 93 circuitsISCAS 89 and 93 circuits

• Four retimed circuits (high sequential ATPG complexity)Four retimed circuits (high sequential ATPG complexity)

• Three industrial circuitsThree industrial circuits

Sequential learning performed up to 50 time framesSequential learning performed up to 50 time frames Sequential ATPGSequential ATPG

• Without sequential learningWithout sequential learning

• With learned relations used as known-value implicationsWith learned relations used as known-value implications

• With learned relations used as forbidden-value implicationsWith learned relations used as forbidden-value implications

Test Coverage = Detected/(Total - Untestable)Test Coverage = Detected/(Total - Untestable)

Benchmark circuitsBenchmark circuits• ISCAS 89 and 93 circuitsISCAS 89 and 93 circuits

• Four retimed circuits (high sequential ATPG complexity)Four retimed circuits (high sequential ATPG complexity)

• Three industrial circuitsThree industrial circuits

Sequential learning performed up to 50 time framesSequential learning performed up to 50 time frames Sequential ATPGSequential ATPG

• Without sequential learningWithout sequential learning

• With learned relations used as known-value implicationsWith learned relations used as known-value implications

• With learned relations used as forbidden-value implicationsWith learned relations used as forbidden-value implications

Test Coverage = Detected/(Total - Untestable)Test Coverage = Detected/(Total - Untestable)

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Sequential learning resultsSequential learning resultsSequential learning resultsSequential learning results

CircuitCircuits5378s5378s6669s6669

s13207s13207s15850s15850s38417s38417

s510jcsrres510jcsrres510josrres510josrres832jcsrres832jcsrrescfjisdrescfjisdre

Industrial 1Industrial 1Industrial 2Industrial 2Industrial 3Industrial 3

FFsFFs GatesGates FF-FFFF-FF Gate-FFGate-FF CPU(s)CPU(s)179179239239638638597597

163616362626282827272020

46046070687068

1568915689

27792779308030807951795197729772

2217922179243243243243195195764764

869386936315663156

681595681595

2502502424

1566156615161516155415541271275050

1251252222

1181182069206980168016

2233223316031603

350933509329378293784698146981

891891484484743743

1980198067746774

3639736397186930186930

6.426.420.390.39

23.0823.0842.0442.0430.2430.240.100.100.070.070.110.110.560.562.742.74

24.3124.31403.30403.30

Learned RelationsLearned Relations

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ATPG resultsATPG resultsATPG resultsATPG results

50

60

70

80

90

100

Test

cov

erag

e (%

)

s1423 s3330 s4863 s5378 s6669 s510jcsrre s832jcsrre

No seq. learning Forbidden-value implications Known-value implications

0

20

40

60

80

100

Rela

tive

CPU

(%)

s1423 s3330 s4863 s5378 s6669 s510jcsrre s832jcsrre

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ConclusionsConclusionsConclusionsConclusions

A novel and efficient method for sequential learningA novel and efficient method for sequential learning Identifies implications, invalid states and tied gatesIdentifies implications, invalid states and tied gates Handles industrial circuits with multiple clock Handles industrial circuits with multiple clock

domains and partial or no set/resetdomains and partial or no set/reset Increases number of detected and untestable faultsIncreases number of detected and untestable faults Significantly reduces sequential ATPG timeSignificantly reduces sequential ATPG time Applicable to redundancy identification, logic Applicable to redundancy identification, logic

optimization, and logic verificationoptimization, and logic verification

A novel and efficient method for sequential learningA novel and efficient method for sequential learning Identifies implications, invalid states and tied gatesIdentifies implications, invalid states and tied gates Handles industrial circuits with multiple clock Handles industrial circuits with multiple clock

domains and partial or no set/resetdomains and partial or no set/reset Increases number of detected and untestable faultsIncreases number of detected and untestable faults Significantly reduces sequential ATPG timeSignificantly reduces sequential ATPG time Applicable to redundancy identification, logic Applicable to redundancy identification, logic

optimization, and logic verificationoptimization, and logic verification