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Unit 8: Performing Static Timing Analysis8-1PrimeTime: Introduction to Static Timing Analysis
8-1
Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Agenda: Day Two
DAY2222 I/O Paths and Exceptions LabUnit
Introduction to Timing Models (QTM)7
8
Specifying Timing Exceptions6
Constraining I/O Interface Paths5
Summary9
Performing STA
Customer Support10
Unit 8: Performing Static Timing Analysis8-2PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
MOTIVATIONS
� EFFICIENCY: report_timing is NOT the most efficient report to uncover and direct solution efforts towards obtaining zero violations in the design
� COMPLETENESS: report_timing only uncovers timing violations. DRC, Pulse width and Max skew violations are NOT uncovered by the report_timing
Unit 8: Performing Static Timing Analysis8-3PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Unit Objectives
After completing this unit, you should be able to:
� Quickly find out the scope of violations (5 vs. 5000 violations in the design)
� Do a complete analysis to identify Timing and DRC violations
� Identify bottleneck blocks in the design as candidates for re-synthesis
� Provide “Info Reports” for the largest violations on input paths, reg-to-reg paths and output paths
Unit 8: Performing Static Timing Analysis8-4PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
The Inputs and Outputs of PrimeTime
Reports
PrimeTime
Technology Libraries
SDFTiming
Models in .db format
Gate-LevelNetlist Constraints Exceptions
SetupFile
Log,Script Files
Our Focus
Having applied all the inputs to PT, the goal is to generate various STA reports to analyze for Timing and Constraint violations.
Unit 8: Performing Static Timing Analysis8-5PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Five Step Static Timing Analysis Flow
READREAD
CONSTRAINCONSTRAIN
EXCEPTIONSEXCEPTIONS
CHECKCHECK
ANALYZEANALYZESTA: Any Violations?
Our Focus
Unit 8: Performing Static Timing Analysis8-6PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Three Analysis Techniques
report_constraint –all report_bottleneck
Violations
Constraint Report
1
Bottleneck Report
2
Timing Report
3
OK
Viol
atio
ns
report_timing
NOTE: The arrows are only a recommended sequence of generating reports. All 3 reports can be generated without following the indicated sequence. Bottleneck report can be generated only if there are violations.Given a floor planned Functional Core, you need to identify if there are any Timing/DRC violations and provide information to guide the iterative design decision. The goal of Analyze is to generate Timing and Constraint violation reports. In this unit, you will invoke 3 PT reports in the appropriate order.You will find answers to the following scenarios:
If I had started with a Timing Report that indicated no violations, Would I be done?If I had started with a Constraint Report that indicated no violations, Would I be Done?What is the magnitude and percentage of violations between registers and at the interface?
You will investigate causes for the violations due to: poor partitioning, excessive net fanout, larger capacitance load, slower transition time and so on.You will identify bottleneck block(s) for design budgeting and re-synthesis.
Unit 8: Performing Static Timing Analysis8-7PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
CHECK Before you Analyze
� Check the design to assure it is fully constrained
� To identify problems with design constraints:check_timing [-verbose]
✔ Missing clock definitions?
✔ Ports with missing input delay?
✔ Unconstrained endpoints for setup?
✔ Input /Output delay set without a reference clock?
✔ Combinational feedback loops?
✔ And more …
Example:Use “check_timing –no_clock” to quickly determine if all the Register to Register paths have been constrained.
Unit 8: Performing Static Timing Analysis8-8PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
ANALYZE Step1: Constraint Report
� “report_constraints” shows all types of violations in the design: � Setup� Hold � DRC � Pulse Width …
� The default is to show the longest violation of each type:max_delay/setup 0.61 (VIOLATED)
min_delay/hold 0.00
sequential_clock_pulse_width 0.00
max_capacitance 2.16 (VIOLATED)
max_transition 41.18 (VIOLATED)
How many are the design rules in the above report?
Unit 8: Performing Static Timing Analysis8-9PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Constraint Report: All Violations
� “report_constraints –all_violators” shows all the violations in the design and where the violations are:
Endpoint Slack
I_ALU/Zro_Flag_reg/D0 -0.28 (VIOLATED)I_STACK_TOP/TOS_int_reg[0]/D0 -0.22 (VIOLATED)
Timing Violationsmax_delay/setup ('Clk' group)
Required ActualPin Capacitance Capacitance Slack
Clk 0.00 0.03 -0.03 (VIOLATED)Reset 0.00 0.01 -0.01 (VIOLATED)
max_capacitance DRC Violations
If the report is empty, there are no violations.
The “-all_violators” shows the summary of all violations, one line per violation. If the report is empty, then there are no violations. You need to generate a timing report to understand the longest path (with constraints) that has the smallest amount of positive slack.
Unit 8: Performing Static Timing Analysis8-10PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
� How many end points violate Timing?
� What is the largest violation?� How serious is it compared to the Clock Period?
� Are the end points registers or output ports?
� Are there any design rule constraint (DRC) violations?
� Are the DRC violations real?� Are max_capacitance violations in the previous page real?
Constraint Report: Things to Investigate
pt_shell> redirect vio.rpt \
{report_constraint -all -max_delay -min_delay}
unix% grep “VIOLATED” vio.rpt | wc -l
report_constraint -all -max_capacitance -max_fanout
Each violation in the “vio.rpt” contains the pattern “VIOLATED”. An example of the output of the command: grep “VIOLATED” vio.rpt | wc –l
67max_delay/setup ('Clk' group)Endpoint SlackI_ALU/Zro_Flag_reg/D0 -0.28 (VIOLATED)I_STACK_TOP/TOS_int_reg[0]/D0 -0.22 (VIOLATED)max_capacitancePin Req. Capacitance Actual Capacitance SlackClk 0.00 0.03 -0.03 (VIOLATED)Reset 0.00 0.01 -0.01 (VIOLATED)
Are the DRC violations real?For example: The previous page shows that a max_capacitance of 0 was applied to the Clk and Reset ports – this is not realistic and points to a potential problem with constraints
Unit 8: Performing Static Timing Analysis8-11PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Three Analysis Techniques
report_constraint –all report_bottleneck
Violations
Constraint Report
1
Bottleneck Report
2
Timing Report
3
OK
Viol
atio
ns
report_timing
Constraint report showed a lot of timing violations. What next?
Control the temptation of invoking “report_timing” when you have a lot of violations. It is useful to determine if the violations have anything in common, for example: a heavily loaded cell (or) a poorly synthesized subblock.
Unit 8: Performing Static Timing Analysis8-12PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
ANALYZE Step-2: Bottleneck Analysis
� Bottleneck analysis identifies the cells (or blocks) which are involved in multiple violations
� report_bottleneck -cost_type path_count:
� path_count (the default cost_type) uses the number of violating paths through the cell as the bottleneck cost
Bottleneck Histogram
Bottleneck Cell List
pt_shell> report_bottleneck
****************************************Report : bottleneck-cost_type path_count-max_cells 20-nworst_paths 100****************************************
Bottleneck Cost = Number of violating paths through cell
Bottleneck Cell Reference Cost------------------------------------------------------------U2/U104 EO 100.00U2/U70 AN2 100.00…...U4/core Y_core 100.00U3/U106 OR3 99.00U5/U210 ND2 93.00U5/U207 ND2I 56.00
There are 2 other cost types (in addition to path_count).
•path_cost uses the total cost of violating paths through the cell as thebottleneck cost.•endpoint_cost uses the total cost of violating endpoints in the fanout of thecell as the bottleneck cost.
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� Identify subblock(s) containing bottleneck cells:� Refine subblock(s) by resynthesizing them
� Replace the subblock with a newly synthesized one:
� Re-generate Constraints report (“What if” analysis)
What can I do with Bottleneck Analysis?
A/D
RISC_CORE
USB RAM
MPEG
CODECDSP
Functional CoreCore Clock
U1_ALUALU1.db
read_db ALU1.db
current_design RISC_CORE
swap_cell U1_ALU ALU1.db:ALU
NOTE that PrimeTime only identifies what blocks are causing violations. PT cannot fix the problem. This is only a “What-if” analysis. To fix the problem, perform Design budgeting in Design Compiler and resynthesize the block using the constraints obtained after design budgeting.
NOTE that only the filename of the new design is changed to ALU1.db (example), the design name is still the same, ALU.
Unit 8: Performing Static Timing Analysis8-14PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Three Analysis Techniques
report_constraint –all report_bottleneck
Violations
Constraint Report
1
Bottleneck Report
2
Timing Report
3
OK
Viol
atio
ns
report_timing
Bottleneck report identified a subblock to be fixed. What else?
Before asking a synthesis engineer to resynthesize the bottleneck block, you can now provide him/her with more information regarding the context of block being used and where to find the violations.For example: Are the violations found at the I/O interface? Between registers? Between specific start and end points within the design?
Unit 8: Performing Static Timing Analysis8-15PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
� Timing report (report_timing) command finds all the individual timing paths in the design for analysis
� Each path is analyzed for timing twice:� Once for a rising edge input � Once with a falling edge input
� The critical path (worst violator) for each clock group is found and reported (default)
Analyze Step 3: Timing Reports
ZD Q
QB
D Q
QBFF2 FF3
MY_DESIGN
A
CLK1CLK2
path1 path2 path3
Constrained w.r.t CLK3
By default, how many paths of MY_DESIGN would be reported?
Unit 8: Performing Static Timing Analysis8-16PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Test For Understanding
� Which path will be reported by default, given the following?O Path Delays : 2 ns (path1), 3 ns (path2), 2.5 ns (path3), 2 ns (path4)
O CLK period = 5 ns
O Input delay (ref. CLK) on A = 1.5 ns, output delay (ref CLK) on Z = 1 ns
O Setup (FF2, FF3) = 0.5 ns, Clk-Q (FF2, FF3) = 0.5 ns
O Assume zero net delays
Timing Paths
D Q
QB
D Q
QB
FF2 FF3
MY_DESIGN
A
CLKCLK
path4
path1 path2 path3 Z
Constrained w.r.t CLK
Constrained w.r.t CLK
Unit 8: Performing Static Timing Analysis8-17PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Grouping the Timing Paths
� Timing paths are grouped into path groups by the clocks controlling their endpoints:� The “default” group contains paths not captured by a clock (OR)
not belonging to any user defined path group
� PrimeTime organizes its timing reports by path groups
path1
CLK1
path2
CLK2
Path Groups
ZD Q
QB
D Q
QB
FF2 FF3
MY_DESIGN
A
CLK1CLK2
path4
Timing Paths
path1 path2 path3
default
path3path4
MY_DESIGN
Unit 8: Performing Static Timing Analysis8-18PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Creating User Defined Path Groups
D Q
QB
D Q
QB
FF2 FF3
MY_DESIGN
A
CLKCLK
Z
path4
� A Timing path can ONLY belong to a one path group
� Always create groups to organize the timing paths meaningfully
path1
IN
path2
CLK
Timing Paths Path Groups
path1 path2 path3
COMBO
path3
path4
OUT
MY_DESIGN
group_path -name IN -from [all_inputs]group_path -name OUT -to [all_outputs]group_path -name COMBO -from [all_inputs] \
-to [all_outputs]
group_path command can be invoked from pt_shell or the command window of PT GUI. There is no menu option in the GUI for group_path.
Once you have created the groups, you can generate grouped timing reports as follows:report_timing -group CLKreport_timing -group INreport_timing -group OUTreport_timing -group COMBO
Unit 8: Performing Static Timing Analysis8-19PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Edge Sensitivity in Path Delays
What are the longest and shortest paths through these two inverters?
There is an “edge sensitivity” (called unateness) in a cell’s timing arc.
PT applies the appropriate unateness to each cell in a timing path.
library: pin(Z)intrinsic_rise : 1.8;intrinsic_fall : 0.5;
U1
library: pin(Z)intrinsic_rise : 1.5;intrinsic_fall : 0.7;
U2
Unit 8: Performing Static Timing Analysis8-20PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Example Timing Report: Circuit Diagram
D Q
presum_reg[1]
RISC_CORE
Z
ND2ND2
INV ZZ
D Q
FD1
U2U12
U23
clk1
data1
current_design RISC_CORE
report_timing -from data1 -to presum_reg[1]/D
Unit 8: Performing Static Timing Analysis8-21PrimeTime: Introduction to Static Timing Analysis
Path information section provides you with answers to several questions:-What type of path is being reported (input, reg-reg, output, combo?)-What path group does path belong to?-Is it a setup or hold time report?
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
****************************************Report : timing
-path full-delay max-max_paths 1
Design : RISC_CORE****************************************
Startpoint: data1(input port clocked by clk1)
Endpoint: presum_reg[1]/D(rising edge-triggered Flip-Flop clocked by clk1)
Path Group: clk1Path Type: max
Timing Report: Path Information Section
A timing report consists of four sections:1.Path Information section2.Path Delay section3.Path Requirement section4.Summary section
Unit 8: Performing Static Timing Analysis8-22PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Point Incr Path----------------------------------------------clock Clk1 (rise edge) 0.00 0.00clock network delay (ideal) 0.00 0.00input external delay 2.00 2.00data1 (in) 0.00 2.00 rU2/Z (INV) 1.54 3.54 fU12/Z (ND2) 0.98 4.52 rU23/Z (ND2) 0.66 5.18 fpresum_reg[1]/D (FD1) 0.81 5.99 fdata arrival time 5.99
Running Total ofthe Path Delay
Individual Contribution to Path Delay
Total Delay for the Path Unateness
Net & Cell Delays Are Combined
1.00.54
Cells in
Path
Timing Report: Path Delay Section
Path Delay section provides you with answers to several questions:What is the delay through each cell on the path?What cells have been used from the library?What is the path delay (or data arrival time)?What unateness (or edge sensitivity) has chosen for STA on this path?Does the path go through several (and how many) combinational hierarchies (snake path)?
In the default timing report, the cell delay is combined with the delay of the preceding net.You can show the net and cell delays separately by using: report_timing –input_pins.
Unit 8: Performing Static Timing Analysis8-23PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
u_int/U68/Q (INVB)
Incr Path
clock (input port clock) (rise edge) 0.00 0.00input external delay 22.40 22.40 faddr31 (in) 0.00 22.40 fu_proc/address31 (proc) 1.08 23.48 fu_proc/u_dcl/int_add[7] (dcl) 0.00 23.48 fu_proc/u_dcl/U159/Q (NAND3H) 0.62 24.10 ru_proc/u_dcl/U160/Q (NOR3F) 0.75 24.85 fu_proc/u_dcl/U186/Q (AND3F) 1.33 26.18 fu_proc/u_dcl/U86/Q (INVF) 0.64 26.82 ru_proc/u_dcl/U135/Q (NOR3B) 1.36 28.17 fu_proc/u_dcl/U136/Q (INVF) 0.49 28.67 ru_proc/u_dcl/U100/Q (NBF) 0.87 29.54 ru_proc/u_dcl/U95/Q (BF) 0.44 29.98 fu_proc/u_dcl/U96/Q (BF) 0.45 30.43 ru_proc/u_dcl/U94/Q (NBF) 0.84 31.27 ru_proc/u_dcl/U93/Q (NBF) 0.94 32.21 ru_proc/u_dcl/ctl_rs_N (dcl) 0.00 32.21 ru_proc/u_ctl/ctl_rs_N (ctl) 0.00 32.21 ru_proc/u_ctl/U126/Q (NOR3B) 1.78 33.98 fu_proc/u_ctl/U120/Q (NAND2B) 1.07 35.06 ru_proc/u_ctl/U99/Q (NBF) 0.88 35.94 ru_proc/u_ctl/U122/Q (OR2B) 10.72 46.67 ru_proc/u_ctl/read_int_N (ctl) 0.00 46.67 ru_proc/int_cs (proc) 0.00 46.67 ru_int/readN (int) 0.00 46.67 ru_int/U39/Q (NBF) 1.29 47.95 ru_int/U17/Q (INVB) 1.76 49.71 fu_int/U16/Q (AOI21F) 2.49 52.20 ru_int/U60/Q (AOI22B) 1.43 53.63 f
1.81 55.44 ru_int/int_flop_0/D (DFF) 0.00 55.44 rdata arrival time 55.44
Point
Spot the whales in the timing report: Where are they? What are they? And why?
Six buffers back to back?!
Rather late arrival for a 30 ns period!
11 ns delay for an OR gate is not good
Four hierarchical partitions
Timing Report: Spot the Whales
Unit 8: Performing Static Timing Analysis8-24PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Point Incr Path--------------------------------------------------clock CLOCK (rise edge) 0.00 0.00clock network delay (ideal) 0.00 0.00U3/OUTPUT_reg[12]/CP (FD1) 0.00 0.00 rU3/OUTPUT_reg[12]/Q (FD1) 3.97 3.97 f
. . . . . . . . . .U3/U148/Z (IV) 2.90 17.25 rU3/ZERO (REGCNT) 0.00 17.25 rU5/REGCNT_ZERO (CONTROL) 0.00 17.25 rU5/U232/Z (ND2) 0.64 17.88 fU5/U232/Z (XOR2) 2.77 19.65 fU5/U236/Z (IVA) 1.75 21.15 rU5/U193/Z (ND4) 1.38 22.53 fU5/Y_CONTROL[1] (CONTROL) 0.00 22.53 fU4/OPERATION[1] (Y) 0.00 22.53 fU4/core/MUXOUT[1] (Y_core) 7.24 29.77 rU4/MUXOUT[1] (Y) 0.00 29.77 rU2/DATA[12] (UPC) 0.00 29.77 rU2/U73/Z (ND2) 0.74 30.51 f
. . . . . . . . . .U2/U62/Z (AN2) 1.92 38.90 fU2/OUTPUT_reg[2]/D (FD1) 0.00 38.90 fdata arrival time 38.90
Point Incr Path--------------------------------------------------clock CLOCK (rise edge) 0.00 0.00clock network delay (ideal) 0.00 0.00U3/OUTPUT_reg[12]/CP (FD1) 0.00 0.00 rU3/OUTPUT_reg[12]/Q (FD1) 3.97 3.97 f
. . . . . . . . . .U3/U148/Z (IV) 2.90 17.25 rU3/ZERO (REGCNT) 0.00 17.25 rU5/REGCNT_ZERO (CONTROL) 0.00 17.25 rU5/U232/Z (ND2) 0.64 17.88 fU5/U232/Z (XOR2) 2.77 19.65 fU5/U236/Z (IVA) 1.75 21.15 rU5/U193/Z (ND4) 1.38 22.53 fU5/Y_CONTROL[1] (CONTROL) 0.00 22.53 fU4/OPERATION[1] (Y) 0.00 22.53 fU4/core/MUXOUT[1] (Y_core) 7.24 29.77 rU4/MUXOUT[1] (Y) 0.00 29.77 rU2/DATA[12] (UPC) 0.00 29.77 rU2/U73/Z (ND2) 0.74 30.51 f
. . . . . . . . . .U2/U62/Z (AN2) 1.92 38.90 fU2/OUTPUT_reg[2]/D (FD1) 0.00 38.90 fdata arrival time 38.90
Timing Report Exercise 1/2
How many hierarchical boundaries does this path traverse?
How many hierarchical boundaries does this path traverse?
Do any cells appear to have a relatively large delay?
Do any cells appear to have a relatively large delay?
Unit 8: Performing Static Timing Analysis8-25PrimeTime: Introduction to Static Timing Analysis
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Timing Report Exercise 2/2
clock CLOCK (rise edge) 30.00 30.00clock network delay (ideal) 0.00 30.00clock uncertainty 0.00 30.00U2/OUTPUT_reg[2]/CP (FD1) 30.00 rlibrary setup time -0.80 29.20data required time 29.20---------------------------------------------------------------data required time 29.20data arrival time -38.91---------------------------------------------------------------slack (VIOLATED) -9.71
clock CLOCK (rise edge) 30.00 30.00clock network delay (ideal) 0.00 30.00clock uncertainty 0.00 30.00U2/OUTPUT_reg[2]/CP (FD1) 30.00 rlibrary setup time -0.80 29.20data required time 29.20---------------------------------------------------------------data required time 29.20data arrival time -38.91---------------------------------------------------------------slack (VIOLATED) -9.71
Does the path meet timing?Does the path meet timing?
What is the percentage violation?What is the percentage violation?
Unit 8: Performing Static Timing Analysis8-26PrimeTime: Introduction to Static Timing Analysis
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Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Timing Report for Setup and Hold Checks
� Setup Check Report (default)report_timing -delay max
� Hold Check Reportreport_timing -delay min
� Setup and Hold Check Reports report_timing -delay min_max
� Multiple Timing Reportsreport_timing -max_paths 10report_timing -nworst 10
report_timing by default reports ONE path with the worst slack within each path group.
Analysis is performed to identifyThe slowest paths using setup time, worst case Cell delays, WLM and OC.
Analysis is performed to identifythe fastest paths using library Hold time.
The report contains the analysis of 2 paths: slowest and the fastest.
The report contains the analysis of at most 10 slowest paths.
Using large numbers for -nworst and -max_paths can lead to longer run times.
-nworst paths_per_endpointSpecifies the number of paths to be reported per endpoint. Allowed values are 1 to 2000000; default is 1.
-max_paths countSpecifies the number of paths to be reported per path group. Allowed values are 1 to 2000000; default is 1.
You can also generate non default timing reports by specifying the start or end or both start and end points:report_timing -from [all_inputs]report_timing -to [all_outputs]report_timing -from [all_inputs] -to [all_outputs]
Unit 8: Performing Static Timing Analysis8-27PrimeTime: Introduction to Static Timing Analysis
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Example -nworst vs. -max_paths
How many timing paths are in this picture?Which paths will be reported with report_timing -max_paths 2
What changes with report_timing -nworst 2 -max_paths 2
WNS = -0.3
WNS = -0.25
WNS = -0.15
WNS = -0.05
There are at least 4 timing paths in this picture.
report_timing -max_paths 2 will generate two reports considering only one path per endpoint. So in this example it will give you the paths with WNS = -0.3 and WNS = -0.15.
report_timing -max_paths 2 -nworst 2 will generate two reports considering at least two paths per endpoint. So in this example it will give you the paths with WNS = -0.3 and WNS = -0.25.
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Timing Report: Displaying path details
report_timing -input_pins -nets \
-capacitance –transition_time
Point Fanout Cap Trans Incr Path-----------------------------------------------------------------------------…...I_ALU/U1099/A (inv1a3) 0.31 0.00 0.61 rI_ALU/U1099/Y (inv1a3) 0.24 0.18 0.79 fI_ALU/N6422 (net) 3 0.04 …..
-nets -capa -tran
-input_pins
Cell delay
Net delay: Actually 0.004
-input_pins: Shows the net and cell delays by showing the timing to a cell’s input pins in addition (default) to the output pins.-nets: Show net fanout-capacitance: Show capacitance-transition_time: Show Transition timereport_timing -input_pins –significant_digits 3
Point Incr Path
--------------------------------------------------------------------
I_PRGRM_DECODE/Crnt_Instrn[25] (PRGRM_DECODE) 0.000 2.040 f
I_PRGRM_DECODE/U362/A (buf1a2) 0.030 2.070 f
I_PRGRM_DECODE/U362/Y (buf1a2) 0.450 2.530 f
report_timing -nets
---------------------------------------------------------------
I_PRGRM_DECODE/Crnt_Instrn[25] (PRGRM_DECODE) 0.000 2.04 f
I_PRGRM_DECODE/Crnt_Instrn[25] (net) 0.000 2.040 f
I_PRGRM_DECODE/U362/Y (buf1a2) 0.480 2.530 f
I_PRGRM_DECODE/n984 (net) 4 0.000 2.530 f
I_PRGRM_DECODE/U371/Y (xor2a0) 0.560 3.090 f
Unit 8: Performing Static Timing Analysis8-29PrimeTime: Introduction to Static Timing Analysis
8-29
Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Lab Overview
� You are provided with a design netlist that does not meet timing. Another set of subblocks that were improved for timing possibly at the expense of area are also provided.
� You are in charge of providing STA reports to the synthesis engineer and find if you can meet timing using some or all of the improved blocks.
LAB
45 min
Unit 8: Performing Static Timing Analysis8-30PrimeTime: Introduction to Static Timing Analysis
8-30
Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Review (1/2)
� State 3 techniques in the correct order for analyzing constraint violations in a design.
____________________________________________________________________________________
� List 2 types of violations detected by the constraint report.__________________________________________
� After a bottleneck analysis, using what command can you replace a violating block (or cell) with another?
____________________
Unit 8: Performing Static Timing Analysis8-31PrimeTime: Introduction to Static Timing Analysis
8-31
Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Review (2/2)
� How can you generate a single report containing one setup and one hold violations.
____________________
� How do you obtain the following details from a Timing report:Cell and net delays: _____________________Net fanout: _____________________Net capacitance: _____________________Cell input transition time: _____________________Cell output transition time: _____________________
� Name 2 methods by which you can obtain timing report of a path that starts at an input port and ends at an output port of a design. (Hint: Use of –from and –to options)
__________________________________________
Unit 8: Performing Static Timing Analysis8-32PrimeTime: Introduction to Static Timing Analysis
8-32
Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
APPENDIX: Reporting via PT GUI
Unit 8: Performing Static Timing Analysis8-33PrimeTime: Introduction to Static Timing Analysis
8-33
Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Constraint Report
Reports->
Analysis->
Constraint
1
All Violators2 OK3
Unit 8: Performing Static Timing Analysis8-34PrimeTime: Introduction to Static Timing Analysis
8-34
Performing Static Timing AnalysisPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Bottleneck Report
Reports->
Histograms
1
Timing Bottleneck
2