AFWAL-TR-83-2033 Advanced Aircraft Electrical System Control Technology Demonstrator a136758

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L - TR - 83 - 2033

ADVANCED AIRCRAFT ELECTRICAL SYSTEM - aCONTROL TECHNOLOGY DEMONSTRATOR- Phase I: Requirements Analysis & Prelim!nary Design- Phase I!: Detailed Design

"1.R. BoldtG. I.- DunnI) . E. HlankinsP. J. Leong1. S. Mehdi

BOEING MILITARY All'PLANE COMPANYSEATTLE, WASHINGTON

M4AY 1983

FINAL REPORT FO R THE PERIOD SEPTI'EMBER 1980 -- MARCH 1983

APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED

AIRO PROPULSION LABORATORYAIR FORCE WRIGHT AERONAUTICAL LABORATORIES AIR FORCE SYSTEMS COMMANDWRIGHT - PATTERSON AIR FORCE BASE, OHi!O 45433

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NOTICE-.hen ,-oterinment drawings, specifications, or other da.a are used fo r any purpose

> :2arin in connection with a definitely related Government procurement operation,U;hLnted States Government thereby incurs no responsibili ty nor any obligation,hitsoever; and the fact that the government may have formulated, furnished, or :nn& way supplied the said drawings, specifications, or other 7ata, is not to be re --arded b"t implication or otherwise as in any manner licensing the holder or anytoer petaon or corporation, or conveying any rights or permi -sion to manufacture

or i;i anu patented invention that may in any way be re'ated thereto.

"This resort has been reviewed by the Office of Puhblic Affai *s (ASD/PA) and is-o the National Technical Information Service (NVTT :). At NTIS, it will-va;:aLIe to the general public, including foreign nations

This r:,:


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SECURITY CLASSIF"C:ATION 01 TwIS PAGE (When O)pt .Fnfltered)5 OrUMENTAT'ON PAGE - - READ INSTRUCTIONSREF____RT .. .._________AGE BEFORE COMPLETING FORMNEPORT NMUJ-_FR .GOV ACCESS NO 3 RECIP ENT'S CATALOG NUMBERAFW"IL- TR-833-2033 A

4, TITI.E (end Suhttl'e, S. TYPE OF REPORT & PERIOD COVEREDADVANCED AIRCRAFT ELECTRICAL SYSTEM CONTROL Final Report for PeriodTECHNOLOGY DEMONSTRATOR Sept 1980 - March 1983Phase 1: Requiremetnts Analysis & Prelim. Design 6. PERFORMINGOIGtEPORTNUMBFRPhase II: Detailed Design D180-25927-47. All (-I-O... . 8. CONTRACT OR GRANT NUMBER(.)G. L. Dunn T. R. Boldt F33615-80-C-2004P. J. Leong D. 17. Hankins FI. S. Mehdi) ,LRFOF7MIN3 NOFGA_I4ZATION NAMF AND ADORfESS 10. PROGRAM ELEMENT, PROJECT, TASKMechanical/Electrical Systems Technology ARCA & wORK UNIT NUMBERSBoeing Military Airplane CompanyM/S 47-03, P.O. Box 3707, Seattle, WA 981241 CONTNOLLIN(I OFF I N AMF AND ADDRESS 12. REPORT DATEAero Propulsion Laboratory (AFWAL/POOS) May 1983Air Force Wright Aeronautical Laboratories, AFSC ,13 N U M E n O F PAGESWright-Patterscn AFB, Ohio 45433 154

14 MON IT ORIN AG;ENCY N AME A A NDN _S';if df.erent from (rottrolling Othce) 15. SECURII Y CLASS. (of thif report,

UNCLASSIFIED-S-." DECLASSIFICATIONYDOWNGRADINGSCHEDOJLE

16 DISlTFOOUTION ~ l'r~f,pproved( for public release; distribution unlimited

17. DISTRIEI'J1 IO(N STATIEMENT :1 t7.. ,hsrr,.t enter,! ,,' 111.-< 20. it ifferent from Report)

18. SUPPLEMENTARY NOTES

19. KEY WORDS (Corttinise cn r%-ftrse side of necessary and identify by block number)DAIS Interbus ProcessorElectrical Load Management Center (ELMC) Load ManagementElectrical System Remote Terminal (RT)Solid State Power Controller (SSPC) EMUX

20, ABSTRACT (Continue on reverse side It neceseary and Identify by bluck number)Thiz report summarizes Phase I and documents the results of Phase If of thistwo-phase program. Phase I covered a preliminary design of the advancedaircraft electrical system (AAES). This included a requirements analysisan d an evaluation of concepts applicable to the system design. Phase IIcovered the detailed design of the AAES and support hardware an d softwarenecessary to demonstrate the system in the laboratory. In addition, Task 3of Phase II covers the conceptual design of a multiple data bus architecturefor the AAES. Key characteristics of the AAES are:

DD JAN73 1473 COITION OF INOV65 S OBSOLETE UNCLASSIFIEDSECURITY CLASSIFICATION OF THIS PAGE (Wten D'ate Entered)


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SECURITY CLASSIF !C A'1ION OF THtIS PA(;GF(4e Date Entee.d)

20. ABSI7'KC1 (,;on Iinued)o Irintt rated avionics and power data bus configuration consisting of

Digit..il Av:onics Information System (DAIS) standard elements (MIL-STD-17D :)rzce:;sor, MIL-STD-1553B data bus, controls and displays, andremoi te. tOetiiinals (RT).

o Intel Ii Len; Electrical Load Management Centers (ELMC) capable ofcontrollnj power to loads.o [uilt-ir--tbst (BIT) capability to isolate faults to the module level.BIT includes both circuit and data monitoring checks.o Sol-d St atr Power Controllers (SSPC) to replace circuit breakers andpowe, control switches. SSPCs are turned on/off via, computer control.o Geiorator :ontrol, protection and status monitoring by a GeneratorControl Unit (GCU) compati!)le with DAIS hardware and software.o Multimission data information system through programmable systemprccessors, ELMCs and standard DAIS elements.o Autcratic load management for increased aircraft survivability andprouTabi'li ty of mission completion.

UNCLASS IFI EDSF-CuJRITY CLASSIFICATION OF T'" PAGECWhen Date Enter.d)


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PREFACE

This Technical Report presents the -esults of work performed by the BoeingMilitary Airplane Company, Seattle, Washlngtor, under Air Force ContractF33615-80-C-2004, during the period from September 1980 through March 1983.The work is sponsored by the Aero Propulsion Laboratory, Air Force WrightAeronautical Laboratories, Wright-Patterson Air Force Base, Ohio, underProject 3145, Task 314529, Work Unit 31452959 with Mr. Duane G. Fox,AFWALiPOOS-2, as project engineer.

The Harris Corporation, Melbourne, Florida and the Eaton Corporation,Milwaukee, Wisconsin were subcontracted to provide information andconsultation in the areas of multiplex data bus equipment and solid statepower control I ers.

This report covers ?hase I and Phase II of a two 0hase program to design anadvanced aircraft electrical system. Phase I cove-ed a preliminary design ofthe electrical system. This included a requirements analysis and anevaluation of concepts applicable to the system design. Phase II covered thedetailed design of the advanced aircraft electrical system and laboratorysupoort hardware to demonstrate the system in the laboratory. In addition,task ? of Phase II covers the conceptual design of a multiple data bus3rchitecture fo r the advanced aircraft electrical system.

The program manager was I. S. Mehdi. The report was prepared by T. R. Boldt,G. L. Dunn, D. E. Hankins, and P. J. Leong who were technically responsiblefo r the work. Feessson For -

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TABLE OF CONTENTS

SECTION PAG

I. INTRODUCTION 11. Background 12. Proqram Objectives 23. Approach 2

II. REQUIREMENTS ANALYSIS 71. Electrical System Requirements 7

a. Load Analysis 8b. Generation System 10c. Distribution System 11d. Flight Critical Power 11e. Power Bus Configuration 12f. System Contrnl and Protection 12g. Applicability of J73/I (Jovial) 17h. Controls and Displays 17

2. Control System Requirements 20a. Processing Requirements 22b. Input/Output Requirements 23c. Response Time 23d. Avionics Bus Loading 24

3. Technical Analysis 25a. General Assumptions 27b. Processor Loading 28c. Data Bus Loading 29d. Memory Requirements 30e. Reliability 31f. Results of the Technical Analysis 31

4. Economic Analysis 32

III. CONCEPTUAL DESIGNS 341. Bus Architectures 34a. Data Bus Archi"'ictures 34b. Non-Integrated Data Bus Architecture 35

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TABLE OF CONTENTS (continued)

SECTION PAGE

c. Integrdted Data Bus Architecture 37d. Hierarchical Data Bus Architecture 39

2. Selected Concept 39

IV. SYSTEM HARDWARE AND SOFTWARE DEVELOPMENT 421. System Specification 42

a. Power Generation Subsystem 42b. Power Distribution Subsystem 46c. Control Subsystem 49d. Real Tine System Software 51e. Non-Real Time Support Software 51

(1) Jovial JT3 Compiler 51(2) ALAP Assembler 52(3) Partitioning Analyzing and Linkage Editing 52

Facility (PALEFAC)2. Hardware Specifications 54

a. Power Systemi Processor 55b. Electrical Load Management L,,nter 55

(1) Power Distribution Center 57(2) SSPC Control and Monitoring 57c. Electrical Remote Terminal 57

(1) MIL-STD-1153B Data Bus Interface 60(2) I/O Bus Irterfa.,e 6")(3) Electrical Power Interface 60(4) ER T Software Computations 60(5) Built In Test 61

d. Solid State Power Controller 61e. Eleztromechanical Power Controller 61

3. Software Specifications 65a. Power Sys'em Processor Executive 65b. Power System Proces.or Applications 67c. ElectrIcAl Remote Terminal Executive 69d. Electrical Remote Terminal Applications 71

4. Svstem Drawings 71

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SECTION PAGE

V. SUPPORT HARDWARE AND SOFTWARE DEVELOPMENT 791. Laboratory Simulator Design 79Z. Simulator Hardware Specifications 79

a. System Test Console 79b. Avionics Simulator 85c. Bus Monitor 85

3. Simulator Software Specifications 85a. Avionics Simulator 95b. Bus Monitor 87

4. Test Plans 3nd Procedures 875. Safety Anal3sis 876. Relidbility and Maintainability 89

a. Reliability Evaluation 89b. Maintainability Evaluation 89

VI. MULTIPLE DATA BU S ARCHITECTURE INVESTIGATIONS 931. System Requirements Definition 93

a. Generic Multibus System Configuration 94b. Interbus Data Transfer Requirements 97

(1) Type of Data 97(2) Quantity of Data 97(3) Timing Constraints 98(4) Redundancy Requirements 101(5) Reliability Requirements 103

c. Interbus Processing Requirements 103d. Requirements Summary 105

2. Interbus Connection Device Evaluatien 105. Identification of Interbus Devices 105

(1) Generator Control Unit (GCU) 106(2) Electrical Load Management Centet (ELMC) 106(3) DAIS Remote Terminal (RT) 107(4) Power System Processor (PSP) 108(5) Dedicated Remote Terminal (RT) 109(6) Special Purpose Interbus Processor 110

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SECTION PAGE

b. Selection of the Interbus Devices 110c. Identification of Redundancy Mode 114d. Identification of Interbts Configuration 117

3. Trade Study Conclusions and Recommendations 1234. Conceptual Design of a Multibus System 125

a. Hardware 127b. Software 127

5. Simulator Support Hardware/Software Design 131

VII. RESULTS AND CONCLUSIONS 133

VIII. RECOK4ENDATIONS 139

REFERENCES 141

APPENDIX-DOCUMENTATION, DRAWINGS, SPECIFICATIONS 142

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ILLUSTRATIONS

FIGURE PAGE

1 Phase I Program Flow Chart 42 Phase II Program Flow Chart 63 Electrical Load Profile 94 Flight Critical Bus in the ELMC 135 Power Bus Configuration 146 Load Management Matrix 187 Load Management Level Selection 198 DAIS Integrated Controls/Displays 219 Data Bus Architecture Configi,.atiuns 26

10 Baseline Non-Integrated Architecture 3611 Integrated Architecture 3812 Hierarchical Architecture 4013 Advanced Aircraft Electrical System Configuration 4314 Integrated Data Bus Architecture 4415 Power Generation Subsystem 4516 Power Generation Subsytem Control Circuit 4717 Distribution Subsytem Power Flow 4818 Electrical Control Subsystem 5019 PALEFAC Structure 5320 ELMC Functional Block Diagram 5621 ELMC Power Distribution Center 5822 ER T Functional Block Diagram 5923 SSPC Circuit Card 6224 PSP System Architecture with PSP Executive 6625 PSP Applications Software Modules Diagram 6826 ER T System Architecture with ER T Executive 7027 ERT Applications Software Structure 7228 System Data Bus Diagram 7329 System Data Flow 730 System Power Flow 7731 Data Bus System Configuration 8032 Laboratory Floor Plan 8133 Physical Layout of Simulator Hardware 82

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ILLUSTRATIONS (continued)

FIGURE PAGE

34 Syctem Test Co~isole 8335 Simulator Equipment Rack 8436 Avionics Simulator Functional Block Diagram 8637 Avionics Simulator Software Functional Block Diagram 8838 AC Power Loss Fault Tree 9039 DC Power Loss Fault Tree 9140 FC DC Power Loss Fault Tree 9241 Generic Multibus Configuration 9542 Candidate Interbus Connections 9643 Data Transfer Timeline 10044 Irterbus Device Data Patl.s 10245 Redundant Interbus Device Data Paths 10446 Redundancy Candidates 11647 Interbus Configuration Candidates 11948 Reconmmended Configuration 12649 AEPS Multiple Data Bus Architecture 12850 Multibus Configuration for AAES 12951 Multibus Processor Executive 13052 Laboratory Simulator Block Diagram 132

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TABLES

TABLE P

I Electrical Load Analysis Summary2 Solid State Power Controller Dictribution3 Baseline Avionics Data Bus Loading4 Distribution of SSPCs Per ELMC5 EMPC Requirements6 Relative Merits of Interbus Device Candidates7 Identification of Suhscripts in Reliability Equations8 Evaluation of Interbus Configurations

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SUMMARY

In this study, advanced1 concepts pertaining to electrical systems wereinvestigated. These concepts were then applied to the design o. an advancedaircraft electrical system (AAES). As part of this study, a laboratorydemonstrator for the AAES was also designed. The AAES is designed to meet therequirements for a 1990 time frame two-engine tactical aircraft withmultimission capability. The sy3tem performs the following major functions onthe aircraft.

o Provide electrical power to meet all mission requirementso Distribute electrical power to the loadso Provide electrical system protectiono Control the distribution of electrical power and provide load management

Electrical power generation consists of those functions necessary to assurethat proper quality power is provided for distribution. Distribution ofelectrical power relates to the electrical bus structure, AC and DC , alongwith reliability and redundancy considerations to ensure that t1-e generatedelectrical power is optimally delivered to the loads. Electrical systemErotection involves the automatic detection and isolation of system faultssuch as short circuits and generator failures. Finally, control of powerdistribution encompasses the on/off control o*' , ,vidual loads, load sheddingand load sequencinq.

The key characteristics of the AAES are:

o Integrated avionics and power data bus configuration consisting of DigitalAvionics Informaticn System (DAIS) standard elements (MIL-STD-1750processor, MIL-STD-1553B data bus, controls and displays, and remoteterminals RT).

o Intelligent Electrical Load Management Centers (ELMC) capable ofcontrolling power to loads.

0 Built-in-test (BIT) capability to isolate faults to the module level. BITincludes both circuit and data monitoring checks.

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Solid State Power Contro., "s (CrIor1,to replace circuit breakers and pcontrol switches. SSPCs are turned on/off via computer control.Generator control, protection and status monitoring by a Generator ConUnit (GCU) compatible with DAIS hardware and software.[ Multimission data information system through programmable systemprocessors, ELMCs and standard DAIS elements.

o Automatic load management for increased aircraft survivability andprobahility of mission completion.

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,E SECTION IINTRODUCTION

1. BACKGROUND

The Air Force Wright Aeronautical Laboratories (AFWAL) Aero PropulsionLaboratory has been sponsoring research and development programs directedtoward applying advanced solid state power switching and computer controltechnology to aircraft electrical power systems. Development of componentsand subsystems utilizing solid state power switching an d microprocessor-basecomputer technology has progressed rapidly. Multiplexing techniques have bedeveloped for transmission an d processing of electrical system control data.This data usually consists of a large number of discrete (on/off) signals aninformation for solving control logic equations. Multiplex hardware andsoftware designs have been optimized for electrical system controlapplications such as the B-i E-Mux system. This, however, results in highinitial development, integration an d logistics costs. On large aircraft theamount of siqnal processing an d data transfer may justify the use of aseparate and optimized multiplex system for electrical system control;however, in the case of smaller aircraft this may not be the most costeffective solution.For small aircraft, where the electrical system signal processing and datatransfer may not be a; large as for the B-1, it may be possible to integrateelectrical system control with the avionics system in a single data bus systas developed in the Digital Avionics Information System (DAIS) program.Previous studies, such as AFAPL-TR-73-41 (Reference 1), examined this concepand concluded that integration was possible. Inteqration of the electricalpower control was also examined in the DAIS program but wat not implemented.Areas of concern with such integration are that the electrical power controlwas also examined in the DAIS program but was not implemented. Areas ofconcern with such integration are that the electrical power redundancyrequired for mission essential functions may not be adequate for flightcritical functions. Another area of concern is that if the electrical powersystem is controlled by the multiplex system and in turn the multiplex syste

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requires electrical power to operate, procedures nust be devised to power-upthe system. The third area of concern is that growth of the data bus trafficmay reach the point where system complexity would negate the technical andcost advantages of an integrated system.

In order to permit evaluatio., of aircraft electrical power system design,laLtoratory simulators need to be designed and built. An A-7 electrical systemsimulator (Reference 2) was built by the Aero Propulsion Laboratory fordemonstrating functional operation of the solid state distribution concept andto show that electromagnetic interference (EMI) presented no problem.Therefore this simulator was built so that it would have the same groundplanes and shielding that exists on the A-7 aircraft. This type of simulatorhas several disadvantages such as, difficulty in maintenance due to tighthardware locations, difficulty in making changes to the wiring harness, andpoor utilization of laboratory floor space.

Modular concepts of building a laboratory simulator (Reference 3) provide theadvantages of lower cost easy modification and more universal application,even though they do not allow for adequate EMI evaluation. To date nosimulator has been developed to evaluate integr-ated power and avionics databus control concepts.

2. PROGRAM OBJECTIVES

The overall objective of this contract was to develop an aircraft electricalpower distribution and control system that is integrated to the fullestpractical extent with an aircraft digital avionics information managementsystem. Specifically this program had two distinct objectives. They were,first to define the requirements and conduct the design of a computercontrolled, solid state electrical power distribution and control system for asmall two engine tactical aircraft, and second to develop the design of alabor-itory simulator fo r evaluation of the aircraft electrical system.

3. APPROACH

To achieve the objectives of this program, a two phase study with three tasksin Phase I and three tasks in Phase II was undertaken. The tasks for eachPhase were as follows:

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Phase I Analysis an d Preliminary DesignTask 1 Requirements AnalysisTask 2 Conceptual DesignTask 3 Preliminary DesignPhase II Detailed DesignTask 1 System Hardware and Software DevelopmentTask 2 Support Hardware and Software DevelopmentTask 3 Multiple Data Bus Architecure Investigations

The program flow chart for Phase I is shown in Figure 1. During Task 1 therequirements were defined for the electrical power system and the integratedpower system control for a small two engine tactical aircraft which will becapable of performing various missions (fighter, attack, reconnaissance,trainer, electronic warfare, fighter bomber). In addition, a data base ofinformation regarding subsystems and component hardware and software of anAdvanced Electrical Power Systems (AEPS) simulator was accumulated. Therequirements definition and data base were developed with the primaryobjective of achieving the most cost effective designs for both the aircraftelectrical system ard electrical system laboratory simulator. To keep thesystem cost at a minimum, the program was tailored so the requirements metclosely as possible the existing electrical and DAIS system requirements andapplicable hardware an d software available at the AFWAL Aero Propulsion andAvionics Laboratories. Also, during Task 1 an evaluation of the AeroPropulsion and Avionics Laboratories and equipment was made. This evaluatiohelped to arrive at a cost effect design of the laooratory simulator throughutilization of existing hardware.

In Task 2 each of 3 data bu s architectures (single integrated bus,hierarckical integrated bus, separate dedicated/non-integrated bus) wereconfigured with options ranging from all computation&l capability residingthe digital p'(._-ssor (mission computer) to most of the processing relegatedto remote terminals. Based on these options, AEPS conceptual designs wereprepared. A tabulatiun of all the relevant parameters including processor/bloading, reliability, memory, an d cost was made. The baseline for thearchitectural studies was the separate dedicated/non-integrated data bus.

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Both the hierarchical integrated bus and the single integrated bus wereevaluated ajainst this baseline. Based on the architectural trade studies,one of the three cortrol architectures was reconrrended for preliminary des

In Task 3 a preliminar-y design of the electrical system with the selectedarchitecture was conducted. System block diagrams, functio,ldl flow diagramdata flow diagrams and key event/timing diagrams were prepared for theelectrical system. Draft specifications for the har,'frare and software forvarious component- of ti,- system were also prepared. A preliminary hazardanalysis of the systcm was conducted and a detailed development plan for PiH s prepared.Two reports were published covering the results of Phase I. ReDortAFWAL-TR-81-2058 (Reference 4) covers Tasks 1 an d 2 and teportAFWAL-TR-81-2128 (Reference 5) covers Task 3.

The program flow chart for Phase II is shown in Figure 2.During Task 1 the Jetail design of the electrical power generation anddistribution system was completed, based on the preliminary design conductein Phase I, Task 3. Documents prepared included the Advanced Electrical PSystem (AEPS) system specification, system safety analysis, and hardware ansoftware specifications.During Task 2 the detail design of the laboratory simulator to be used forelectrical system evaluation was conducted. Overall simuiator specificatioalong with hardware and software specifications for the support equipmentprepared.

Task 3 covereJ investigations of multiple data bus architectures and includdefinition of system requirements, trade study evaluation of the alternativand conceptual desigr of a multibus system including the simulator supporthardware and software.This Final Technical Report summarizes Phase I and covers the results of PII.


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SECTION II

REQUIREMENTS ANALYSIS

1. ELECTRICAL SYSTEM REQUIREMENTSDesign options were developed for an electrical power system for a smalltactical two engine aircrdft with advanced avionics ard fly-by-wire (FBW)flight controls. The following assumptions were made to arrive at theelectrical system requirements:

o 2 Engine Driven Generatorso 1 Flight Operable Auxiliary Generatoro '4ission Completion With 1 Main Generatori Safe ketirn With Auxiliary Generatoro Triple Redundant Fly-By-Wire Flight Control SystemL FBW Electronics will be Powered by DC Powero Solid State Distribution

A primary generator is drivei by each engine. The auxiliary generator isdriven by a flight operable auxiliary power unit.

The electrical power system requirements include provisions to interface withe following subsystems.

Automatic Flight Control FuelAuxiliary Power Hydraulic PowerCommunications InstrumentsCrew Escape Landing Gear

I Engines Life SupportEnvironmental Control NavigationFlight Controls Stores Management

* The degree to which the electrical power system interfaces with other airplasystems varies. For some subsystems, such as automatic flight controls, theinterface will be only to provide power and caution and warning indication.


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For other subsystems, such as environmental control, allocations were made formore extensive interfacinq, such as on/off control of equipment and sensordata communication.

a. Load Analysis

Spvcral aircraft with dliff-rent missions were surveyed with the intent ofdetermining the effect of the mission on the generation capacity (Reference4). The survey showed that the fighter, electronic warfare, and fighterbomber missions required the most electrical power. The power requirementswere also dependent on the number of crew members.

The trend for new aircraft is toward more electrical power generationcapacity. This is the result of increased sophistication in avionics,weapons, and flight control systems. Aircraft dedicated to electronic warfaremissions require greater amounts of power. Next to the electronic warfaremission, the fighter and fighter bomber aircraft have the highest powerrequirements.

A load analysis for a two engine tactical aircraft was developed. Theanalysis is based on the air-to-surface fighter which Boeing is studying. Theload analysis encompasses the fighter and fighter-bomber missions and also hassome EC M capability. A load profile developed from the analysis is shown inFigure 3. The load analysis is summarized in Table 1.

TABLE 1. ELECTRICAL LOAD ANALYSIS SUMMARYMAXIMUM CONNECTED SUSTAINED PEAK EMERGENCY

LOAD LOADTOTAL AC POWER 58477 VA 12577 VATOTAL DC POWER 7805 WATTS 2630 WATTSTR U LOSSES 1377 WATTS 465 WATTSTOTAL TRU INPUT POWER 9182 WA TTS 3095 WATTSTOTAL AC AN D DC POWER 67659 VA 15672 VA

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b. Generation System

Using the load analysis an d the mission effects analysis as a base, thegeneration an d distribution system was sized. The equipment complement isshown below.

2-60 KVA 115/200 VAC Generators1-20 KVA 115/200 VAC Auxiliary Generator3-100 Amp 28 VDC Transformer Rectifier Units

Two 60 KVA main generators allow mission completion with one generator out.Three 100 amp transformer-rectifier units (TPRU) provide the system's DCpower. The TRUs are sized to provide power for all connected loads. Two TRUswili provide enough DC power for mission completion.

Based on the circuit breaker counts of three aircraft and the Reference 6study, the nunmer of solid state power controllers (SSPCs) selected for thisaircraft was 500, distributed as shown in Table 2. Loads requiring SSPCslarger than 7.5A AC or 20A DC are controlled by discretely packaged SSPCs orelectromechanical power controllers (EMPCs).

TABLE 2. SOLID STATE POWER CONTROLLER DISTRIBUTION115 VAC

SIZE PERCENT TOTAL2A 31.53A 8.55A 77.MA 3

28 VDCSIZE PERCENT TOTAL

2A 373A 6.55A 27.5A 20IA 1.5

155A .520A .5

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c. Distribution System

The distribution system consists of distributed electrical load manag-2mentcenters (ELMCs). Previous studies (Rsferences 6 and 7) have shown that thdistributed concept lowers vulnerability to combat damage and in some caselowers total system weight when compared to a single centralized distributcenter. Individual loads are connected to the ELMCs rather than to the melectrical power buses as in conventional electrical systems. Power to thloads is controlled by SSPCs housed in the ELMC.

Five ELMCs, in the left an d right forward avionics bay, left and right winarea and in the cockpt area, provide coverage for the entire aircraft.The primary functions of the ELMC are to house the SSPCs and interface theSSPCs to the data bus. To maximize the utility of each box on the data buthe ELMC will include additional functions such as those incorporated in RThis will minimize the number of boxes on the data bus. Additionalcapabilities included in the ELMCs are analog-to-digital (A/D) conversiondiscrete input/output (i/O).The ELMCs handle 15% of the system's discrete I/O data transfer. Remoteterminals (RTs) handle 80% of the discrete I/O data transfer an d the rema5'T, is allocated to the generator control units (GCUs). Preliminary designan RT indicates a capacity of approximately 250 inputs and 118 ouputs canpackaged in a 4 MCU (1/2 ATR) size box. Based on such a design, three RTrequired to handle the I/O requirements of the system.d. Flight Critical Power

As a design philosophy, each channel of the flight control system must havits own independent power source. These sources may be cross tied foradditional redundancy. For a triple redundant flight control system, threindependent power sources are thus required. With DC, this provision iseasily met by using three TRUs. With AC, the main generators provide twosources. A third source cani be an inverter powered from a DC bus. A drawto using AC power is the lack of a simple method for providing uninterruppower to the flight critical equipment. With DC power, this is accomplishby paralleling the sources.

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DC power is recommended fo r the flight critical systems. In the selectedconcept (Figure 4), a flight critical bus is provided in each ELMC. Each busis powered by its own TRU. Backup power is provided by a battery which isparalleled with the TRU. Any number of flight critical equipments can beconnected to the bus; however, where redundancy is required, such a, a tripleredundant flight control system, only one channel of equipment is cotnected toeach bus. Having a flight critical bus in the .LMC provides more versatilityand reduces the number of load feeders. The vulnerability of the load due tothe sinqle feeder is minimized by short feeder lengths resulting from having 5ELMCs dist,-4buted throughout the aircraft.

e. Power Bus Configuration

The selected electrical power bus configuration is shown in Figure 5. Onlythree of the five ELM,;s are shown. Bus ties are incorporated in thisconfiquration. In the AC system, the bus ties eliminate the need for s.paratepower feeders for the auxiliary generator. The auxiliary generator suppliespower to the ELMCs through the main generator buses. The DC bus ties allowthe TRUs to be paralleled and to share power feeders.

f. System Control and Protect;:n

The system control and protection provides for automatic operation andcoordinated fault isolation. Control and protection is sectionalized into thefollowing areas: generator, distribution, and loads. The objectIves ofcontrol and protection is to :

o Reduce crew work loado 'ncrease flexibilityo Increase survivabilityo Increase probability of mission success

The reduced crew work load is achieved by automation. The use of digitalprocessors and data bus communication lines link the various subsystems andallow coordination of most of the components of the electrical system withother aircraft subsystems.

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ELMVCFLIGHT CRITICAL BUS

FB W EQUIPMENT

Figure 4. Flight Critical Bus in the ELMC

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Flexibility is achieved by programmable digital processors which control thesystem and the individual SSPCs. The capability to reconfigure the systemqreatly enhaitces system flexibility.

Increased survivability and probability of mission success are achieved bycoordination of all electrical functions and a comprehensive load managementprogram. Automatic switching provides for fast fault isolation, busswitchinq, and load shedding. Load managment diverts power to flight andmission essential loads in the event of a decrease in available power.

The control and protection functions for both the main and the AP U generatorare shown below.

Generator Protection

o over/under frequency o over/under voltageo open phase o input underspeedo differential protection o failed rotating rectifiero overload

Generator Control

o voltaqe regulationo frequency reclulationo generator contactor

For advanced aircraft which depend on electrical power for mission completionand flight control, protection and control of the primary qenerating system iscritical. To provide maximum fault isolation and to provide the necessaryresponse time for the control of an aircraft generator, the control andprotection of the generator is accomplished by the GCU and is not delegated tothe system processors. The control and sensor lines to the generator arehardwired. The GC U is connected to the data bus. However, the generatorcontrol and protection functions operate independently of data bus servicefunctions. This isoiaLes the generaLo, from, data bus failures. The data bu sis used to carry data such as overload instructions, maintenance information,and fault indications, between the GC U and the system processors. Having the

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GCU hardwired to the generator also facilitates system startup from e "dead"airplane. In addition, loads necessary during startup are controlled by ,SPCswhich are in the closed state when no control signal is present.The distribution system includes the main buses, external power receptaclesan d distribution feeders. The function of the distribution protection systemis mainly to provide fault isolation. The protection and control functionsassociated with the distribution system are shown below.

Protection

o fault protection and isolationo abnormal external power protection

Control

o bus tie breaker controlo external power breaker controlo power distribution to ELMCs

The versatility an d survivability of the aircraft is enhanced with themultiplexed data bus control of the loads. All loads are under system controland status of the loads is constantly monitored. Load control is accomplishedby the solution of Boolean control equations. There i one equation for eachload. The equation takes the form shown below.

C = U P (R + Q)C = SSPC On/Off Control Signal1.= Trip latchP = Priority SignalR = Request for Power (Solution of a Boolean Equation)Q = Test Request (Such as Ground Test)

The variable R is the output of a system equation consisting of inputs fromthe system's RTs and ELMCs. The priority signal, P, is used to implement loadmanagement. Sixteen load management levels are available. Each level

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represents a different set of priority signals for the SSPCs. At each leveeach SSPC has an assigned oriority, P. A P set to "0" inhibits or commandsthe SSPC to turn off. A "1" allows the SSPC to turn on. The relationshipthe P variable an d the load management levels can be visualized as a 16 x 5matrix (500 SSPCs in the system) of "is" and "Os". Depending on the loadmanagement level implemented, a preselected combination of 500 "Is" and "Osare substituted for the variable P in the SSPC control equations. The loadmanagement matrix is shown in Figure 6. Various system parameters are usedlogically select on e of the sixteen load management levels. The level canalso be selected manually. Figure 7 shows parameters which are used indetermining the load management level.g. Applicability of J73/I (JOVIAL)The evaluation of the applicability of JOVIAL higher order language toelectrical systems was investigated. A literature search aimed at acomparison of the efficiency of assembly and higher order languages wascLiducted. The actual coding of two typical power control routines in bothJLVIAL and assembly language was done for comparison. The analyses wereperformed using J73/I; however, J73/I has since been superceded by J73. Thchanges made in the language have been in the area of syntax and data typeconversion. Also, a few new functions have been added. The differencesbetween J73/I an d J73 are minor and do not affect the results of the analysBased on the results of the literature search and codinq evaluation, it wasconcluded that J73 should be used as the programming langu-ge.h. Controls and Displays

An analysis was done to establish the requirements for the controls anddisplays of the electrical system. The aim of the design is to minimize thcontrols, an d only display that information which is essential for the piloto maintain aircraft safety an d to assure mission success.In keeping with this objective, no panel indicators are provided forindividual SSPC status or trip indication an d individual SSPC reset control.Indi'ation of a failed or tripped SSPC appears on the appropriate sub-otem

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warning panel or equipment war'.ing panel. A control panel is required for theDAIS processors. It provides power to the appropriate processor duringstartup and restart control for any architecture.

A CRT display dedicated to the electrical system is not feasible in a twoengine tactical aircraft; however, it is feasible to display electrical systemdata on the avionics display units. This integrated CRT display concept ispossible with the integrated data bus architecture and the hierarchical databus architecture. An example of this integrated controls/displays concept,which uses existing DAIS hardware, is shown in Figure 8. Only key systemfailures which affect the mission success are displayed on the CRT.

2. CONTROL SYSTEM REQUIREMENTS

Processing, bus loading, and response time requirements are defined in thissection. Following are the major assumptions for defining the requirementsfor the integrated power system control:

a) Maximum use of Digital Avionics Information System (DAIS) concepts(Reference 8)

- MIL-STD-1553B multiplexed data bus- RTs per specification SA 321301- DAIS executive with synchronous bus protocol- Use of Jovial higher order language fo r power system application

software

b) Separate AN/AYK-15A processor for power system cont.J].

c) Hardware connected to the 1553B bus.

- 5 ELMCs with 100 SSPCs each- 3 Power system RT s-2 GC1is

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rS FLT COT0 ~[NAY] LIGHIT [

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a. Processing RequirementsProcessing requirements for the power system were based on the B-1 EMUXspecification (Reference 9). Using the number of SSPCs as a complexitymeasure, the number and type of equations necessary for the power system in atactical fighter was determined by scaling the equation count for the B-1aircraft by the ratio of the SSPC requirement for the fighter to that requiredin the case of the B-1 EMUX.

The processing requirements can be separated into three categories ofequations as described below.Category I: These are power request equations and dre of the form Z=R where R

may taPe one of the fol'owing forms:Form 1 One variable of the Form '. or A, or the value "logic 1"

Form 2 Five variables arranged in any valid Booleanexpression with each variable used once only

Form 3 Twenty variables arranged in any valid dooleanexpression with each variable used once only

Form 4 Two hundred variables arranged as the sum of product3with each product term composed of no more than sixvariables with no variable repeated in the Booleanexpression.

There will be 208 form !, 236 form 2, 45 form 3, and 8 form 4 equations forthis aircraft.

Category II : There are 500 SSPC power control equations of the form:c = 1P (R + Q)

Where R is a Boolean expression of Form 1, 2, 3, or 4 listed above; P is asingle variable; L is the solution to the latch equation and Q is test request.

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Cateqory III: There are 500 power system status equations of the form:

I = (L + PX)

Where L is as defined in Category II above; P and X are single variablesavai1 %hle o the system designer for definition.

b. Input/Output Requirements

In the power system, the input/output consists of the data and traffictransmitted between the power system processor and its ELMCs and RTs in orderto accomplish the power system management and control functions. The I/Orequirements were determined by scaling the B-1 EMUX requiremen~ts by the ratiof the SSPC count. The discretes transmitted on the bus consist of sensor,SSPC status, system control and status, RT sync, and mode control informationThe requirements for this study were 2096 discrete inputs and 1041 discreteoutputs. It was assumed that the GC U interface with the power systemprocessor would require approximately 50 discretes for either input oroutput. All remaining discretes were uniformly distributed among the ELMCsand RTs. That is, each device '--nnected to the data bus with the exception othe GCUs, contributes equally to the total discrete input and outputrequirements.

c. Response Time

In order to compute the processor loading and data bus loadiotg, the responsetime of the system must be known. Response time refers to the maximum timerequired to detect a change in an event, process the information and then sena response on the data bus. A bimodal response time was used in this study.For the power system, approximtely 95 % of the discrete data must be receivedby the power system processor (PSP), processed, and the results must betransmitted within 300 ms. The remaining 5% of the equations and discretedata must be processed for a 50 ms response time. The 50 ms response timepertains to events which require power bus switching for power distributionreconfiguration.

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d. kvionics Bt- Loading

The avionics bus loading is necessary so the bus loading capacity for anintegrated power and avionics data bus architecture could be sized. In orderto determine realistic bus loading for the avionics system, the followingaircraft missions were studied: fighter, attack, reconnaissance, trainer,electronic warfare, and fighter bomber.In order to establish a representative avionics baseline bus loading, modelsubsystems with average complexity were selected. Data for the weaponsdelivery function (fire control computer, stores management, fire controlradar, an d laser set), inertial navigation system, and air data computer wereall taken from published data for the F-16. F-16 Control and Display data wasused since no fighter-bomber control an d display data was available. Thebaseline control and display subsystem therefore consists of a fire controland navigation panel, head-up-display (HUD), and radar display. Electroniccounter measures (ECM), imaging, an d communications data bus loading was basedon data developed at Boeing for a multi-role bomber. The ECM subsystemfunction is assumed to consist of flare and chaff dispersal. The imagingsubsystem baseline consists of a forward looking radar.

Perturbations from the baseline in the form of increased complexity for thecontrol an d display, inertial navigation system, ECM. and imaging subsystemsfor the reconnaissance, trainer, and electronic warfare missions wereexamined. Significant complexity increases in the inertial navigation systemand the imaging subsystem exist for the reconnaissance mission.Reconnaissance missions are assumed to require a very accurate irertialnavigation system and the imaging subsystem would contain side looking radar,infra-red mapping equipment, high resolution cameras, and TV cameras as wellas forward looking radar. The increase in data bus loading incurred by thesemore complicated subsystems is expected to be neutralized by the absence of aweapons delivery capability.In the case of the trainer a more complicated control and display subsystem isanticipated because of the requirement for dual controls an d displays, and anadditional monitor function for on e of the pilots. The increase in the bustraffic is estimated to be less than 20% for this subsystem.

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The electronics warfare mission represents perhaps the greatest potential foincreased data bus traffic from the baseline due to the large amount of dataneeded to identify threats and jamming as appropriate. Data from themulti-role bomber study indicates that EM C can add 8000 words/sec to bustraffic. Again this is offset by a lack of weapon delivery capability forthis mission. Using the F-16 data, the weapons delivery capability would ad8975 words/sec to the data bus, more than offsetting the EC M traffic.

Based on the above analysis, the number of words/sec shown in Table 3 wasselected as the baseline avionics data bus loading model. The percent busloading, based on approximately 40,000 data words/sec maximum bus loading fothe MIL-STD-1553B data bus, was 36%.

TABLE 3. BASELINE AVIONICS DATA BUS LOADING

SUBSYSTEM WORDS/SECControl and Display 661Weapons Delivery 8975Inertial Navigation 3350Air Data Computer 775Commuunications 128EC M 205Imaging Radar 128

14,222

3. TECHNICAL ANALYSIS

A technical analysis was performed on the three separate architecturesconsidered for electrical control. These three architectures are shown inFigure 9 and are described below:

a) Integrated: The electrical control system is on the same bus as theavionics.

b) Hierarchical: The electrical control system is on a separate bus bu-Iis connected to the avionic bus through an interbus processor.

c) Non-Integrated: The electrical control system is not connected to tavionic system by any multiplex data bus.

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1S53B BU S

AV IO!IC POWERPROCESSOR(S AVIONIC PROCESSOR POWERRT's RT's

A: INTEGRATED ARCHITECTURE

1553B BU S

AVIONIZ SPOWERPROCESSO{(S AVIONIC PROCESSOR' i'S~1553B PUS

POWERRT's

B: HIERARCHICAL ARCHITECTURE

1553B BU S

POWER ...... L IPROCESSOR POWER RT's

C: lION-INTEGRATED POWER BU SFigure 9. Data Bu s Architecture Configurations

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For each of these architectures the following analyses were performed:a) Processor loading: This is calculated as the total time required to

calculate the necessary set of logic equations in a minor cycledivided by the time in a minor cycle. The accepted limit forprocessor loading is 50%.

b) Bus Loading: This is calculated as the time required to transmit thnecessary se t of data, including overhead, in a minor cycle dividedthe time in a minor cycle. The accept, limit for bus loading is 5

c) Memory Requirements: The total memory requirements for the logicequations an d the executive is calculated.

d) Reliability: an arcnitectural reliability for comparison of theintegrated and hierarchical concepts is calculated.

e) Number of Processors Required: An estimate of the total number ofprocessors is qiven for each architecture.f) Smart RTs: The effect on processor loading an d bu s loading isanalyzed using distributed processing with smart PTs.

a. General AssumptionsThe analysis of the three data bu s architectures was made based on theassumptions listed below. The assumptions (a) through (j) apply to all of tthree architectures studied, whereas (k) through (n) apply only to theintegrated data bus architecture.

a) Response 4ime is defined to be the time required for a data changeone RT to ue received by the processor, processed, and transmitted tall other RTs that require the data.

b) Bus I/O and processing are bimodal to meet separate response times50 msec an d 300 msec. The messages that require a 50 msec responsetime are 5 percent of the total.

c) The system uses an MIL-STD-1553B multiplex data bus.d) All bus transmissions are terminal-to-controller or controller-to-

terminal. These are not terminal-to-terminal transmissions.e) All bus transmissions are synchronous.f) The system runs at 128 minor cycles per second. This provides 7.812

msec in each minor cycle.

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g) All remote terminals in the system receive the minor cyclesynchronization mode code each minor cycle.

h) All data words transmitted on the bus are packed 12 data bits per 16bit word. This will allow expansion of 4 bits per word.

i) For each arcnitecture, there is one power system processor. Thisprocessor is a MIL-STD-1750 machine with 128 K words (16 bits each) ofmemory.

j) For each architecture there are ten power RTs. This includes 5ELMCs. In the smart RT configurations, the 5 ELMCs have a Z8002microprocessor as the processing element.

k) The power system processor is a remote processor on the data bus. Thebus controiler is the avionics processor.

1) All power applications processing occurs in thE power systemprocessor. There is no power processing in the avionics processor(s).

m) Bus loading for the avionics I/O is 36%.n) The avionic bus controller processor sends a minor cycle

synchronization mode code to the power system processor and to each ofthe power RTs every minor cycle. The bus time required to do this isincluded in the avionics bu s load.

b. Processor Loading

Processor loading is defined as the amount of time within a minor cycle thatthe processor is buz,' executing application and executive code. The loadingof the power system processor, smart RT with Z8002 microprocessor, andexecutive loading are all discussed.

Processor loading was calculated for both dumb RT and smart RTconfigurations. In the dumb RT configuration the power system processorcalculates all equations. In the smart RT configuration the ELMC RT scalculate the category II and III equations and the processor calculates onlythe category I equations.Equation calculation is bimodal to meet response times of 50 msec and300 msec. In a dumb RT configuration, 5% of the calculations are spread over2 minor cycles to meet the 50 msec response time and 95% of the calculations

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are spead over 32 minor cycles to meet the 300 msec response time. In a smartRT configuration, 5%of the calculations are spread over 2 minor cycles and

of the calculations are spread over 16 minor cycles.

In the smart RT configuration, each of the 5 ELMC RTs has a Z8002 processingelement. Only the processing time for the 500 SSPC complement wa s calculatedfor the smart RTs. The Category II and III equations are divided equallybetween the 5 smart RTs. As with power processor loading, the calculation ofequations is bimodal to meet response times of 50 and 300 msec. Theprocessing load for each RT is 21% with 5% of the processing spread over 2minor cycles an d 95% of the processing spread over 16 minor cycles.

Because each of the three architectures requires a different executive, theprocessing time required by the executive is different for each architecture.

In the inteqrated architecturr;, the executive is responsible only for actionslocal to the power system processor. It is not responsible for bus contr'ol orsystem actions. In the hierarchical an d non-integrated architctures, thepower system processor has an executive that is responsible for both systemactions and local actions. In addition the hierarchical power processorexecutive has slightly more processing requirements as a result of being aremote or. the avionics bus. In relation to on e another, the hierarchicalexecutive requires the most overhead, the non-integrated executive is secondand the integrated executive requires the least.The actual percentage of processor loading during a minor cycle required bythe executive is dependent on the type of executive as stated above, and onhow the applications software is structured and the amount of executiveservices the application software requires. The more applications tasks thereare, the more overhead the executive requires. A general assumption is thatthe executive overhead for servicing applications tasks is about 20% of theapplications processor load.

c. Data Bus LoadingData bus loading is defined as the time required to transmit the requireddata, including overhead, divided by the total time available. The overhead

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included in the bus loading analysis is inter-message gap time and messageresponse time. Bus loading was calculated for dumb and smart RTconfigurations in each of the three architectures for the four different SSPCcomplemerts. The data bus I/O, like the processor loading, is bimodal to meetresponse times of 50 and 300 msec.

d. Memory ReqtuirementsEstimates of memory requirements were made for the power system processor andfor a smart RT. The elements that are competing for memory are listed a.follows:

o executable code for applications equationso other executable code for applicationo application datao executive codeo executive data

The memory requirements for equation calculations can be determined exactlybut 'nly estimates can be made for the others. The memory requirement for theequations was determined by coding representative equations in the J73/Ihigher order lanquage.

Other executable code for applications include such things as control logicfor the equations themselves and applications processing other thanequations. The memory required for this is totally dependent on the designand structure of the applications software and cannot be accurately deter.,inedhere.

Estimates can be made, however, for the memory requirements of the executiveand the executive data base. The power system processor in each architecturetype requires a different executive size and executive data base size.Estimates on the executive size are: 3000 words for the integrated powerprocessor, 7000 words for the hierarchical processor an d 5000 words for thenon-integrated power system processor. The executive data base is dependenton the type of executive and the structure of the application software. Alarge number of application tasks, events, etc. results in a larger executivedata base. A conservative estimate on the size of the executive data base foran average set of applications tasks is 5000 words.

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e. ReliabilityReliability comparisons for the three architectures are made using thegeneralized reliability model. Reliability computeC is not an overall systereliability. It is a computer architecture reliability and its main purposeis for comparison of the three architectural configurations.The following assumptions were used in the reli3bility analysis:a) 2.5 HR mission time for the tactical two engine airplane.h) Processor MTBF - 3000 HRS: This MTBF was obtained from the DAIS

AN/AYK-15A specification in Reference 10.c) GCU MTBF - 4000 HRS: obtained from Reference 6.d) ELMC MTBF - 1159 HRSe) RT MTBF - 2354 HRSf) Connector MTBF = 1.8 x 106 HRSAssumptions d-f are based on Harris Corporation hardware experience.The reliability for the respective architectures was calculated an d is shownbelow:

Non-integrated - 0.984Integrated - 0.976Hierarchical - 0.976

Due to the high reliability of the connectors and since an equal number ofelements is connected to the data bus for both the hierarchical and integratarchitectures, the reliablity is the same for these two configurations.

f. Results of the Technical AnalysisThe major conclusions of the technical analysis performed on the threearchitectures are:

a) Processor loading: Smart ELMCs and an integrated architecture arenecessary to meet the processing requirements for a two enginetactical aircraft.

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b) Bus loadina: All architectural concepts can meet the two enginetactical aircraft power system control requirements if smart ELMCs are

c) Memory: Smart ELMCs will require 17% more memory than the dumb ELMCconfigurations to meet the equation processing requirements.

d) Reliability: The hierarchical and integrated architectures haveidentical reliablity due to the high reliablity of connectors.

4. ECONOMIC AA1ALYSIS

Both softwgare and hardware costs of a two engine tactical aircraft electricalpower control system architecture were examined. Software costs are forapplication software development only. These costs are independent of thearchitecture chosen. Hardware costs are relative to the baseline non-integrated architecture. Only relative hardware costs were obtained sinceabsolute costs from the manufacturers could not be obtained fo r the hardwareat this early stage of development. The effects of SSPC count Andarchitectural differences were included in the analysis.

All architectural -onfigurations studied have identical numbers of ELMCs, RTs,and GCUs. The major differences between the three concepts are in theprocessor requirements.

The requirements for the power system processor for the non-integratedarchitecture approach can be met by the 'AIS AN/AYK-15A machine both in termsof hardware and software. The requirements for the power system processor forthe integrated architecture approach can also be met by the DAIS AN/AYK-15Aexcept that the executive software will not be as extensive since here theavionics processor will have most of this responsibility. Thus, the softwarerequirements for the integrated architecture processor are 20% lower than thatof the non-integrated architecture processor. This results in a costreduction for the integrated architecture system over the non-integratedarchitecture system.

For the hierarchical architecture additional hardware and software will berequired to provide the AN/AYK-15A processor with the capability to interfacewith two data buses and perform the interbus communications in addition to the

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power system processor functions. The interbus communication results in a 4increase in processor executive software requirements. This increases thecost of the hierarchical architecture processor hardware and software cver tnon-integrated architecture processor. Therefore, the hierarchicalarchitecture system will cost more than the non-integrated architecturesystem. From an economic standpoint the integrated data bus architectureconcept is considered most appropriate for a two engine tactical aircraft.

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SECTION III

CONCEPTUAL DESIGNS

1. BU S ARCHITECTURES

Three power control system data bus architectures were configured using DAISconcepts to the maximum extent possible. In order to examine the feasiblityof integrating the power system control function into the DAIS architecture,two conceptual designs were configured which have varying degrees ofintegration with the avionics data bus. In the first design, the integratedconcept, both avionics an d power system control is aonmplished using a commondata bus. In the second design, the hierarchical concept, a separate data busis used for the avionics and the power system control. The power systemprocessor is connected to both the avionics and power data buses an d performsthe additional function of interbus processing.

The third design is the dedicated or non-integrated power system controlconcept. In this arrangement the avionics an d power system control functionsare totally separate with a separate data bus for each. Such an architectureprobably could not be justified for a light tactical fighter. However, thisconcept was used as a baseline for comparing the two aoproaches described inthe previous paragraph and for determining power system control requirementsfor a light tactical aircraft.

a. Data Bus ArchitecturesAll the data bu s architectures presented in this section are based on the DAISconfiguration. The DAIS architecture consists of federated processorscommunicatinq with each other and the other system elements (sensors, weapons,and controls and displays) through a standardized multiplex data bus.Centralized system single-point control is performed by a processor residentsoftware executive that ca n be relocated for redundancy. Applicationssoftware is structured to provide modularity, reliability, an d transferability.This system archi.tecture is flexible to accommodate a wide variety of avionicsconfigurations, missions, and sensors, which provides redundancy to improveavailability, an d accommodate changes in technology.

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The basic architecture is designed for a broad class of configurations wherethe number of processors ca n be reduced or enlarged depending upon theavionics an d mission requirements. Standardization, modularity, andapplication independent executive software allows adaptability of thisarchitecture to a broad class of different applications as well as to makingmission-to-mission changes in a particular aircraft.

Sensors, weapons, an d other subsystems are selected as required for theparticular mission an d connected to the interface modules of the remoteterminals of the multiplex system or connected directly to the multiplex bus.b. Non-Integrated Data Bus ArchitectureThe baseline non-integrated data bus architecture is shown in Figure 10. Theconfiguration has 2 GCUs, 3 RTs, 5 ELMCs and one DAIS type processor. Powermanagement an d control software resides in this processor. In the case of asmart ELMC some of this software is moved to the ELMCs.The major advantages of this architecture as compared to the other twocandidates are:

a) Simple system integration and test - due to the separation of avionicand power control functions.

b) Easily expandable with minimum software impact - due to similaritywith DAIS concept an d existing software an d hardware modularity.

c) Minor changes to existing DAIS software - existing software for DAISis "off the shelf" and only an application software package needs tohe written.

The major disadvar -sof the non-integrated architecture are:

a) Redundant avionics RT interfaces - because both buses are physicallyseparate, avionics signals needed in power system management requireduplicate interfaces on each data bus.

b) Additional controls an d displays - since there is no data path betweethe avionics and power control systems, multi-function controls anddisplays already developed for the DAIS concept cannot be utilized.

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c) Higher bu s loading - because avionics signals from the avionics buscannot be used, these must be obtained by duplicate interfaces.

d) Additional weight - due to -edundant DAIS components like the controlsand displays an d bus interface hardware.

c. Integrated Data Bus ArchitectureThe integrated data bu s architecture combines the avionics an d power systemprocessors on a single data bus. This concept is shown in Figure 11. Theavionics processor acts as th? bus controller for the entire data bu s and isotherwise dedicated to avionics functions. The power system processor sharesthe same 1553B data bus and manages and controls its 5 ELMCs, 3 RTs, and 2GCUs. Controls an d displays are shared both by the power and avionicssystem. The major advantages of this concept are:

a) Minor changes to existing DAIS concept - in this configuration thepower system processor acts as an RT and all executive software is"off the shel"'. Only a power system application software packageneeds to be designed.

b) Le3st power and weight - when compared to the other two concepts, theintegrated approach minimizes the redundant use of DAIS software andhardware.

c)" Le.s memory requirements - due to the fact that the power systemprocessor is an RT on the avionics data bus, a full executive is notnecessary.

The major disadvantages of the integrated concept are:

a) Interaction of the power and avionics systems - changes to eithersystem can effect the other as the bus traffic has a fixed limit of 1megabits per second. Also response time requirements for both systemsmust be considered in designing data bus protocol an d message handlingb) Less expandability - a single DAIS type data bu s can be expanded toaccommodate up to 32 elements maximum.

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d. Hierarchical Data Bus ArchitectureThe hierarchical concept is shown in Figure 12. The key difference betweenthis arrangement an d the previous two concepts is that the power systemprocessor is connected between a separate avionics data bus an d power systemdata bus. The power system processor is a remote terminal on the avionics bubut a bus controller on the power system data bus. The number of RTs, ELMCs,an d GCUs needed in order to accommodate the power system cortrol requirementsis the same as in previously discussed architectures. The key advantages ofthis approach are:

a) Less bus loading - because avionics data can be obtained from aseparate bus, the traffic on the power data bus is reduced.

b) Greater expandability - the hierarchical data bus architecture offersalmost unlimited growth potential due to the ability to cascade anynumber of data buses each communicating with the next via an interbusprocessor.

c) Independence of avionics an d power system - software development canprogress more independently for the avionics and power system sincethe need to coordinate response time requirements is almost entirelyel irni nated.

The major disadvantages of this concept are:

a) Immature software/hardware: both the interbus processor an d itsexecutive software for interfacing to two data buses is still indevelopment.

b) Added weight - more bus interface circuitry an d power supplies arenecessary for multiple 1553B data buses than in an integrated approac

c) Higher executive overhead - a single power system processor configureto be both an RT on the avionics bus an d the bu s controller on thepowcr system data bus incurs enormous software overhead.

2. SELECTED CONCEPT

Based on the foreqoing, an integrated avionics an d power system architectureusing a single data bu s system is the selected concept to manage an d controlan electrical system for a light tactical two-engined fighter aircraft with

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multimission capability. The system consists of separate avionics and powesystem processors, 5 ELMCs, and 3 RTs (for the power system). The avionicsprocessor handles the system overhead an d perfor ;s the bus controllerfunctions.

The electrical sy,-,+em consists of two 60 KVA engine-driven generators, oneKVA auxiliary generator, three 100 A 28 VDC TRUs an d 500 SSPCs. Software fthis system uses the JOVIAL J73 higher order language.

The selection of the integrated architecture is based on the assumption thaavionics bus loading including overhead does not exceed 36% of total capaciof an MIL-STD-1553B deta bus. Also that the total number of avionics andpower system elements attached to the data bus does not exceed 32.

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SECTION IV

SYSTEM HARDWARE AND SOFTWARE DEVELOPMENT

A detailed design was performed on the Advanced Aircraft Electrical System.The resuls of the design are hardware and software specifications for thecomponents of the system. In addition, 3 system level specification wasprepared.

1. SYSTEM SPECIFICATION

The AAES configuration is shown in Figure 13. The unique feature of the AAESis the integrated data bus architecture of the control subsystem. As shown inFigure 14, elements of the AAES an d of the avionics system are integrated onthe same dual redundant data bus.The Advanced Aircraft Electrical System (AAES) is subdivided into threesubsystems, power generation, power distribution, and contrel. The powergeneration subsystem includes the primary and secondary power sources. Thisincludes two engine driven generators, an alixiliary power unit (APU)generator, and provisions for external power - plication. In addition DCpower is provided by three transformer rectifier units (TRU) and these arebacked up by a battery. The power distribution subsystem distributes powerfrom the main power buses, AC an d DC, to distributed load centers calledelectrical load management centers (ELMC). Within the ELMCs are solid statepower controllers (SSPC) which control power to the individual aircraftloads. The control subsystem consists of a dual redundant multiplex data bus(MIL-STD-1553B), 16-bit processors (MIL-STD-1750', controls and displays, andremote terminals (RT). The control subsystem incorporates DAIS hardware andsoftware. The control subsystem provides for automatic system operation ofthe AAES under normal and abnormal operating conditions.a. Power Generation SubsystemThe power generation subsystem is shown in Figure 15. Primary power shall beprovided from two engine driven variable speeJ constant frequency (VSCF)

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generators. These generators shall operate in the isolated mode only. Aninflight operable APU generator shall be provided for emergency operation andalso for ground power operation. An external power receptacle shali beDrovided for ground operation. None of the AC power sources shall beparalleled. The generator circuit breakers (GCB) are used to control power tothe main AC bu s from the VSCF qenerator. The GCB is under control of the VSCFqenerator control system. The bus tie breakers (BTB) allow the main AC busesto be paralleled during single generator operation, AP U generator operation,and external power operation. In addition to allowing cross powering of themain AC buses the BTBs provide overcurrent protection. The BT B is controlledby the circuit shown in Figure 16. The auxiliary power contactor (APC)controls application of power to the AC tie bus from the AP U generator. Theexternal power contactor (EPC) controls application of power to the AC tie"from the external power source. In addition, the EPC provides overcurrentprotection for the external power source. The control circuits for the AP Cand the EP C are shown in Figure 16.Three TRUs provide DC power to the AAES. Each TRU provides power to its ownisolated DC bus as shown in 1igure 15. TR U 1 and TRU 2 receive AC power fromAC Bus I an d AC Bus 2 respectively. TR U 3 receives power from either AC Bus 1and AC Bus 2 through the relay configuration shown in Figure 15. DC Bus 3 isparalleled through a diode to the Battery Bus. The Battery Bus is connectedto the Hot Battery Bus through a relay controlled by a cockpit mountedswitch. A battery is connected directly to the Hot Battery Bus. The batteryis charged by TR U 3.

b. Power Distribution Subsystem

The power distribution subsystem distributes power from the main AC and DCpower buses to distributed load centers called electrical load managementcenters (ELMC). Within the ELMCs are solid state power controllers (SSPC)which control power (and also provide overcurrent protection) to theindividual aircraft loads. The power flow is shown in Figure 17. Theelectromechanical power controller (EMPC) shall provide fault protection forthe feeder to the ELMC. The EMPC shall also control power to loads connecteddirectly to the main power buses. The subsystem shall have 7 ELMCs and 500SSPCs.

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Within the ELMC are a three phase AC bus, a DC bus, and a flight criticalbus. As shown in Figure 13, each bus is supplied from two sources of poweOne of the power sources for the fliqht critical DC bus is the battery busThis battery bus connection makes this bus an uninterruptible power bus fopowering flight control computers.

The feeders from the main AC and DC bu:s arc protected from overcurrent bEMPCs. The EMPCs also provide on/off control. The EMPCs are controlled bthe control subsystem through RTs. During system operation, these EMPCsremain closed.

c. Control Subsystem

The control subsystem is shown in Figure 18 . The control subsystem providfor automatic system operation of the AAES under normal and abnormal operaconditions. The electrical system control is integrated with the avionicssystem in that both systems share a common 1553B multiple data bus. The bcontrol function resides in the avionics system processor; however, controthe AAES resides in the power system processor. The control subsystemincorporates the DAIS architecture and the DAIS core elements which includDAIS processors, remote terminals, and data bus. In addition, the controlsubsystem shall include a controls and display unit, mass memory unit, andbus monitor,Dual redundant power system processors shall be used to control the AAES.power system Drocessors (PSP) shall use two discrete uni-directional contrlines to transfer control between the two PSPs.

In the control subsystem, centralized single point data bus control shallperformed by only one processor which is designated the master. In thiscontrol mode, the master which is the avionics processor, issues commandsother devices on the data bus, participates in data transfers on the bus irequired, checks status response from the addressed devices and interpretsanomalies for all bus traffic. Remote mode is the operational state assigto those processors which are not directed to be master, including the powsystem processor. Remote mode functions include monitoring of the multipldata bus for commands directed to that address, responding with an appropstatus word, and sending or receiving bus data.

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In the AAES laboratory simulator, the aiionics system processor (and buscontroller) shall be simulated.d. Real Time System SoftwareThe AAES simulator requires several major software modules. These modulesinclude operating system executives to control and synchronize operations inthe PSP and ELMCs. In addition, the PSP and ELMCs each contain applicationssoftware for performing their respective functions. Software modules are alrequired for the avionics simulator an d the bu s monitor, respectively.

e. Non-Real Time Support SoftwareSupport software modules are required for the AAES simulator. These non-reatime software modules are the Jovial J73 compiler, the Avionics Lab AssembleProgram (ALAP), and the partitioning Analyzing and Linkage Editing Facility(PALEFAC).

(1) Jovial J73 CompilerThe AAES software will for the most part be compiled with the J73 compiler.Furthermore, these sections of code which are not written in J73 must beconsistent with the linkages used by that compiler. The JOVIAL compiler is non-real time program which translates high-order-languaqe statements (J73source code) as specified in MIL-STD-1589A into software object modules(mission software and support software) which can be loaded and executed on.pecified target computers (e.g. DAIS processors, DEC-10 computer).

The system programmer will generate the J73 source input and compool inputfiles using the jOVIAL J73 User's Guide MA 224 200. The programmer will thecompile the source programs using the J73 compiler which shall produce sourclistings, cross references, object listings, and the relocatable object filefor the selected target computer.The output of the J73 compilation shall be relocatable module files. In ordto execute the program on the DEC-10, it shall be converted from relocatablefile to core image form using the DEC-10 (LINK-IO) linker loader. In order

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execute the program on the DAIS processor, it s'all also be converted to coreimage form using the DAIS Processor linker loader.

(2) ALAP Assembler

Machine dependent features of the 1tS software are translated by the ALAPassembler, described in DAIS Assembler User's Reference Manual, SA 206201.

(3) Partitioning Analyzing and Linkage Editing Facility (PALEFAC)

PALEFAC is a non-real time support software tool for use by the systemdesigner and application programmer to:

(a) Build the data tables for the DAIS loader and master executives.(b) Provide bus analysis and module partitioning information.(c) Produce the executive tables in J73 source code.(d) Generate linker command files for each DAIS processor for the

DEC-10 Linker or HB C Linker.

PALEFAC is used as a stand alone tool and consists of three basic programs asshown in Figure 19. PALEFAC pre-processor, PALEFAC main program, and PALEFACmodule input (PMI) decoder.

PALEFAC will oe used to build the mission software load modules for each ofthe DAIS processors. Inputs to PALEFAC are the application software modulesincluding the executive service requests generated by the applicationprogrammer in J73 source code. The pre-processor shall read each applicationmodule and create a record for each application module in the PMI file.

The system design will prepare PALEFAC Global Input (PGI) file based upon thespecific system configuration, partitioning of application tasks to eachprocessor, and bus messages to each terminal. This shall include:

(a) Bus Messageso To/from data block name or Terminal Address/Subaddresso Cycle (period and phase) for synchronous transmissionso Activity request identificaion for asynchronous transmissiono Word counto Class of retry

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(b) List of all tasks or modules for each processor

(c) Override directives

(d) Number of processors in the system configuration and address of eachterminalThe system designer will also generate the PALEFAC Auxiliary File (PAL) forcommon subroutines (comsubs) ane common communication data blocks (compools).The PALEFAC main program shall build the executive tables an d linker commandfiles based upon the system designer specified configuration. The output ofPALEFAC shall be the PALEFAC mission files (PMD), PALEFAC PartitioningInformation Files (PPI), an d text output files shown in Figure 19. The PMDfiles shall contain all the executive tables including the bus control tablesin J73 source code. The PPI files shall contain the linker commands for eachprocessor an d specify all the mission software modules (e.g. executivemodules, application tasks, comsubs, an d executive tables) in oroer for thelinker to produce the load modules for each processor.PALEFAC shall also produce text output files listing all the PALEFAC inputfiles, the output files, and error messages.

2. HARDWARE SPECIFICATIONSThe electrical control system consists of a distributed netwurk of processors,controllers, and terminals that monitor the elect'ical power system an d exertcontrol functions over it. The various elements of the electrical controlsystem communicate with each other via messages transferred on a standar1 DAIS1553B multiplax data bus. Control an d synchronization of the data bus i3performed by the avionics processor. All electrical control system elementsperform as remote terminals in relation to the avionics processor. Thoseelements that make up the electrical control system are the PSP, 71 RTs, 5DAIS RTs, 2 GCUs, avionics controls an d displays, an d a DAIS mass memory unit.

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a. Pow, r System Processor

The PSP provides overall control of the electrical control system. Electricalsystem status information is provided to the PSP by other elements in theelectrical control system. Avionics controls provide updated control andflight mod' information whenever this information changes. The PSP uses thisi