Advn Mp Module1

8/10/2019 Advn Mp Module1

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Lecture #1

1. Synopsis

Interfacing Definition

Transmission modes

Architecture of 8255

2. Target

By this lecture you should be able to answer the following questions

1 !ow many "orts are on 8255#

2 $%"lain the control word format of 8255 in B&' mode( Describe different modes of 8255

3. Introduction

The "rimary function of micro"rocessor is to acce"t data from in"ut such as )eyboard

* A+D con,erters- read instructions from memory- "rocess data according to the instructions-

and send the result to out"ut de,ices such as .$D/s- "rinters and ,ideo monitors

4. Concepts

Definition

Designing logic circuits and writing instructions to enable the micro"rocessor tocommunicate with these "eri"herals is called interfacing

0icro"rocessor communicates to "eri"herals in either of two formats synchronous and

asynchronous &imilarly- transfers data in either of two modes memory ma""ed I+ or

"eri"heral I+- on the basis of interfacing logic circuitsTransmission format

&ynchronous

Asynchronous

0odes of Data transfer 3arallel here- the entire word is transferred at one time 4eyboards- .$D/s- data

con,erters and memory are generally use the "arallel data transfer mode

&erial Data is transferred one bit at a time o,er a single line between

micro"rocessor and "eri"heral 3rinters- 'T terminals and modem fortele"hone line use "arallel mode of data transfer

Ty"es of I+

3eri"heral

0emory ma""ed

Programmabe perip!era De"ice

A 3rogrammable de,ice is designed to "erform ,arious in"ut+out"ut functions The

de,ice can be set u" to "erform s"ecific functions by writing an instruction to the controlregister And the functions can be changed at any time during e%ecution of the "rogram by

writing a new instruction into the control register

rganiation and arc!itecture of $2%%

8255A is a general "ur"ose- "rogrammable- "arallel I+ de,ice It has 26 I+"ins that can be grou"ed "rimarily in two 87bit "arallel "orts A and B- with the remaining

eight bits as "ort The eight bits of "ort can be used as indi,idual bits or can be

grou"ed in two 67bit "orts u""er * lower The functions of these "orts are defined bywriting a control word in the control register


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8255A I+ "orts

3ort A

u

l

3ort B

The functions of 8255A can be classified according to two modes bit &et or 'esetmode B&'9 and the I+ mode The B&' mode is used to set or reset the bits in "ort The

functions of each "ort are defined in I+ mode The I+ mode can be further di,ided into

three modes 0ode:- 0ode 1 * 0ode 2

&perationa 'odes

'&D( );hen a "ort is used for sim"le in"ut or out"ut o"eration without handsha)ing- then it

is initiali

'&D( 2

nly "ort A can be initiali


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A1 A: &$.$TI@

: : 3'T A

: 1 3'T B

1 : 3'T

1 1 @T'.

Contro ,ord

The content of control register is control word- which s"ecifies I+ function for each

"ort The register can be accessed to write a control word when A: and A1 are at logic 1

The register is not accessible for read o"eration

Contro ,ord format of $2%%

8255 can o"erate in two modes In"ut+ut"ut mode and Bit set+'eset 0ode To ma)e

the o"eration "ossible in either of these modes- we write control words to control

register If bit > of the control word is a logical 1 then the 8255 will be configured inI+ mode

If bit > of the control word is a logical : then each bit of the "ort can be set or reset


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-C*IT(CT/(

Data 0us 0ufferThis three7state bi7directional 87bit buffer is used to interface the 8255 to the system data bus

Data is transmitted or recei,ed by the buffer u"on e%ecution of in"ut or out"ut instructions by

the 3 ontrol words and status information are also transferred through the data bus buffer

ead,rite and Contro Logic

The function of this bloc) is to manage all of the internal and e%ternal transfers of both Data

and ontrol or &tatus words It acce"ts in"uts from the 3 Address and ontrol busses and inturn- issues commands to both of the ontrol rou"s


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CS C!ip Seect A ClowC on this in"ut "in enables the communication between the 8255 andthe 3

D 'ead A ClowC on this in"ut "in enables 8255 to send the data or status information to the

3 on the data bus In essence- it allows the 3 to Cread fromC the 8255

, ;rite A ClowC on this in"ut "in enables the 3 to write data or control words into the

8255

-) and -1 3ort &elect : and 3ort &elect 1 These in"ut signals- in conunction with the 'Dand ;' in"uts- control the selection of one of the three "orts or the control word register They

are normally connected to the least significant bits of the address bus A: and A19

(S(T 'eset A ChighC on this in"ut initialiE

2 !ow a )ey debounce can be chec)ed# $%"lain


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3. Introduction

82>E is a hardware a""roach to interfacing a matri% )eyboard and a multi"le%ed

dis"lay that scans and encodes u"to a =67)ey )eyboard and controls u"to a 1=7digit numerical

dis"lay It is a 6:7"in de,ice with two maor segments )eyboard and dis"lay The )eyboardsegment can be connected to a =6 contact )ey matri% The )eyboard entries are debounced and

stored in the internal GIG memoryH and an interru"t signal is generated with each entry The

dis"lay segment can "ro,ide a 1=7character scanned dis"lay interfaces with de,ices li)e .$D/sThis segment has 1=8 '+; memory- which can be used to read or write information for

dis"lay "ur"oses

4. Concepts

Pinout Definition of $278

A: &elects data :9 or control+status 19 for reads and writes between micro and 82>E

BD ut"ut that blan)s the dis"lays

.4 sed internally for timing 0a% is ( 0!7DB: onsists of bidirectional "ins that connect to data bus on micro

I'J Interru"t request- becomes 1 when a )ey is "ressed- data is a,ailable

T A(7A:+B(7B: ut"uts that sends data to the most significant+least significant

nibble of dis"lay

'D;'9 onnects to microKs I' or 'D signal- reads data+status registers

'$&$T onnects to system '$&$T

'.>7'.: 'eturn lines are in"uts used to sense )ey de"ression in the )eyboard matri%

&hift &hift connects to &hift )ey on )eyboard

&.(7&.: &can line out"uts scan both the )eyboard and dis"lays

Programmabe 9eyboardDispay Interface : $278

A "rogrammable )eyboard and dis"lay interfacing chi"o&cans and encodes u" to a =67)ey )eyboard

oontrols u" to a 1=7digit numerical dis"lay

4eyboard has a built7in GIG 8 character buffer

The dis"lay is controlled from an internal 1=%8 'A0 that stores the coded

dis"lay information

4eyboards consist of a large matri% of )eys- all of which are monitored by an on7board

"rocessor called the C)eyboard encoderC The s"ecific "rocessor ,aries from )eyboard7to7)eyboard but they all basically do the same thing 0onitor which )eys9 are being

"ressed+released and send the a""ro"riate data to the host This "rocessor ta)es care of all the

debouncing and buffers any data in its 1=7byte buffer- if needed

0otherboard contains a C)eyboard controllerC that is in charge of decoding all of the datarecei,ed from the )eyboard and informs software of whatKs going on


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;unctiona boc+ diagram of $278

DB0-DB7

CL9 (S(T IE

generates an interru"t signal when there is an entry on GIG

Dis"lay section has eight out"ut lines di,ided into two grou"s A:7A( and B:7B( The out"ut lines are connected to the anodes through dri,er transistor in case of

common cathode > segment .$D The dis"lay can be blan)ed by BD line The dis"lay

section consists of 1=L 8 dis"lay 'A0 which can also be organi for data transfer

;hen a )ey is "ressed it bounces for a short time If a )ey code is generatedimmediately after sensing a )ey actuation- then the "rocessor will generate the same

)eycode a number of times A )ey ty"ically bounces for 1: to 2: ms !ence the

"rocessor has to wait for the )ey bounces to settle before reading the )eycode

Interfacing a matri= +eyboard >it! $)$%

A matri% )eyboard is where there are more than eight )eys A )eyboard with 1= )eyscan be arranged in a 6 % 6 matri% It requires eight lines from the micro"rocessor to

ma)e all the connections ;hen a )ey is "ressed- it shorts one row and column The

interfacing of a matri% )eyboard requires two "orts one out"ut "ort and one in"ut "ort'ows are connected to the out"ut "ort and the columns are connected to the in"ut "ort

round all the rows by sending logic : through the out"ut "ort

hec) the columns by reading the in"ut "ort If no )ey is "ressed- all columns

remain high ontinue the abo,e two ste"s until the reading indicates a change

;hen one of the )eys is "ressed- the corres"onding column goes lowH identify

and encode the )ey

The columns and rows ma)e contact only when a )ey is "ressed therwise it remains

high ;hen the )ey is "ressed- the intersection of row and column must change fromhigh to low The column lines of the )eyboard are connected to the return lines- '.:7

'.> of 82>E As a low is "ut on each row- the 82>E chec)s these return lines one at a

time to see any of them is low If it finds any of return lines low- indicating a )ey"ress-it waits a debounce time of about 1:( ms and chec)s again If )ey"ress is still "resent-

the 82>E "roduces an 87bit code to re"resent the "ressed )ey After sending the "ac)et


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information of "ressed )ey- it stores the byte in an internal GIG 'A0 IT also assertsthe I'J "in high and increment the GIG count in the internal status register

Scan Codes

The )eyboardKs "rocessor s"ends most of its time CscanningC- or monitoring- the matri% of

)eys If it finds that any )ey is being "ressed- released- or held down- the )eyboard will send a

"ac)et of information )nown as a Cscan codeC to the com"uterThere are two different ty"es of scan codes Cma)e codesC

and Cbrea) codesC A ma)e

code is sent when a )ey is "ressed or held down A brea) code is sent when a )ey is released

$,ery )ey is assigned its own unique ma)e code and brea) code so the host can determinee%actly what ha""ened to which )ey by loo)ing at a single scan code The ma)e code only

re"resents a )ey on a )eyboard77it does not re"resent the character "rinted on that )ey This

means that there is no defined relationshi" between a ma)e code and an A&II code ItKs u" to

the host to translate scan codes to characters or commands

Interfacing +eyboard and a se"en segment L(D to $)$%

A "ushbutton )eyboard is connected to "ort A and a se,en segment .ed is connected to "ort B

of 8255 3ort A should be configured as an in"ut "ort and "ort B as an out"ut "ort

Analyse the address decoding circuits and find the address of "ort A- "ort B and control

register

;rite the a""o"riate control word to the control register to configure the "orts as

required

hec) if a )ey is "ressed7 write the software "rogram to do it

Debounce the )ey7 hardware soln7 use of cross cou"led @A@D gate and software soln

is to write a delay loo"

Identify the )ey "ressed7 write the A.3 to store the identified )ey in the accumulator

$ncode the )ey con,erts the binary hardware reading of the )ey :"ressed intoa""ro"riate binary format according to the number of the )ey

btain the se,en segment .$D code using table loo)7u" technique and dis"lay it

FFFFFFFFFFFFFFFFFFFF


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-sync!ronous Seria Transmission

Asynchronous transmission allows data to be transmitted without the sender ha,ing to

send a cloc) signal to the recei,er Instead- the sender and recei,er must agree on timing"arameters in ad,ance and s"ecial bits are added to each word which are used to synchroni


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0oc+ Diagram

0oc+ diagram of t!e $2%1 /S-T /ni"ersa Sync!ronous -sync!ronous ecei"er

Transmitter

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Lecture # 4

1. Synopsis

8251A com"onents and wor)ing

Interfacing of 8251A

2. Target

By this lecture you should be able to answer the following questions1 !ow the data is con,erted during transmission#

2 !ow the functions are defined to control the o"eration of &A'T#

3. Introduction

8251A is a "rogrammable "eri"heral designed for synchronous +asynchronous serial datacommunication- "ac)aged in a 287"in DI3 It includes fi,e sections

19 'ead+;rite ontrol .ogic29 0odem ontrol

(9 Data Bus buffer

69 Transmitter

59 'ecei,er

4. Concepts

'ead+;rite ontrol logic

This section includes a control logic- si% in"ut signals- and three buffer registers Dataregister- control register and status register The control logic interfaces the chi" with 03-

determines the functions of the chi" according to the control word in the control register and

monitors the data flow

In"ut signals

& hi" &elect ;hen this signal goes low- the 8251A is selected by the 03 forcommunication

+D ontrol+Data ;hen this signal is high- the control or status register is addressedH

when it is low- data buffer is addressed The control register and status register aredifferentiated by ;' and 'D signals

;' ;hen this signal is low- the 03 either writes in the control register or sends

out"ut to the data buffer


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'D ;hen this signal goes low- the 03 either reads a status from the status register or

acce"ts data from data buffer

'$&$T A high on this signal reset 8252A and forces it into the idle mode

.4 This is the cloc) in"ut- usually connected to the system cloc) for communication

with the micro"rocessor

ontrol 'egisterThe 1=7bit register for a control word consist of two inde"endent bytes the first byte

is called mode word and the second byte is called the command word The mode word

s"ecifies the general characteristics of o"eration such as baud- "arity- number of bits etc But

the command word enables the data transmission and rece"tion The register can be accessedas an out"ut "ort when the ontrol+Data "in is high

&tatus register

This in"ut register chec)s the ready status of the "eri"heral The status word in thestatus register "ro,ides the information concerning register status and transmission errors

Data buffer

This bidirectional register can be used as an in"ut and out"ut "ort when the +D is low

& +D

;' 'D "eration

:

:

:

:

1

:

:

1

1

M

1

:

:

1

M

:

1

1

:

M

03 reads data from data buffer

03 writes data from data buffer

03 writes a word to control register

03 reads a word from status register

hi" is not selected for any o"eration

Transmitter section

The transmitter acce"ts "arallel data from 03 and con,erts them into serial data It has tworegisters

buffer register to hold eight bits

out"ut register to con,ert eight bits into a stream of serial bits

Transmit control

ut"ut 'egister

Transmitter Buffer


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The 03 writes a byte in the buffer register- whene,er the out"ut register is em"tyH

the contents of buffer register are transferred to out"ut register And transmit the data on the

T%D "in with a""ro"riate framing bits Three out"ut and one in"ut signals are associatedwith this transmitter section

T%D This is an out"ut signal to transmit the data to "eri"herals

T% An in "ut signal controls the rate of transmission

T%'DN An out"ut signal- indicate the buffer register is em"ty and the &A'T is ready to

acce"t the ne%t data byte

T%$ An out"ut signal to indicate the out"ut register is em"ty and the &A'T is ready to

acce"t the ne%t data byte

ecei"er Section

'ecei,er section acce"ts serial data on the '%D "in and con,erts them to "arallel data

This section has two registers

the recei,er in"ut register

The buffer register

'%D

'%'DN

'%

;hen the '%D goes low- the control logic assumes it is a start bit- waits for half bit time- and

sam"les the line again If the line is still low- the in"ut register acce"ts the following data- and

loads it into buffer register at the rate determined by the recei,er cloc)

'%'DN7 recei,er 'eady This is an out"ut signal It goes high when the &A'T has acharacter in the buffer register and is ready to transfer it to the 03

'ecei,e Buffer

'ecei,e control

In"ut 'egister

Transmitter Buffer


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'%D7 'ecei,e data Bits are recei,ed serially on this line and con,erted into a "arallel byte inthe recei,er in"ut register

'%7 'ecei,er cloc) This is cloc) signal that controls the rate at which bits are recei,ed by

the &A'T

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Advn Mp Module1