Scheme of Examination for M.Tech.(Regular & weekend) P rogramme has been approved by BoS of USICT on dated

28/05/2012 and AC subcommittee on dated 6th July, 2012 and 5th November,2012. This scheme is effective from academicsession 2012-13.

Basic principle of MOS transistor, Introduction to large signal MOS models (long channel) for

digital design.

scaling, MOS SPICE model and simulation, CMOS

layout: design rules, Transistor layout, Inverter layout, NMOS and CMOS basic manufacturing steps.

Inverter principle, the basic CMOS inverter, transfer characteristics, logic threshold, Noise

margins, switching characteristics, Propagation Delay, Power Consumption.

Static latches, Flip flops & Registers, Dynamic Latches & Registers, CMOS Schmitt trigger, Astable Circuits.

Memory Design: ROM & RAM cells design Dynamic logic families and

performances.

Clock Distribution. Input and Output Interface circuits.

Design styles, design concepts: Hierarchy, Regularity, Modularity, Locality. CMOS Sub system design:Adders , Multipliers.

[1] S.Kang & Y. Leblebici CMOS Digital IC Circuit Analysis & Design-McGraw Hill, 2003.

[2] J. Rabaey, Digital Integrated Circuits Design, Pearson Education, Second Edition, 2003.

[1] Neil Weste and David Harris : CMOS VLSI design Pearson Education 2009.

Page 120

Static MOS des ign,Ratioed logic, Pass Transistor logic, complex logic

circuits.

Paper Code: MEEC-606 L T C

Paper: Advanced VLSI Design 4 - 4

INSTRUCTIONS TO PAPER SETTERS: MaximumMarks : 60

1. Question No. 1 should be compulsory and cover the entire syllabus. This question should have

objective or short answer type questions. It should be of 20 marks.

2. Apart from Question No. 1, rest of the paper shall consist of four units as per the syllabus. Every

unit should have two questions. However, student may be asked to attempt only 1 question from

each unit. Each question should be 10 marks

Unit 1

Introduction :

MOS Circuit Layout & Simulation and manufacturing:

Unit 2

The MOS Inverte r :

Unit 3

Dynamic MOS design :

Clock Distribution

Unit 4

Subsystem design

Refe rence Books

Combinational MOS Logic Design :

SequentialMOS Logic Design

Text Books