Advanced Verifivstion Topics Index

7/27/2019 Advanced Verifivstion Topics Index

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Advanced Ver i f icat ion Topics

Bishnupriya BhattacharyaJohn DeckerGary HallNick HeatonYaron KashaiNeyaz KhanZeev KirshenbaumEfrat Shneydor


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Contents

2.6 Collecting Coverage 262.6.1 Direct and Computed Coverage Collection 272.6.2 Deciding on Coverage Ranges 302.6.3 Trading Off Speed and Visibility 30

2.7 Generat ing Inputs 322.7.1 Dealing with Configurat ions and Settings 322.7.2 Generating and Driving Digital Cont rol 33

2.8 Checking Analog Functionality 382.8.1 Comparing Two Values 382.8.2 Triggering a Check on Cont rol Changes 402.8.3 Measuring Signal Timing 432.8.4 Compar ing a Value to a Threshold 452.8.5 Checking Frequency Response 47

2.9 Using Assert ions 492.9.1 Checking Inpu t Condi tions 492.9.2 Verifying Local Invariants 502.9.3 Limitations on Assertion Checking of Analog Properties 502.9.4 Dealing with Different Modeling Styles 50

2.10 Clocks, Resets and Power Controls 512.10.1 Driving Clocks 512.10.2 Resets 512.10.3 Power-Up and Power-Down Sequences 512.11 Analog Model Creation and Validation 53

2.12 Integrating the Test Environment 542.12.1 Connect ing the Testbench 542.12.2 Connecting to Electrical Nodes 552.12.3 System-Level Parameters and Timing 562.12.4 Supporting Several Model Styles In A Single Testbench 572.12.5 Interfacing Between Real and Electrical Signals 592.12.6 Creat ing Run Scripts and Other Support Files 612.12.7 Recommended Directory Structure 622.13 Closing the Loop Between Regressions and Plan 632.13.1 Implementat ion of Coverage for Analog 632.13.2 Updat ing the Verification Plan With Implementat ion Data 64

2.14 Regression Runs for Analog IP 652.14.1 Single Simulation Runs 652.14.2 RegressionsRunning Multiple Test Cases 67

2.15 Moving Up to the SoC Level 692.15.1 Mix-and-Match SoC-Level Simulation 692.15.2 Updating the SoC-Level Test Plan 70

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2.15.3 Integrating Into the SoC-Level Testbench 702.16 UVM-MS Universal Verification Blocks 72

2.16.1 Wire Verification Component 722.16.2 Simple register UVC 782.16.3 Analog to Digital Converter (ADC) UVC 822.16.4 Digital to Analog Converter (DAC) UVC 842.16.5 Level Crossing Monitor 862.16.6 Ramp Generator and Monitor 89

2.17 Summary 943 Low-Power Verification wi th the UVM 97

3.1 Introduction 973.1.1 What is Unique about Low-Power Verification 983.1.2 Understanding the Scope of Low-Power Verification 993.1.3 Low-Power Verification Methodology 1003.1.4 Understanding Low-Power Verification 102

3.2 Understanding Low-Power Design and Verification Challenges 1023.2.1 How Low-Power Implementations Are Designed Today 1023.2.2 Challenges for Low-Power Verification 1033.2.3 Low-Power Optimization 1043.2.4 Low-Power Architectures 1053.2.5 Low-Power Resources I l l3.3 Low-Power Verification Methodology I l l

3.4 Low-Power Discovery and Verification Planning 1133.4.1 Low-Power Discovery 1133.4.2 Verification Planning 1133.4.3 System-Level Planning 1133.4.4 Hierarchical Planning 1173.4.5 Domain-Level Verification Planning 1183.4.6 A Note on Verifying Low-Power Structures 1193.4.7 Recommendations for Designs with a Large Number of Power Modes 1193.5 Creating a Power-Aware UVM Environment 1213.5.1 Tasks for a Low-Power Verification Environment 1213.5.2 Solution: Low-Power UVC 1223.5.3 UVC Monitor 1243.5.4 LP Sequence Driver 1263.5.5 UVM-Based Power-Aware Verification 128

3.6 Executing the Low-Power Verification Environment 1283.6.1 LP Design and Equivalency Checking 1283.6.2 Low-Power Structural and Functional Checks 129

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3.6.3 Req uirements for Selecting a Simulator and Em ulator 1303.6.4 Advanced Debug and Visualizations 1323.6.5 Au tom ated Assertions and Coverage 1353.6.6 Legal Power Modes and Transitions 1353.6.7 Au toma tic Checking of Power Con trol Sequences 1353.6.8 Verification Plan Gen erated from Power Inten t 136

3.7 Co mm on Low-Power Issues 1383.7.1 Pow er-Co ntrol Issues 1383.7.2 Do ma in Interfaces 1393.7.3 System-Level Co ntro l 140

3.8 Sum mary 1414 Mu l t i- L an g u ag e UV M 143

4.1 Overview of UVM Multi-Language 1434.2 UV C Requ iremen ts 146

4.2.1 Providing an Ap prop riate Configuration 1464.2.2 Exp orting Collected Inform ation to Highe r Levels 1464.2.3 Providin g Support for Driving Sequences from Oth er Languages 1464.2.4 Providin g the Fou ndatio n for Debugg ing of All Components 1464.2.5 Op tional Interfaces and Capabilities 147

4.3 Fundam entals of Conne cting e and SystemVerilog 1474.3.1 Type Conversion 1474.3.2 Func tion Calls Across Languages 1504.3.3 Passing Events Across Languages 153

4.4 Configuring Messaging 1544.5 e Over Class-Based SystemV erilog 154

4.5.1 Environm ent Architecture 1554.5.2 Configura tion 1564.5.3 Generating and Injecting Stimuli 1604.5.4 M onito ring and Checking 168

4.6 SystemVerilog Class-Based over e 1714.6.1 Simulation Flow in Mixed e and SystemVerilog Env ironm ents 1734.6.2 Co ntacting Caden ce for Fur ther Inform ation 173

4.7 UVM SystemC Method ology in Multi-Language Env ironm ents 1744.7.1 Introdu ction to UVM SystemC 1744.7.2 Using the Library Features for Mode ling and Verification 1754.7.3 Co nnec ting between Languages using TLM Por ts 1824.7.4 Exam ple of SC Reference Model used in SV Verification Env ironm ent 1884.7.5 Reusing SystemC Verification Co mp one nts 191

4.8 Sum mary 193

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Advanced Verifivstion Topics Index