MIT Lincoln LaboratoryNU Status-1JAB 04/19/23

Advanced Photodiode Development

7 April, 2000James A. Burnsjab@ ll.mit.edu

MIT Lincoln LaboratoryNU Status-2JAB 04/19/23

3D Photodiode DevelopmentSnapshot

• Goal– Produce high quality photodiodes for visible imaging

Standard CMOS processes do not produce image-quality photodiodes Photodiode process must be compatible with 3D integration

• Approach– Review existing Lincoln silicon-photodiode processes– Optimize an existing process to meet the active pixel sensor requirements

using Process and device simulation Additional characterization of existing photodiodes

• Tasks– Define photodiode requirements– Define photodiode fabrication process– Layout a photodiode test chip– Fabricate and characterize photodiodes

3 runs to optimize device properties 3D integration and photodiode characterization

MIT Lincoln LaboratoryNU Status-3JAB 04/19/23

Lincoln Silicon Photodiode Survey

• A comparison of photodiodes and the principal processes which affect dark current

Processes Avalanche photodiode PIN active pixel CCD/CMOS

Gettering Backside Backside P- epi/P+ substrateIsolation LOCOS Etched field oxide LOCOSOxidation Non-slip process Non-slip process Standard with CZ wafers

Sequential anneal Yes No NoEtch Wet Wet Plasma

Metal deposition Evaporated Evaporated Sputtered

Dark Current (pA/cm2) 15 100 300

MIT Lincoln LaboratoryNU Status-4JAB 04/19/23

Photodiode Process1st Pass

• Bulk substrate– 25-m epi, 300 -cm– 0.01 -cm p-type wafer

• Process highlights– LOCOS isolation

30-nm stress-relief oxide

20-nm Si3N4

– 250-nm field oxide– Dual N+ implant

Phosphorus to obtain a deep junction

Arsenic to maintain high C0

– Extended anneal to repair N+ implant damage

• Eight Mask Levels– Six through metal-1, passivation– Deep via and back metal for 3D integration tests

MIT Lincoln LaboratoryNU Status-5JAB 04/19/23

Photodiode Simulations

Profile following field oxidation LOCOS bird’s beak limits fill factor

Completed simulation indicates a 1-m junction depth

0.5 m

P-type epi

Xj

Field Oxide

MIT Lincoln LaboratoryNU Status-6JAB 04/19/23

Photodiode Test Chip Characterization

• Front side measurements– Diode leakage vs diode area, perimeter– Cross talk vs diode, isolation spacing– Diode responsivity(), dark current, linearity()– Array uniformity and yield

• Back side measurements– Determine if bond process degrades photodiode– Measure photodiode properties vs silicon thickness

• 3D imager– Measure photodiode properties vs deep via resistance– Determine whether 3D assembly degrades photodiode– Deep via and back metal layers included in reticle set

MIT Lincoln LaboratoryNU Status-7JAB 04/19/23

Imager Test DevicesDiode Array

• Array measurements– Leakage and cross talk vs diode area and N+N+, N+P+ spacing– Responsivity, linearity, and yield

P+ Contacts

N+P Diodes

L W

gG

w

Metal-1

4 individual diodes2 diodes in parallel10 diodes in parallel

Diode Array Features Dimensions(um) per DeviceFeature Dimension 1 2 3 4 5 6 7 8L,W N+ active layer length,width 10 20 40 80 160 10 10 10G N+ active layer seperation 2 0.5 1 2g N+ active-P+ contact seperation 2 1

MIT Lincoln LaboratoryNU Status-8JAB 04/19/23

Imager test DevicesEdge Effects Diode

• Measure leakage vs diode area, perimeter to isolate edge effects

– LOCOS-induced stress, inadequate channel stop– Misaligned contacts

N+P Diodes-5 in parallel

N+P Outer Diodes-2 in parallelP+ Contact

Dimensions(um) per DevicePerimeter(linear) Diode Features 1 2 3L N+ active layer length 500 W N+ active layer width 2G N+ active layer seperation 2w P+ contact layer width 2g N+ active-P+ contact seperation 2Nd Number of N+ bars per array 4 8 16

MIT Lincoln LaboratoryNU Status-9JAB 04/19/23

Imager Test DevicesIndividual Diodes

• Measure leakage vs isolation features

N+-N+ Gap

N+P Diode

P+ Contact

Sizes Gaps Pad FunctionsN+ Inner N+ Ring N-N N-P 1 280x80 80x80 4 2 P+ Guard N+ Diode+Ring80x80 80x80 2 2 P+ Guard N+ Diode+Ring80x80 80x80 1 2 P+ Guard N+ Diode+Ring80x80 80x80 0.5 2 P+ Guard N+ Diode+Ring

MIT Lincoln LaboratoryNU Status-10JAB 04/19/23

Imager test DevicesParasitic FET

• Characterize leakage mechanisms– separate surface from bulk leakage with metal gate– determine minimum N+ separation

Dimensions(um) per DeviceField Leakage Features 1 2 3 4L N+P diode length 20W N+P diode width 4G N+-N+ gap 4 2 1 0.5g N+-P+ gap 2o metal-N+P diode overlap 0.5w P+ contact width 2

L g

Metal-1 Gate

N+P Diode

W P+ Contact

G

o

MIT Lincoln LaboratoryNU Status-11JAB 04/19/23

Backside Illuminated Characterization

• Photodiode wafer bonded to support wafer– Silicon thinned– Silicon etched to expose metal-1 pads

Standard CCD process for backside imaging

Photodiode wafer

Support wafer

+

Silicon

Oxide

Metal-1

Bond layerN+ Silicon

Support wafer

Completed backside imager

Support wafer

MIT Lincoln LaboratoryNU Status-12JAB 04/19/23

3D Assembly Characterization

• Photodiode wafer bonded to oxidized silicon wafer– Silicon removed from transfer wafer– Deep vias etched and connections made to metal-1 of photodiode wafer

• Assembly bonded to support wafer– Silicon thinned – Silicon etched to expose metal-1 pads

Photodiode wafer

Transfer wafer

+

Photodiode wafer

Completed backside imager

Support wafer

MIT Lincoln LaboratoryNU Status-13JAB 04/19/23

Photodiode Development Status

• Silicon photodiode process survey complete

• Initial process defined; optimization via simulation underway

• Test devices defined; layout nearly complete