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ADVANCED DIGITAL DESIGNDESIGN EXERCISE I
Metastability Measurement and Analysis
What you get from us
• A working late transition detector• Implementation of [PS13 and PS15]• But without the case separation• Only one FIFO is present
• Python based PC software• Automates the measurement• Prints a CSV trace to standard out
Environment
• Altera Cyclone-IV FPGA• Design software: Quartus• Includes all necessary design tools
• PC software• Python program for collection of CSV traces• Analysis with program of choice (Excel, Python, MATLAB, ...)
Your Task (LTD Measurement)
• Implement the case separation from [PS13, PS15]• Measure two different clock duty cycles
• One where only the master can be seen• One where master and slave are present
• Record enough data point• Per resolution time• Resolution time range
Your Task (LTD MTBF)
• Analyze your measurements (MTBF vs. resolution time)• Calculate the different TAU values (master and slave, if
applicable) for all cases and simulation runs• Estimate T0 (if applicable) for all cases and simulation
runs• Plot each case in a separate plot and visualize the
above calculated parameters• Comparison plots of
• All cases in a single run• All runs for a single case
Your Task (LTD Distribution)
• Analyze your measurements (TBU distribution vs. resolution time)• Plot each case in a separate plot (rising, falling, …)• Use a box-whiskers plot• Compare the mean value (MTBU) with the standard
deviation and the smallest/largest measured value for each resolution time
• What are the implications on system reliabiltiy?
Your Task (Oscilloscope)
• Measure the output of a metastable flip flop using an oscilloscope
• Create a color-grade timing plot (using the oscilloscope) showing all measured traces• Use the large scope in the lab for color grading
• Adapters for the oscilloscope inputs will be in the lab
• Generate a histogram of all observed output delays
LTD Example Result
LTD Example Comparison
LTD Example Box Plot
LTD Example 3D Histogram
References
• PS13 - T. Polzer and A. Steininger - An Approach for Efficient Metastability Characterization of FPGAs through the Designer - 19th International Symposium on Asynchronous Circuits and Systems, 2013
• PS15 - T. Polzer and A. Steininger - Measuring the Distribution of Metastable Upsets over Time - Euromicro Conference on Digital System Design, 2015
ADVANCED DIGITAL DESIGNDESIGN EXERCISE I
Metastability Measurement and Analysis