Upload
mrithyunjaysiv
View
200
Download
1
Embed Size (px)
Citation preview
Advanced Debug With Questa
Chuck Seeley
Verification Technologist
DVT
� Introduction
� Debug Enhancements for Traditional Languages
� Debugging Constraints
� Debugging Assertions
� Debugging Dynamic Objects
Agenda
� Designs grow ~2x every 18 months
— Moore’s law still applies
� Verification requirements grow faster
— 2x more logic and complexity to verify
— Higher quality verification demanded
Today’s Verification
� Companies with the highest verification productivity
— Get new products to market faster
— Take maximum advantage of Moore’s law
— Build the most competitive products
Debug - A Big Challenge
� Designs continue to include Verilog/VHDL/SystemC
and now SystemVerilog
� Transition to HVL improve verification productivity
at the price of debug productivity
— Introduces new debug paradigm
� OVM delivering advanced techniques to everyone
� Ability to create unknown “out-of-body” code
experiences
Language and methodology are the starting point
Questa - Advancing Productivity
Class browsing & wave viewingSV/SystemC thread debugging
UPF Power-Aware SystemC TLM 2.0
Time to next simulation improvements
6.4
June 08
Verification Management
SV OVM 1.0Power-Aware Simulation
SV&SC Transaction ViewAssertion Thread View
Post-Sim Debug
6.3
May 07
SV Testbench/AVM 2.x Unified Coverage Database
VOPT SV, VHDL & SystemCFull SystemC TLM
FSM extractionSource Code Annotation
6.2
April 06
6.1
SV Testbench/AVM 1.xSVA and PSL
Functional coverageVOPT Verilog
TLM support
June 05
6.0
SystemCSystemVerilog
VHDL and VerilogModernized GUI
Aug 04
Window ManagerHyperlinked navigation
FSM ViewingVHDL Hierarchical
ReferencesVHDL Encryption
Lossless Cover Merge
6.5
Q1 09
� Leader in mixed language interoperability
� Highest performance for gate-level, RTL and TLM
� Fastest, highest capacity Unified Coverage Data Base (UCDB)
� Powerful Verification Management tools to reach coverage closure faster
� Unified debug for all languages and abstraction levels
Proven Technology
Questa – The Most Advanced Functional Verification Platform
� Introduction
� Debugging Enhancements for Traditional Languages
� Debugging Constraints
� Debugging Assertions
� Debugging Dynamic Objects
Agenda
Easing Processes Debug
View all processes
together regardless of
language
Toggle between
viewing modes
All Windows linked to process window
Integral with SystemC Debug
Interface
Message Viewer
Source Code Annotation
� Linked to cursor location in wave window
� Linked to dataflow window
Textual Dataflow: Tracing Signals
Find reader of strb_r
Select Signal then RMB
Textual Dataflow: Tracing Signals
Find driver(s) of prdy_r
Select Signal then RMB
Drop Source To Waveform
Wave Window: Signal Grouping
Group signals
under user
defined name
Drag & drop
signals into and
out of group
Drag & drop
group as one
object
Collapse &
expand group
as needed
Wave Window: Expanded Time
� Expand the Wave Window to view all transitions
during a single time step.
Indicates multiple transitions
Blue background indicates
expanded section
Delta-time steps
16
Easing Causality TracingSource Code Hyperlinking
Optional source code hyperlinking
Hyperlinked variables
17
Jump to source window and Jump to source window and
highlight variable declarationhighlight variable declaration
Easing Causality TracingSource Code Hyperlinking
Comprehensive FSM Debug Solution
State diagram animation linked
to active wave cursor
State variables identified
with FSM icon
Select FSM from list
FSM Debug with transition expressions
Control display of:* Transition counts
* State counts* Conditional paths
* Balloon popups* Wave cursor linking
FSM states:* Brown - Reset state
* Yellow - Previous state* Green - Present state
* Blue - Not one of the above
� Introduction
� Debugging Enhancements for Traditional Languages
� Debugging Constraints
� Debugging Assertions
� Debugging Dynamic Objects
Agenda
Failures during Randomization
Error reported for
failed randomization of a class object
Debugging Constraint Solver
� On randomize() failure, display the minimum set of
constraints that caused failure
— Default is off
— Setting SolveFailDebug in the modelsim.ini file
SolveFailDebug = 1
— Using -solvefaildebug on vsim command line
vsim –solvefaildebug
— Using verilog attribute in source code
randomize (* solvefaildebug=1 *) (a, b) with {a > b; a < b;};
Debugging Failures in Constraint Solver
� Derived class constraint
contains a conflict
— c0 in child
— c1 and c2 in parent
� vsim –solvefaildebug …
� Simulator output:
class TFoo;
rand bit [5:0] a, b, c;
constraint c1 { a < b; }
constraint c2 { b < c; }
constraint c3 { a < 23; }
constraint c4 { b > 12; }
constraint c5 { c == 20; }
endclass
class TBar extends TFoo;
constraint c0 { a == c; }
endclass
TBar f = new;
int status;
$display("status = f.randomize();");
# test.v(22): randomize() failed due to conflicts between the following constraints:
# test.v(5): ((f.a)<(f.b))
# test.v(6): ((f.b)<(f.c))# test.v(13): ((f.a)==(f.c))
Constraint Solver Performance
� Adjusting performance for certain types of constraints
— May improve or decrease performance
— Command line: -solveflags=<flags>
— modelsim.ini file: SolveFlags = <flags>
� Valid flags are:
i = disable bit interleaving for >, >=, <, <= constraints
n = disable bit interleaving for all constraints
r = reverse bit interleaving
� Getting more information about what solver is doing
— Command line: –solveverbose [1 or 2]
— Verbose messaging typically requires interpretation by R&D
� Introduction
� Debugging Enhancements for Traditional Languages
� Debugging Constraints
� Debugging Assertions
� Debugging Dynamic Objects
Agenda
Simulation With Assertion
� Questa ABV added value
—Advance Debug capabilities for PSL & SVA
� Integrated Assertion Browser
�View assertions in wave window
�Assertion Thread Viewer
—Best root cause analysis
Analysis Window
Capacity Details Analysis WindowPinpoint effects of Assertions on
Performance & Memory Usage
Effects of Cover Directives
Effects of
Covergroups
Viewing Assertions in the Wave
Green mid-line
indicates assertion is active
Blue low-line
indicates assertion is
inactive
Simply D&D Assertions from Assertion Browser into Wave Window to view assertions
Assertions can be expanded to view all signals associated with the assertion
Red inverted triangle
indicates assertion
failure
Green triangleindicates assertion
passed
Multiple Threads in Wave Window
Automatic Thread count
integer
Expand to see
individual thread
RMC on start of thread box
invokes ATV
Blue box above thread
indicates start of new
thread
Advanced Assertion Debug with ATVExpanded assertion
Yellow dot indicates additional thread spawned
Green dot indicates
expression is true
Redundant failure:
individual spawned thread failed but other threads still active
Red dot indicates
expression is false
Local variable
pane
ATV and Local Variables
Toggle Local Variable Pane
Annotation of local
variable on selected thread
Blue boxes indicate local variable sampling
Wave Window: Signal Grouping
Group signals
under user
defined name
Drag & drop
signals into and
out of group
Drag & drop
group as one
object
Collapse &
expand group
as needed
� Introduction
� Debugging Enhancements for Traditional Languages
� Debugging Constraints
� Debugging Assertions
� Debugging Dynamic Objects
Agenda
Viewing/Debugging SV Class Objects
� Information about SV class objects available in
several forms:
— Objects/Locals Windows
— Watch Window
— Class Tree/Class Graph
— Structure Window
� SV testbench structure for AVM/OVM
— Wave Window
� Transaction Viewing and Classes objects
Debugging Dynamic Objects
� View class contents and property values
— Useful when setting breakpoints & single stepping
Enhanced Watch Window
Understand class relationshipsSee class member values
Highlight selected relationship
� Display values for signals & variables
— View dynamic and static objects together
� arrange objects independently
� object grouping
� quickly scroll window with mouse panning
Class Tree Window
Classes can beorganized by
extended class
View all methods &
properties within a class
Classes can also beorganized by base
classView parent/child
relationship
Class Graph Window
Graph window shows all methods & properties
Zoom out to see entire hierarchy
Hover cursor over block to see name
Default view organized by extended class, can also
be viewed by base class
Transaction Viewing: The Wave Window
� OVM/AVM stimulus are transactions in streams of data
� Questa SV Transaction API enables viewing of any SV
transactions View and debug at the transaction level
OVM/AVM Classes and Questa
� Questa extracts SV TB structure from OVM/AVM class based environment
— OVM/AVM source code instrumented with Questa specific PLI calls� TB extraction occurs automatically only when using pre-compiled OVM/AVM
package or source code (Closed kit)
— OVM/AVM “static” component classes are converted into design scopes� Includes ovm_components, analysis/tlm_fifos’s, ovm_subscriber
� Object window contents are filtered to show only user added members
� Visible in sim tab of Workspace after run 0 (after OVM’s end_of_elab phase)
OVM ENVOVM ENV
DUTDUT
Workspace Instances
module cpu_wb_environment;
cpu_wb_agent wb_agent();
eth_mii_rx_agent rx_agent();
eth_mii_tx_agent tx_agent();
endmodule
� Module based hierarchy created by vopt/vsim
elaboration
class cpu_wb_environment extends ovm_env;
cpu_wb_agent wb_agent;
eth_mii_rx_agent rx_agent;
eth_mii_tx_agent tx_agent;
function new(…) … endfunction
function void build;
wb_agent = new("wb_agent",this);
rx_agent = new("rx_agent",this);
tx_agent = new("tx_agent",this);
endfunction // new
endclass
module top;
cpu_wb_environment env;
initial begin
env = new(“env”);
env.run_test();
end
endmodule
Workspace Instances
� Component hierarchy created at runtime
Other Windows and OVM TB Class scenario_base is not an ovm_component
scenario_base class reference can be added to and viewed
in the wave window
Wave window
name reflects static class hierarchy
@333 is the value assigned
to scenario_bases’class variable
Environment Class
converted to a scope
Object Window contents are
filtered to show only user added members
Sub-Env components converted to scopes
Class Objects in Wave Window
Class variable value assigned by simulator
View a class object by adding specific class
variable to wave window
Summary
� Questa’s debug features which will increase your verification productivity
— industry leading integrated and interactive debugging features supporting mixed languages in single environment
� Questa’s debug features will increase verification productivity of traditional languages and techniques
— Verilog, VHDL, and SystemC
� Questa’s supports advanced debug features required by today’s advanced verification languages and methodologies
— SV based verification methodologies� OVM/AVM/VMM
— Dynamic object support� SV/SC Transaction and Class viewing
— Assertion Based Verification� SVA and PSL