EE720Dense,Performance Directed, Auto Place

and Route

Ranjith MurugesanSpring Semester 2015

May 2, 2023

May 2, 2023 EE720 Paper Presentation 2

Author and Affiliations• Marc Rose, Manfred Wiesel, Desmond Kirkpatrick,

Nancy Nettleton

• Intel Corporation, 2625 Walsh Avenue,SC3-17,Santa Clara, California 95051

DAPR• Intel’s place and route system for standard cell based logic

• Inputs

Schematic, a chip plan, a standard cell library, a technology file

May 2, 2023 EE720 Paper Presentation 3

May 2, 2023 EE720 Paper Presentation 4

Routing• DAPR output is the layout itself and it can produce accurate

RC extraction data• Fully Automatic• 100% completion guaranteed• Metal 1 in parallel, Poly and Metal 2 are perpendicular

• Users are also allowed to execute other commands between uses of the router itself to improve the results

Techniques for High Density

• Placement of cells into back-to-back rows• Flexible cell design• Flexible connection strategy to cells• Routing through and over cells• Channel routing with multiple boundaries over variable height

cells• Compaction and contouring of cells

May 2, 2023 EE720 Paper Presentation 6

Back to Back Rows• Places the cells back to back

• Saves some area for the power lines, wells and the power taps

• Better channel utilization

• To have a fine enough control of aspect ratio, DAPR allow unpaired rows

• Better to have fewer channels and more routing in each one of them

May 2, 2023 EE720 Paper Presentation 7

Contd.

May 2, 2023 EE720 Paper Presentation 8

Flexible Cell Design

• Cell Connection points

• Variable cell height

• Standard cells must include VSS and VCC lines

• DAPR looks inside the cells and extract relevant geometries

May 2, 2023 EE720 Paper Presentation 9

Flexible Cell Connection

• Routes vertically from the channels in poly or Metal2

• Routes horizontally through the cell rows in metal1

• Poly Connection

• Via connections

May 2, 2023 EE720 Paper Presentation 10

Routing through and over Cells• Utilizes the area inside the cells free of metal 1.• Technique reduces the total height of the result.

• Advantage : Metal 2 not used in any standard cells

Channel Routing• Grid less three layer router• Solves vertical constraint graph problem for pin placement• Channels are rectilinear instead of simply rectangular• Creates protection frames for each of the routing layers• Channel Compactor• Contouring

May 2, 2023 EE720 Paper Presentation 11

Channel before and after contouring

Courtesy : Yoo,Hoi-Jun. “A Study of Pipeline Architectures for High-Speed Synchronous DRAMs.”Solid State Circuits,IEEE Journal of 32.10(1997): 1597-1603

May 2, 2023 EE720 Paper Presentation 12

Overall Steps followed in DAPR• Read performance directive file• Runs the router • Runs DAPR command Automatically sets Timber wolf placement weights Net routing priorities• Place cells closer togetherExtra options Change the standard cell location User can move chip plan pins interactively Widen individual wires

May 2, 2023 EE720 Paper Presentation 13

DAPR Results• Good results on layout with 100 to 1000 cells.

• Compares favorably with custom layout process results that are 20 to 25% larger but with much greater throughput.

• Used mostly in ASIC chips to high performance chips that are mostly custom chips.

May 2, 2023 EE720 Paper Presentation 14