ADS8598S 18-Bit, 200-kSPS, 8-Channel, Simultaneous-Sampling … · 2020. 12. 13. · ain_1p ain_1gnd ain_2p ain_2gnd ain_7p ain_7gnd ain_8p ain_8gnd 18-bit sar adc 2.5 v ref agnd

AIN_1P

AIN_1GND

AIN_2P

AIN_2GND

AIN_7P

AIN_7GND

AIN_8P

AIN_8GND

18-BitSARADC

2.5 VREF

REFGNDAGND

DVDDAVDD

ADS8598S

ADCDriver

REFIN/REFOUT

REFCAPB

REFSEL

Digital Filter

OS2

OS0

OS1

SAR Logic and

Digital ControlDB[15:0]

DOUTA

DOUTB

PAR/SER

RANGE

RD / SCLK

CS

RESET

CONVSTA, CONVSTB

FRSTDATA

STBY

REFCAPA

BUSY

1 M:Clamp

1 M:

3rd-OrderLPFClamp

PGA

ADCDriver

1 M:Clamp

1 M:

3rd-OrderLPFClamp

PGA

ADCDriver

1 M:Clamp

1 M:

3rd-OrderLPFClamp

PGA

ADCDriver

1 M:Clamp

1 M:

3rd-OrderLPFClamp

PGA

18-BitSARADC

18-BitSARADC

18-BitSARADC

SER/PAR Interface

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADS8598SSBAS827 –SEPTEMBER 2017

ADS8598S 18-Bit, 200-kSPS, 8-Channel, Simultaneous-Sampling ADC WithBipolar Inputs on a Single Supply

1

1 Features1• 18-Bit ADC With Integrated Analog Front-End• Simultaneous Sampling: 8 Channels• Pin-Programmable Bipolar Inputs: ±10 V and ±5 V• High Input Impedance: 1 MΩ• 5-V Analog Supply: 2.3-V to 5-V I/O Supply• Overvoltage Input Clamp With 9-kV ESD• Low-Drift, On-Chip Reference (2.5 V) and Buffer• Excellent Performance:

– 200-kSPS Max Throughput on All Channels– DNL: ±0.5 LSB Typ; INL: ±2.0 LSB Typ– SNR: 94 dB Typ; THD: −109 dB Typ

• Over Temperature Performance:– Max Offset Drift: 3 ppm/°C– Gain Drift: 6 ppm/°C

• On-Chip Digital Filter for Oversampling• Flexible Parallel, Byte, and Serial Interface• Temperature Range: –40°C to +125°C• Package: LQFP-64

2 Applications• Monitoring and Control for Power Grids• Protection Relays• Multi-Phase Motor Controls• Industrial Automation and Controls• Multichannel Data Acquisition Systems

3 DescriptionThe ADS8598S device is an 8-channel, integrateddata acquisition (DAQ) system based on a 18-bitsuccessive approximation (SAR) analog-to-digitalconverter (ADC). All input channels aresimultaneously sampled to achieve a maximumthroughput of 200 kSPS per channel. The devicefeatures a complete analog front-end (AFE) for eachchannel, including a programmable gain amplifier(PGA) with high input impedance of 1 MΩ, inputclamp, low-pass filter, and an ADC input driver. Thedevice also features a low-drift, precision referencewith a buffer to drive the ADC. A flexible digitalinterface supporting serial, parallel, and parallel bytecommunication enables the device to be used with avariety of host controllers.

The ADS8598S can be configured to accept ±10-V or±5-V true bipolar inputs using a single 5-V supply.The high input impedance allows direct connectionwith sensors and transformers, thus eliminating theneed for external driver circuits. The highperformance and accuracy, along with zero-latencyconversions offered by this device, also makes theADS8598S a great choice for many industrialautomation and control applications.

Device Information(1)PART NUMBER PACKAGE BODY SIZE (NOM)ADS8598S LQFP (64) 10.00 mm × 10.00 mm

(1) For all available packages, see the orderable addendum atthe end of the datasheet.

Simplified Block Diagram

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 56.2 ESD Ratings.............................................................. 56.3 Recommended Operating Conditions....................... 66.4 Thermal Information .................................................. 66.5 Electrical Characteristics........................................... 76.6 Timing Requirements: CONVST Control ................ 106.7 Timing Requirements: Data Read Operation.......... 106.8 Timing Requirements: Parallel Data Read Operation,

CS and RD Tied Together ....................................... 106.9 Timing Requirements: Parallel Data Read Operation,

CS and RD Separate ............................................... 116.10 Timing Requirements: Serial Data Read

Operation ................................................................. 116.11 Timing Requirements: Byte Mode Data Read

Operation ................................................................. 116.12 Timing Requirements: Oversampling Mode.......... 116.13 Timing Requirements: Exit Standby Mode............ 116.14 Timing Requirements: Exit Shutdown Mode......... 126.15 Switching Characteristics: CONVST Control ........ 126.16 Switching Characteristics: Parallel Data Read

Operation, CS and RD Tied Together ..................... 126.17 Switching Characteristics: Parallel Data Read

Operation, CS and RD Separate ............................. 136.18 Switching Characteristics: Serial Data Read

Operation ................................................................. 136.19 Switching Characteristics: Byte Mode Data Read

Operation ................................................................. 146.20 Typical Characteristics .......................................... 18

7 Detailed Description ............................................ 257.1 Overview ................................................................. 257.2 Functional Block Diagram ....................................... 257.3 Feature Description................................................. 267.4 Device Functional Modes........................................ 35

8 Application and Implementation ........................ 488.1 Application Information............................................ 488.2 Typical Applications ................................................ 48

9 Power Supply Recommendations ...................... 5310 Layout................................................................... 54

10.1 Layout Guidelines ................................................. 5410.2 Layout Example .................................................... 54

11 Device and Documentation Support ................. 5611.1 Documentation Support ........................................ 5611.2 Receiving Notification of Documentation Updates 5611.3 Community Resources.......................................... 5611.4 Trademarks ........................................................... 5611.5 Electrostatic Discharge Caution............................ 5611.6 Glossary ................................................................ 56

12 Mechanical, Packaging, and OrderableInformation ........................................................... 56

4 Revision History

DATE REVISION NOTESSeptember 2017 * Initial release.

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64A

IN_8

GN

D17

DB

1

1AVDD 48 AVDD

63A

IN_8

P18

DB

2

2AGND 47 AGND

62A

IN_7

GN

D19

DB

3

3OS0 46 REFGND

61A

IN_7

P20

DB

4

4OS1 45 REFCAPB

60A

IN_6

GN

D21

DB

5

5OS2 44 REFCAPA

59A

IN_6

P22

DB

6

6PAR/SER/BYTE_SEL 43 REFGND

58A

IN_5

GN

D23

DV

DD

7STBY 42 REFIN/REFOUT

57A

IN_5

P24

DB

7/D

OU

TA

8RANGE 41 AGND

56A

IN_4

GN

D25

DB

8/D

OU

TB

9CONVSTA 40 AGND

55A

IN_4

P26

AG

ND

10CONVSTB 39 REGCAP2

54A

IN_3

GN

D27

DB

9

11RESET 38 AVDD

53A

IN_3

P28

DB

10

12RD/SCLK 37 AVDD

52A

IN_2

GN

D29

DB

11

13CS 36 REGCAP1

51A

IN_2

P30

DB

12

14BUSY 35 AGND

50A

IN_1

GN

D31

DB

13

15FRSTDATA 34 REFSEL

49A

IN_1

P32

DB

14/H

BE

N

16DB0 33 DB15/BYTE_SEL

Not to scale

3

ADS8598Swww.ti.com SBAS827 –SEPTEMBER 2017


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5 Pin Configuration and Functions

PM Package64-Pin LQFP

Top View

Pin FunctionsPIN

TYPE DESCRIPTIONNAME NO.

AGND 2, 26, 35, 40,41, 47 P Analog ground pin.

AIN_1GND 50 AI Analog input channel 1: negative input.

AIN_1P 49 AI Analog input channel 1: positive input.






4




Pin Functions (continued)PIN












AVDD 1, 37, 38, 48 P Analog supply pin. Decouple this pin to the closest AGND pins(see the Power Supply Recommendations section).

BUSY 14 DO Active high digital output indicating ongoing conversion(see the BUSY (Output) section).

CONVSTA 9 DI Active high logic input to control start of conversion for first half count of device input channels (see theCONVSTA, CONVSTB (Input) section).

CONVSTB 10 DI Active high logic input to control start of conversion for second half count of device input channels (seethe CONVSTA, CONVSTB (Input) section).

CS 13 DI Active low logic input chip-select signal (see the CS (Input) section).

DB0 16 DO Data output DB0 (LSB) in parallel interface mode (see the DB[6:0] section).

DB1 17 DO Data output DB1 in parallel interface mode (see the DB[6:0] section).






DB7/DOUTA 24 DOMulti-function logic output pin (see the DB7/DOUTA section):this pin is data output DB7 in parallel and parallel byte interface mode;this pin is a data output pin in serial interface mode.

DB8/DOUTB 25 DOMulti-function logic output pin (see the DB8/DOUTB section):this pin is data output DB8 in parallel interface mode;this pin is a data output pin in serial interface mode.






DB14/HBEN 32 DIOMulti-function logic input or output pin (see the DB14/HBEN section):this pin is data output DB14 in parallel interface mode;this pin is a control input pin for byte selection (high or low) in parallel byte interface mode.

DB15/BYTE SEL 33 DIOMulti-function logic input or output pin (see the DB15/BYTE SEL section):this pin is data output DB15 (MSB) in parallel interface mode;this pin is an active high control input pin to enable parallel byte interface mode.

DVDD 23 P Digital supply pin; decouple with AGND on pin 26.

FRSTDATA 15 DO Active high digital output indicating data read back from channel 1 of the device (see the FRSTDATA(Output) section).

OS0 3 DI Oversampling mode control pin(see the Oversampling Mode of Operation section).



PAR/SER/BYTE SEL 6 DI Logic input pin to select between parallel, serial, or parallel byte interface mode (see the Data ReadOperation section).

RANGE 8 DIMulti-function logic input pin (see the RANGE (Input) section):when STBY pin is high, this pin selects the input range of the device (±10 V or ±5 V); when the STBY pinis low, this pin selects between the standby and shutdown modes.


5




Pin Functions (continued)PIN


RD/SCLK 12 DIMulti-function logic input pin (see the RD/SCLK (Input) section):this pin is an active-low ready input pin in parallel and parallel byte interface;this pin is a clock input pin in serial interface mode.

REFCAPA 44 AO Reference amplifier output pin. This pin must be shorted to REFCAPB and decoupled to AGND using alow ESR, 10-µF ceramic capacitor.

REFCAPB 45 AO Reference amplifier output pin. This pin must be shorted to REFCAPA and decoupled to AGND using alow ESR, 10-µF ceramic capacitor.

REFGND 43, 46 P Reference GND pin. This pin must be shorted to the analog GND plane and decoupled withREFIN/REFOUT on pin 42 using a 10-µF capacitor.

REFIN/REFOUT 42 AIOThis pin acts as an internal reference output when REFSEL is high;this pin functions as input pin for the external reference when REFSEL is low;decouple with REFGND on pin 43 using a 10-µF capacitor.

REFSEL 34 DI Active high logic input to enable the internal reference(see the REFSEL (Input) section).

REGCAP1 36 AO Output pin 1 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor.

REGCAP2 39 AO Output pin 2 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor.

RESET 11 DI Active high logic input to reset the device digital logic(see the RESET (Input) section).

STBY 7 DI Active low logic input to enter the device into one of the two power-down modes: standby or shutdown(see the Power-Down Modes section).

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Transient currents of up to 100 mA do not cause SCR latch-up.

6 Specifications

6.1 Absolute Maximum Ratingsat TA = 25°C (unless otherwise noted) (1)

MIN MAX UNITAVDD to AGND –0.3 7.0 VDVDD to AGND –0.3 7.0 VAnalog input voltage to AGND (2) –15 15 VDigital input to AGND –0.3 DVDD + 0.3 VREFIN to AGND –0.3 AVDD + 0.3 VInput current to any pin except supplies (2) –10 10 mA

TemperatureOperating –40 125

°CJunction, TJ 150Storage, Tstg –65 150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM),per ANSI/ESDA/JEDEC JS-001 (1)

All pins except analog inputs ±2000

VAnalog input pins only ±9000Charged-device model (CDM),per JEDEC specification JESD22-C101 (2) ±500


6




6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITAVDD Analog supply voltage 4.75 5 5.25 VDVDD Digital supply voltage 2.3 3.3 AVDD V

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

6.4 Thermal Information

THERMAL METRIC (1)ADS8598S

UNITPM (LQFP)64 PINS

RθJA Junction-to-ambient thermal resistance 46.0 °C/WRθJC(top) Junction-to-case (top) thermal resistance 7.8 °C/WRθJB Junction-to-board thermal resistance 20.1 °C/WψJT Junction-to-top characterization parameter 0.3 °C/WψJB Junction-to-board characterization parameter 19.6 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

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7




(1) Ideal input span, does not include gain or offset error.(2) LSB = least significant bit.(3) This parameter is the endpoint INL, not best-fit INL.(4) Gain error is calculated after adjusting for offset error, which implies that positive full scale error = negative full scale error = gain error ÷

2.

6.5 Electrical Characteristicsminimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at TA= 25°C; AVDD = 5 V, DVDD = 3 V, VREF = 2.5 V (internal), and fSAMPLE = 200 kSPS (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

Full-scale input span (1)(AIN_nP to AIN_nGND)

RANGE pin = 1 –10 10V

RANGE pin = 0 –5 5

AIN_nP Operating input range,positive inputRANGE pin = 1 –10 10

VRANGE pin = 0 –5 5

AIN_nGND Operating input range,negative input All input ranges –0.3 0 0.3 V

RIN Input impedance At TA = 25°C 0.85 1 1.15 MΩ

Input impedance drift All input ranges –25 ±7 25 ppm/°C

IIkg(in) Input leakage currentWith voltage at AIN_nP = VIN,all input ranges (VIN – 2) / RIN µA

SYSTEM PERFORMANCE

Resolution 18 Bits

NMC No missing codes 18 Bits

DNL Differential nonlinearity All input ranges –0.9 ±0.5 0.9 LSB (2)

INL Integral nonlinearity (3) All input ranges –5.5 ±2 5.5 LSB

EG Gain error (4)

All input ranges,externalreference

TA = –40°C to+85°C –256 ±10 256

LSBTA = –40°C to+125°C –256 ±10 300

All input ranges,internal reference ±10

Gain error matching(channel-to-channel)

Input range = ±10 V,external and internal reference 32 170

LSBInput range = ±5 V,external and internal reference 34 170

Gain error temperature drift

All input ranges,external reference –14 ±6 14

ppm/°CAll input ranges,internal reference ±10

EO Offset errorInput range = ±10 V –1.8 ±0.3 1.8

mVInput range = ±5 V –1.8 ±0.3 1.8

Offset error matching(channel-to-channel) All input ranges 0.5 5 mV

Offset error temperature drift All input ranges –3 ±0.3 3 ppm/°C

SAMPLING DYNAMICS

tACQ Acquisition time 1 µs

fSMaximum throughput rate per channelwithout latency All eight channels included 200 kSPS


8




Electrical Characteristics (continued)minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at TA= 25°C; AVDD = 5 V, DVDD = 3 V, VREF = 2.5 V (internal), and fSAMPLE = 200 kSPS (unless otherwise noted)


(5) Calculated on the first nine harmonics of the input frequency.(6) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 160 kHz to a channel, not selected in the multiplexing

sequence, and measuring the effect on the output of any selected channel.(7) Does not include the variation in voltage resulting from solder shift effects.(8) Recommended to use an X7R-grade, 0603-size ceramic capacitor for optimum performance (see the Layout Guidelines section).

DYNAMIC CHARACTERISTICS

SNRSignal-to-noise ratio,no oversampling(VIN – 0.5 dBFS at 1 kHz)

Input range = ±10 V 92 94dB

Input range = ±5 V 90.25 93.2

SNROSRSignal-to-noise ratio,oversampling = 16x(VIN – 0.5 dBFS at 130 Hz)

Input range = ±10 V 99.6 101.8dB

Input range = ±5 V 97.4 99.2

THD Total harmonic distortion(5)

(VIN – 0.5 dBFS at 1 kHz)All input ranges –109.2 –95 dB

SINADSignal-to-noise + distortion ratio,no oversampling(VIN – 0.5 dBFS at 1 kHz)

Input range = ±10 V 91.75 93.9dB

Input range = ±5 V 90 93.1

SINADOSRSignal-to-noise + distortion ratio,oversampling = 16x(VIN – 0.5 dBFS at 130 Hz)

Input range = ±10 V 98.5 101dB

Input range = ±5 V 96.6 98.9

SFDR Spurious-free dynamic range(VIN – 0.5 dBFS at 1 kHz)All input ranges 109 dB

Crosstalk isolation (6) –95 dB

BW(–3 dB) Small-signal bandwidth, –3 dB

At TA = 25°C,input range = ±10 V 24

kHzAt TA = 25°C,input range = ±5 V 16

BW(–0.1 dB) Small-signal bandwidth, –0.1 dB

At TA = 25°C,input range = ±10 V 14

kHzAt TA = 25°C,input range = ±5 V 9.5

tGROUP Group delayInput range = ±10 V 13

µsInput range = ±5 V 19

INTERNAL REFERENCE OUTPUT (REFSEL = 1)

VREF(7)Voltage on the REFIN/REFOUT pin(configured as output) At TA = 25°C 2.4975 2.5 2.5025 V

Internal reference temperature drift 7.5 ppm/°C

C(REFIN_ REFOUT)Decoupling capacitor on theREFIN/REFOUT pin (8) 10 µF

V(REFCAP)Reference voltage to the ADC(on the REFCAPA, REFCAPB pin) At TA = 25°C 3.996 4.0 4.004 V

Reference buffer output impedance 0.5 1 Ω

Reference buffer output temperature drift 5 ppm/°C

C(REFCAP)Decoupling capacitor on REFCAPA,REFCAPB 10 µF

Turn-on time C(REFCAP) = 10 µF,C(REFIN_REFOUT) = 10 µF25 ms

EXTERNAL REFERENCE INPUT (REFSEL = 0)

VREFIO_EXTExternal reference voltage on REFIO(configured as input) 2.475 2.5 2.525 V

Reference input impedance 100 MΩ

Reference input capacitance 10 pF


9




Electrical Characteristics (continued)minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at TA= 25°C; AVDD = 5 V, DVDD = 3 V, VREF = 2.5 V (internal), and fSAMPLE = 200 kSPS (unless otherwise noted)


POWER-SUPPLY REQUIREMENTS

AVDD Analog power-supply voltage Analog supply 4.75 5 5.25 V

DVDD Digital power-supply voltage Digital supply range 2.3 3.3 AVDD V

IAVDD_DYNAnalog supply current(operational)

AVDD = 5 V,fS = 200 kSPS,internal reference

17.7 24

mAAVDD = 5 V,fS = 200 kSPS,external reference

17.1 24

IAVDD_STCAnalog supply current(static)

AVDD = 5 V, internal reference,device not converting 12.4 17

mAAVDD = 5 V, external reference,device not converting 12 17

IAVDD_STDBYAVDD supplySTANDBY current

At AVDD = 5 V, device in STDBYmode, internal reference 4.2 5.5

mAAt AVDD = 5 V, device in STDBYmode, external reference 3.8 5.0

IAVDD_PWR_ DNAVDD supplypower-down current

At AVDD = 5 V, device in PWR_DN,internal orexternal reference,TA = –40°C to +85°C

0.2 6 µA

IDVDD_DYN Digital supply currentDVDD = 3.3 V,fS = 200 kSPS

0.15 0.3 mA

IDVDD_STDBY DVDD supply STANDBY currentAt AVDD = 5 V, device in STDBYmode 0.05 1.5 µA

IDVDD_PWR-DN DVDD supply power-down currentAt AVDD = 5 V, device in PWR_DNmode 0.05 1.5 µA

DIGITAL INPUTS (CMOS)

VIH Digital high input voltage logic level DVDD > 2.3 V 0.7 × DVDD DVDD + 0.3 V

VIL Digital low input voltage logic level DVDD > 2.3 V –0.3 0.3 × DVDD V

Input leakage current 100 nA

Input pin capacitance 5 pF

DIGITAL OUTPUTS (CMOS)

VOH Digital high output voltage logic level IO = 100-µA source 0.8 × DVDD DVDD V

VOL Digital low output voltage logic level IO = 100-µA sink 0 0.2 × DVDD V

Floating state leakage current Only for SDO 1 µA

Internal pin capacitance 5 pF

TEMPERATURE RANGE

TA Operating free-air temperature –40 125 °C


10




6.6 Timing Requirements: CONVST Controlminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), BUSY load = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 200 kSPS(unless otherwise noted) (see Figure 1)

MIN NOM MAX UNIT

tACQAcquisition time:BUSY falling edge to rising edge of trailing CONVSTA or CONVSTB 1 µs

tPH_CN CONVSTA, CONVSTB pulse high time 25 nstPL_CN CONVSTA, CONVSTB pulse low time 25 nstSU_BSYCS Setup time: BUSY falling to CS falling 0 nstSU_RSTCN Setup time: RESET falling to first rising edge of CONVSTA or CONVSTB 25 nstPH_RST RESET pulse high time 50 nstD_CNAB Delay between rising edges of CONVSTA and CONVSTB 500 µs

6.7 Timing Requirements: Data Read Operationminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), BUSY load = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 200 kSPS(unless otherwise noted) (see Figure 2)

MIN NOM MAX UNIT

tDZ_CNCSDelay between CONVSTA, CONVSTB rising edge to CS falling edge, start ofdata read operation during conversion 10 ns

tDZ_CSBSYDelay between CS rising edge to BUSY falling edge, end of data readoperation during conversion 40 ns

tSU_BSYCSSetup time: BUSY falling edge to CS falling edge, start of data read operationafter conversion 0 ns

tD_CSCNDelay between CS rising edge to CONVSTA, CONVSTB rising edge, end ofdata read operation after conversion 10 ns

6.8 Timing Requirements: Parallel Data Read Operation, CS and RD Tied Togetherminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, andfSAMPLE = 200 kSPS (unless otherwise noted) (see Figure 3)

MIN NOM MAX UNITtPH_CS,tPH_RD

CS and RD high time 15 ns

tPL_CS,tPL_RD

CS and RD low time 15 ns

tHT_RDDB,tHT_CSDB

Hold time: RD and CS rising edge to DB[15:0] invalid 2.5 ns


11




6.9 Timing Requirements: Parallel Data Read Operation, CS and RD Separateminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, andfSAMPLE = 200 kSPS (unless otherwise noted) (see Figure 4)

MIN NOM MAX UNITtSU_CSRD Set-up time: CS falling edge to RD falling edge 0 nstHT_RDCS Hold time: RD rising edge to CS rising edge 0 nstPL_RD RD low time 15 nstPH_RD RD high time 15 nstHT_CSDB Hold time: CS rising edge to DB[15:0] becoming invalid 6 nstHT_RDDB Hold time: RD rising edge to DB[15:0] becoming invalid 2.5 ns

6.10 Timing Requirements: Serial Data Read Operationminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, VIL and VIH at specifiedlimits, and fSAMPLE = 200 kSPS (unless otherwise noted) (see Figure 5)

MIN NOM MAX UNITtSCLK SCLK time period 50 nstPH_SCLK SCLK high time 0.45 0.55 tSCLKtPL_SCLK SCLK low time 0.45 0.55 tSCLKtHT_CKDO Hold time: SCLK rising edge to DOUTA, DOUTB invalid 7 nstSU_CSCK Setup time: CS falling to first SCLK edge 8 nstHT_CKCS Hold time: last SCLK active edge to CS high 10 ns

6.11 Timing Requirements: Byte Mode Data Read Operationminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, andfSAMPLE = 200 kSPS (unless otherwise noted) (see Figure 6)

MIN NOM MAX UNITtSU_CSRD Setup time: CS falling edge to RD falling edge 0 nstHT_RDCS Hold time: RD rising edge to CS rising edge 0 nstPL_RD RD low time 15 nstPH_RD RD high time 15 nstHT_CSDB Hold time: CS rising edge to DB[15:0] becoming invalid 6 nstHT_RDDB Hold time: RD rising edge to DB[15:0] becoming invalid 2.5 ns

6.12 Timing Requirements: Oversampling Modeminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), VIL and VIH at specified limits, and fSAMPLE = 200 kSPS (unless otherwisenoted) (see Figure 7)

MIN NOM MAX UNITtHT_OS Hold time: BUSY falling to OSx 20 nstSU_OS Setup time: BUSY falling to OSx 20 ns

(1) First conversion data must be discarded or RESET must be issued if the maximum timing is exceeded.

6.13 Timing Requirements: Exit Standby Modeminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C, AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), VIL and VIH at specified limits, and fSAMPLE = 200 kSPS (unless otherwisenoted) (see Figure 8)

MIN NOM MAX UNITtD_STBYCN Delay between STBY rising edge to CONVSTA or CONVSTB rising edge (1) 100 µs


12




(1) Excludes wake-up time for external reference device.

6.14 Timing Requirements: Exit Shutdown Modeminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), VIL and VIH at specified limits, and fSAMPLE = 200 kSPS (unless otherwisenoted) (see Figure 9)

MIN NOM MAX UNIT

tD_SDRST Delay between STBY rising edge to RESET rising edgeInternal reference mode 50

msExternal reference mode (1) 13

tPH_RST RESET high time 50 nstD_RSTCN Delay between RESET falling edge to CONVSTA or CONVSTB rising edge 25 µs

6.15 Switching Characteristics: CONVST Controlminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), BUSY load = 20 pF, VIL and VIH at specified limits, and fSAMPLE = 200 kSPS(unless otherwise noted) (see Figure 1)


tCYC ADC cycle time period

No oversampling, parallel read, serialread with both DOUTA and DOUTBduring conversion

5

µsNo oversampling, serial read afterconversion with both DOUTA andDOUTB

9.7

No oversampling, serial read afterconversion with only DOUTA orDOUTB

15

tCONV Conversion time: BUSY high time

No oversampling 3.7 3.8 3.9

µs

Oversampling by 2 8.4 8.8Oversampling by 4 17 18Oversampling by 8 34 36Oversampling by 16 68 72Oversampling by 32 136 144Oversampling by 64 272 288

tD_CNBSYDelay between trailing rising edges ofCONVSTA or CONVSTB and BUSYrising

15 ns

6.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Togetherminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, andfSAMPLE = 200 kSPS (unless otherwise noted) (see Figure 3)


tD_CSDB,tD_RDDB

Delay time: CS and RD falling edge toDB[15:0] becoming valid(out of tri-state)

12 ns

tD_CSFD,tD_RDFD

Delay time: CS and RD falling edge toFRSTDATA going high or low out of tri-state

10 ns

tDHZ_CSDB,tDHZ_RDDB

Delay time: CS and RD rising edge toDB[15:0] tri-state 12 ns

tDHZ_CSFD,tDHZ_RDFD

Delay time: CS and RD rising edge toFRSTDATA tri-state 10 ns


13




6.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separateminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, andfSAMPLE = 200 kSPS (unless otherwise noted) (see Figure 4)


tD_CSDBDelay time: CS falling edge to DB[15:0]becoming valid(out of tri-state)

12 ns

tD_RDDBDelay time: RD falling edge to new dataon DB[15:0] 17 ns

tDHZ_CSDBDelay time: CS rising edge to DB[15:0]becoming tri-state 12 ns

tD_CSFDDelay time: CS falling edge toFRSTDATA going low out of tri-state 15 ns

tDHZ_CSFDDelay time: CS rising edge toFRSTDATA going to tri-state 10 ns

tD_RDFDDelay time: RD falling edge toFRSTDATA going high or low 15 ns

6.18 Switching Characteristics: Serial Data Read Operationminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, VIL and VIH at specifiedlimits, and fSAMPLE = 200 kSPS (unless otherwise noted) (see Figure 5)


tD_CSDODelay time: CS falling edge to DOUTA,DOUTB enable(out of tri-state)

12 ns

tD_CKDODelay time: SCLK rising edge to validdata on DOUTA, DOUTB 15 ns

tDZ_CSDODelay time: CS rising edge to DOUTA,DOUTB going to tri-state 12 ns

tD_CSFDDelay time: CS falling edge toFRSTDATA from tri-state to high or low 10 ns

tDZ_CKFDDelay time: 18th SCLK falling edge toFRSTDATA falling edge 15 ns



CONVSTA

CONVSTB

BUSY tCONV

tD_CNAB

tD_CNBSY

tACQ

tCYC

tPH_CNtPL_CN

CS

tSU_BSYCS

RESET

tSU_RSTCN

tPH_RST

14




6.19 Switching Characteristics: Byte Mode Data Read Operationminimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, VIL and VIH at specified limits, andfSAMPLE = 200 kSPS (unless otherwise noted) (see Figure 6)


tD_CSDBDelay time: CS falling edge toDB[7:0] becoming valid(out of tri-state)

12 ns

tD_RDDBDelay time: RD falling edge tonew data on DB[7:0] 17 ns

tDHZ_CSDB

Delay time: CS rising edge toDB[7:0] becoming tri-state 12 ns

tD_CSFDDelay time: CS falling edge toFRSTDATA going low out of tri-state

10 ns

tD_RDFDDelay time: RD falling edge toFRSTDATA going low or highstate

15 ns


Figure 1. CONVST Control Timing Diagram


CS

DB[15:0]

FRSTDATA

RD

tD_CSDB

tD_CSFD

AIN_1[17:2]

AIN_1[1:0]

AIN_2[17:2]

AIN_2[1:0]

AIN_3[17:2]

AIN_8[17:2]

AIN_8[1:0]

tPH_RD

tHT_CSDBtDHZ_CSDB

tDHZ_CSFD

tSU_CSRDtPL_RD

Invalid

tHT_RDDBtD_RDDB

tHT_RDCS

tD_RDFD

DB[15:0]

FRSTDATA

tD_CSDB

tD_CSFD

AIN_1[17:2]

AIN_1[1:0]

tPH_RD

tDHZ_CSDB

tDHZ_CSFD

AIN_2[17:2]

AIN_2[1:0]

AIN_7[17:2]

AIN_7[1:0]

AIN_8[17:2]

AIN_8[1:0]

tD_RDDB

tPH_CS

tD_RDFD

tDHZ_RDDB

tDHZ_RDFD

tPL_RDtPL_CS

tHT_RDDBtHT_CSDB

CS RD,

CONVSTACONVSTB

BUSY

tDZ_CNCS

CS

tDZ_CSBSY

tSU_BSYCS tD_CSCN

Read During Conversion Read After Conversion

RESET tPH_RST

tSU_RSTCN

15




Figure 2. Data Read Operation Timing Diagram

Figure 3. Parallel Data Read Operation, CS and RD Tied Together

Figure 4. Parallel Data Read Operation, CS and RD Separate


CONVSTACONVSTB

BUSY

OSR x

OSR latched for Conversion (N+1)

tHT_OS

Conversion N

Conversion N+1

tSU_OS

CS

DB[7:0]

FRSTDATA

RDtD_CSDB

tD_CSFD

High Byte AIN_1

Mid Byte AIN_1

Low Byte AIN_1

High Byte AIN_2

Mid Byte AIN_8

Low Byte AIN_8

tPH_RD

tHT_CSDBtDHZ_CSDB

tDHZ_CSFD

tSU_CSRDtPL_RD

Invalid

tD_RDFD

tHT_RDDB tD_RDDB

tHT_RDCS

FRSTDATA

tDHZ_CSFD

CS

SCLK

DB17 DB16 DB15 DB1 DB0DOUTADOUTB

tPH_SCLKtPL_SCLK

tSCLK

tSU_CSCK

tD_CSDOtHT_CKDO tD_CKDO

tDZ_CKFD

tDZ_CSDO

tHT_CKCS

tD_CSFD

16




Figure 5. Serial Data Read Operation Timing Diagram

Figure 6. Byte Mode Data Read Operation Timing Diagram

Figure 7. Oversampling Mode Timing Diagram


STBY

tD_SDRST

RANGE

RESET

CONVSTACONVSTB

tPH_RST

tD_RSTCN

STBY

tD_STBYCN

RANGE

CONVSTACONVSTB

17




Figure 8. Exit Standby Mode Timing Diagram

Figure 9. Exit Shutdown Mode Timing Diagram


Output Codes

Num

ber

of H

its

0

100

200

300

400

500

600

700

800

-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11

D010Codes (LSB) 2's Complement

Diff

eren

tial N

onlin

earit

y (L

SB

)

-131072 -65536 0 65536 131071-1.5

-1

-0.5

0

0.5

1

1.5

D011

Free-Air Temperature (qC)

Inpu

t Im

peda

nce

(M:

)

-40 -7 26 59 92 1250.95

0.97

0.99

1.01

1.03

1.05

D004

± 10 V± 5 V

Output Codes

Num

ber

of H

its

0

100

200

300

400

500

600

700

-9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10

D009

Input Voltage (V)

Ana

log

Inpu

t Cur

rent

(uA

)

-10 -6 -2 2 6 10-15

-9

-3

3

9

15

D002

25 C-40 C125 C

Input Voltage (V)

Ana

log

Inpu

t Cur

rent

(uA

)

-5 -3 -1 1 3 5-9

-6

-3

0

3

6

9

D003

25 C-40 C125 C

18




6.20 Typical Characteristicsat TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 200 kSPS per channel (unless otherwisenoted)

Figure 10. Analog Input Current vs Input Voltage andTemperature (±10 V)

Figure 11. Analog Input Current vs Input Voltage andTemperature (±5 V)

Figure 12. Input Impedance vs Free-Air Temperature

Mean = 0.71, sigma = 1.83, number of hits = 4096, VIN = 0 V

Figure 13. DC Histogram of Codes (±10 V)

Mean = 0.86, sigma = 2.1, number of hits = 4096, VIN = 0 V

Figure 14. DC Histogram of Codes (±5 V) Figure 15. DNL for All Codes



Inte

gral

Non

linea

rity

(LS

B)

-40 -7 26 59 92 125-10

-6

-2

2

6

10

D016

MaximumMinimum


Offs

et E

rror

(m

V)

-40 -7 26 59 92 125-1.8

-1.08

-0.36

0.36

1.08

1.8

D017

± 10 V± 5 V

Codes (LSB) 2's Complement

Inte

gral

Non

linea

rity

(LS

B)

-131072 -65536 0 65536 131071-5

-3

-1

1

3

5

D014 Free-Air Temperature (qC)

Inte

gral

Non

linea

rity

(LS

B)

-40 -7 26 59 92 125-10

-6

-2

2

6

10

D015

MaximumMinimum


Diff

eren

tial N

onlin

earit

y (L

SB

)

-40 -7 26 59 92 125-1.5

-0.75

0

0.75

1.5

D012

MaximumMinimum

Codes (LSB) 2's Complement

Inte

gral

Non

linea

rity

(LS

B)

-131072 -65536 0 65536 131071-5

-3

-1

1

3

5

D013

19




Typical Characteristics (continued)at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 200 kSPS per channel (unless otherwisenoted)

Figure 16. DNL vs Free-Air Temperature Figure 17. INL vs All Codes (±10 V)

Figure 18. INL vs All Codes (±5 V) Figure 19. INL vs Free-Air Temperature (±10 V)

Figure 20. INL vs Free-Air Temperature (±5 V) Figure 21. Offset Error vs Free-Air Temperature



Gai

n E

rror

(LS

B)

-40 -7 26 59 92 125-200

-100

0

100

200

D022

± 10 V± 5 V

Gain Drift (ppm/qC)

Num

ber

of H

its

0

10

20

30

40

50

60

70

80

0 1.76 4.21 5.595 6.98 8.365 9.75 11.13512.52 14

D023


Offs

et E

rror

(m

V)

-40 -7 26 59 92 125-1.8

-1.08

-0.36

0.36

1.08

1.8

D021

Channel 1Channel 2Channel 3


Channel 7Channel 8

Offset Drift (ppm/qC)

Num

ber

of H

its

0

10

20

30

40

50

60

70

80

90

100

110

120

130

0 0.22 0.49 0.76 1.03 1.3 1.57 1.84 2.11 2.38 2.65 3

D020


Offs

et E

rror

(m

V)

-40 -7 26 59 92 125-1.8

-1.08

-0.36

0.36

1.08

1.8

D019



Channel 7Channel 8

Offset Drift (ppm/qC)

Num

ber

of H

its

0

10

20

30

40

50

60

70

80

90

100

110

120

130

0 0.355 0.76 1.165 1.57 1.975 2.38 2.785 3

D018

20





Figure 22. Offset Drift Histogram Distribution (±10 V) Figure 23. Offset Error Across Channels vs Free-AirTemperature (±10 V)

Figure 24. Offset Drift Histogram Distribution (±5 V) Figure 25. Offset Error Across Channels vs Free-AirTemperature (±5 V)

External reference

Figure 26. Gain Error vs Temperature

External reference

Figure 27. Gain Error Drift Histogram Distribution (±10 V)


Frequency (kHz)

Am

plitu

de (

dB)

0 25 50 75 100-200

-150

-100

-50

0

D028Frequency (kHz)

Am

plitu

de (

dB)

0 25 50 75 100-200

-150

-100

-50

0

D029


Gai

n E

rror

(LS

B)

-40 -7 26 59 92 125-250

-150

-50

50

150

250

D026

Channel 1Channel 2Channel 3Channel 4Channel 5Channel 6Channel 7Channel 8

Source Resistance (k:)

Gai

n E

rror

(%

FS

)

0 50 100 150 200-20

0

20

40

60

80

100

D027

± 10 V± 5 V


Gai

n E

rror

(LS

B)

-40 -7 26 59 92 125-500

-350

-200

-50

100

250

400

D024

Channel 1Channel 2Channel 3Channel 4Channel 5Channel 6Channel 7Channel 8

Gain Drift (ppm/qC)

Num

ber

of H

its

0

10

20

30

40

50

60

70

80

0 1.76 4.21 5.595 6.98 8.365 9.75 11.13512.52 14

D025

21





External reference

Figure 28. Gain Error Across Channels vs Free-AirTemperature (±10 V)

External reference

Figure 29. Gain Error Drift Histogram Distribution (±5 V)

External reference

Figure 30. Gain Error Across Channels vs Free-AirTemperature (±5 V)

Figure 31. Gain Error as a Function of External SourceResistance

Number of points = 256k, SNR = 93.77 dB,SINAD = 93.52 dB, THD = –105.93, SFDR = 106.98 dB

Figure 32. Typical FFT Plot (±10 V)

Number of points = 256k, SNR = 92.45 dB,SINAD = 92.26 dB, THD = –105.85 dB, SFDR = 107.12 dB

Figure 33. Typical FFT Plot (±5 V)


Input Frequency (Hz)

Sig

nal-t

o-N

oise

Rat

io (

dB)

85

89

93

97

101

105

10 100 1k 10k 100k

D034

OSR-0OSR-2OSR-4OSR-8

OSR-16OSR-32OSR-64


Sig

nal-t

o-N

oise

Rat

io (

dB)

88

91

94

97

100

103

10 100 1k 10k 100k

D035

OSR-0OSR-2OSR-4OSR-8OSR-16OSR-32OSR-64


Sig

nal-t

o-N

oise

Rat

io (

dB)

89

90

91

92

93

94

95

100 1k 10k 100k

D032

± 10 V± 5 V

Free-Air Temperature q(C)

Sig

nal-t

o-N

oise

Rat

io (

dB)

-40 -7 26 59 92 12590

91

92

93

94

95

D033

± 10 V± 5 V

Frequency (kHz)

Am

plitu

de (

dB)

0 1.25 2.5 3.75 5 6.25-200

-150

-100

-50

0

D030Frequency (kHz)

Am

plitu

de (

dB)

0 1.25 2.5 3.75 5 6.25-200

-150

-100

-50

0

D031

22






Figure 34. Typical FFT Plot for OSR 16x (±10 V)


Figure 35. Typical FFT Plot for OSR 16x (±5 V)

OSR = 0

Figure 36. SNR vs Input Frequency for Different InputRanges

OSR = 0

Figure 37. SNR vs Free-Air Temperature for Different InputRanges

Figure 38. SNR vs Input Frequency for Different OSR(±10 V)

Figure 39. SNR vs Input Frequency for Different OSR(±5 V)



Tot

al H

arm

onic

Dis

tort

ion

(dB

)

-120

-110

-100

-90

-80

-70

-60

1k 10k 100k

D040

0 k:10 k:20 k:30 k:40 k:50 k:61 k:68.1 k:82.5 k:90.9 k:100 k:


Tot

al H

arm

onic

Dis

tort

ion

(dB

)

-120

-110

-100

-90

-80

-70

-60

1k 10k 100k

D041

0 k:10 k:20 k:30 k:40 k:50 k:61 k:68.1 k:82.5 k:90.9 k:100 k:


Tot

al H

arm

onic

Dis

tort

ion

(dB

)

-130

-125

-120

-115

-110

-105

-100

-95

-90

-85

-80

100 1k 10k 100k

D038

± 10 V± 5 V


Tot

al H

arm

onic

Dis

tort

ion

(dB

)

-40 -7 26 59 92 125-120

-115

-110

-105

-100

D039

± 10 V± 5 V


Sig

nal-t

o-N

oise

+ D

isto

rtio

n R

atio

(dB

)

89

90

91

92

93

94

95

100 1k 10k 100k

D036

± 10 V± 5 V


Sig

nal-t

o-N

oise

+ D

isto

rtio

n R

atio

(dB

)

-40 -7 26 59 92 12590

91

92

93

94

95

D037

± 10 V± 5 V

23





OSR = 0

Figure 40. SINAD vs Input Frequency for Different InputRanges

OSR = 0

Figure 41. SINAD vs Free-Air Temperature for Different InputRanges

Figure 42. THD vs Input Frequency for Different InputRanges

Figure 43. THD vs Free-Air Temperature for Different InputRanges

Figure 44. THD vs Input Frequency for Different SourceImpedances (±10 V)

Figure 45. THD vs Input Frequency for Different SourceImpedances (±5 V)



Ana

log

Sup

ply

Cur

rent

(P

A)

-40 -7 26 59 92 125-1

0

1

2

3

4

5

6

D057Free-Air Temperature (qC)

Ana

log

Sup

ply

Cur

rent

(m

A)

-40 -7 26 59 92 1254.12

4.14

4.16

4.18

4.2

4.22

4.24

4.26

D056


Ana

log

Sup

ply

Cur

rent

(m

A)

-40 -7 26 59 92 12516.5

17

17.5

18

18.5

19

19.5

D053

± 10 V± 5 V


Ana

log

Sup

ply

Cur

rent

(m

A)

-40 -7 26 59 92 12512.2

12.4

12.6

12.8

13

13.2

13.4

13.6

D055

± 10 V± 5 V

Frequency (kHz)

Isol

atio

n C

ross

talk

(dB

)

-140

-130

-120

-110

-100

-90

100m 1 10 100

D042

±5 V±10 V

Frequency (kHz)

Isol

atio

n C

ross

talk

(dB

)

-150

-140

-130

-120

-110

-100

-90

100m 1 10 100D043

± 5 V± 10 V

24





Figure 46. Isolation Crosstalk vs Frequency(Inputs Within Range)

Figure 47. Isolation Crosstalk vs Frequency (SaturatedInputs)

Figure 48. Analog Supply Current (Operational) vs Free-AirTemperature

Figure 49. Analog Supply Current (Static) vs Free-AirTemperature (Sampling)

Figure 50. Analog Supply Current vs Free-Air Temperature(Standby)

Figure 51. Analog Supply Current vs Free-Air Temperature(Shutdown)


18-bitSAR ADC

2.5 V VREF

REFGNDAGND

DVDDAVDD

ADS8598S

ADCDriver

REFIN / REFOUT

REFCAPB

REFSEL

Digital Filter OS1

OS0

OS2

SARLogic and

Digital Control DB[15:0]

DOUTA

DOUTB

RANGE

CS

RESET

CONVSTA/B

FRSTDATA

REFCAPA

BUSY1 M�

Clamp3rd -Order

LPFClampPGA

ADCDriver

Clamp

ClampPGA

ADCDriver

Clamp

ClampPGA

Clamp

ClampPGA

Clamp

ClampPGA

Clamp

ClampPGA

Clamp

ClampPGA

Clamp

ClampPGA

AIN_1P

AIN_1GND

AIN_2P

AIN_2GND

AIN_3P

AIN_3GND

AIN_4P

AIN_4GND

AIN_5P

AIN_5GND

AIN_6P

AIN_6GND

AIN_7P

AIN_7GND

AIN_8P

AIN_8GND

PAR/ SER

RD/SCLK

STBY

SER / PARInterface

ADCDriver

ADCDriver

ADCDriver

ADCDriver

ADCDriver

18-bitSAR ADC

18-bitSAR ADC

18-bitSAR ADC

18-bitSAR ADC

18-bitSAR ADC

18-bitSAR ADC

18-bitSAR ADC

1 M�

1 M�

1 M�

1 M�

1 M�

1 M�

1 M�

1 M�

1 M�

1 M�

1 M�

1 M�

1 M�

1 M�

1 M�


3rd -OrderLPF

3rd -OrderLPF

3rd -OrderLPF

3rd -OrderLPF

3rd -OrderLPF

3rd -OrderLPF

3rd -OrderLPF

25




7 Detailed Description

7.1 OverviewThe ADS8598S is an 18-bit data acquisition (DAQ) system with 8-channel analog inputs. Each analog inputchannel consists of an input clamp protection circuit, a programmable gain amplifier (PGA), a third-order, low-pass filter, and a track-and-hold circuit that facilitates simultaneous sampling of the signals on all input channels.The sampled signal is digitized using an 18-bit analog-to-digital converter (ADC), based on the successiveapproximation register (SAR) architecture. This overall system can achieve a maximum throughput of 200 kSPSfor each channel. The device features a 2.5-V internal reference with a fast-settling buffer, a programmabledigital averaging filter to improve noise performance, and high speed serial and parallel interfaces forcommunication with a wide variety of digital hosts.

The device operates from a single 5-V analog supply and can accommodate true bipolar input signals of ±10 Vand ±5 V. The input clamp protection circuitry can tolerate voltages up to ±15 V. The device offers a constant1-MΩ resistive input impedance irrespective of the sampling frequency or the selected input range. Theintegration of multiple, simultaneously sampling precision ADC inputs and analog front-end circuits with highinput impedance operating from a single 5-V supply offers a simplified end solution without requiring externalhigh-voltage bipolar supplies and complicated driver circuits.

7.2 Functional Block Diagram


AIN_nP

AIN_nGNDADCDriver

1 M:Clamp

1 M:

ClampPGA

18-bitSARADC

3rd-OrderLPF

26




7.3 Feature Description

7.3.1 Analog InputsThe ADS8598S has 8 analog input channels, such that the positive inputs AIN_nP (n = 1 to 8) are the single-ended analog inputs and the negative inputs AIN_nGND are tied to GND. Figure 52 shows the simplified circuitschematic for each analog input channel, including the input clamp protection circuit, PGA, low-pass filter, high-speed ADC driver, and a precision 18-bit SAR ADC.

Figure 52. Front-End Circuit Schematic for Each Analog Input Channel

The device can support two bipolar, single-ended input voltage ranges based on the logic level of the RANGEinput pin. As explained in the RANGE (Input) section, the input voltage range for all analog channels can beconfigured to bipolar ±10 V or ±5 V. The device samples the voltage difference (AIN_nP – AIN_nGND) betweenthe selected analog input channel and the AIN_nGND pin. The device allows a ±0.3-V range on the AIN_nGNDpin for all analog input channels. Use this feature in modular systems where the sensor or signal conditioningblock is further away from the ADC on the board and when a difference in the ground potential of the sensor orsignal conditioner from the ADC ground is possible. In such cases, running separate wires from the AIN_nGNDpin of the device to the sensor or signal conditioning ground is recommended.

7.3.2 Analog Input ImpedanceEach analog input channel in the device presents a constant resistive impedance of 1 MΩ. The input impedancefor each channel is independent of either the input signal frequency, the configured range of the ADC, or theoversampling mode. The primary advantage of such high-impedance inputs is the ease of driving the ADC inputswithout requiring driving amplifiers with low output impedance. Bipolar, high-voltage power supplies are notrequired in the system because this ADC does not require any high-voltage, front-end drivers. In mostapplications, the signal sources or sensor outputs can be directly connected to the ADC input, thus significantlysimplifying the design of the signal chain.

In order to maintain the dc accuracy of the system, matching the external source impedance on the AIN_nP inputpin with an equivalent resistance on the AIN_nGND pin is recommended (see Figure 54). This matching helps tocancel any additional offset error contributed by the external resistance.

7.3.3 Input Clamp Protection CircuitAs illustrated in Figure 52, the ADS8598S features an internal clamp protection circuit on each of the 8 analoginput channels. Use of external protection circuits is recommended as a secondary protection scheme to protectthe device. Using external protection devices helps with protection against surges, electrostatic discharge (ESD),and electrical fast transient (EFT) conditions.

The input clamp protection circuit on the ADS8598S allows each analog input to swing up to a maximum voltageof ±15 V. Beyond an input voltage of ±15 V, the input clamp circuit turns on, still operating off the single 5-Vsupply. Figure 53 illustrates a typical current versus voltage characteristic curve for the input clamp. There is nocurrent flow in the clamp circuit for input voltages up to ±15 V. Beyond this voltage, the input clamp circuit turnson.


REXTAIN_nP

AIN_nGNDREXT

Input Signal

C

1 M

Clamp

1 M

Clamp

PGA

Input Voltage (V)

Inpu

t Cla

mp

Cur

rent

(m

A)

-20 -15 -10 -5 0 5 10 15 20-50

-40

-30

-20

-10

0

10

20

30

40

50

D007

27




Feature Description (continued)

Figure 53. I-V Curve for an Input Clamp Protection Circuit (AVDD = 5 V)

For input voltages above the clamp threshold, make sure that input current never exceeds the absolutemaximum rating (see the Absolute Maximum Ratings table) of ±10 mA to prevent any damage to the device.Figure 54 shows that a small series resistor placed in series with the analog inputs is an effective way to limit theinput current. In addition to limiting the input current, this resistor can also provide an antialiasing, low-pass filterwhen coupled with a capacitor. In order to maintain the dc accuracy of the system, matching the external sourceimpedance on the AIN_nP input pin with an equivalent resistance on the AIN_nGND pin is recommended. Thismatching helps to cancel any additional offset error contributed by the external resistance.

Figure 54. Matching Input Resistors on the Analog Inputs of Device

The input overvoltage protection clamp on the ADS8598S is intended to control transient excursions on the inputpins. Leaving the device in a state such that the clamp circuit is activated for extended periods of time in normalor power-down mode is not recommended because this fault condition can degrade device performance andreliability.

7.3.4 Programmable Gain Amplifier (PGA)The device offers a programmable gain amplifier (PGA) at each individual analog input channel that converts theoriginal single-ended input signal into a fully-differential signal to drive the internal 18-bit SAR ADC. The PGAalso adjusts the common-mode level of the input signal before being fed into the ADC to ensure maximum usageof the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be accordinglyadjusted by configuring the RANGE pin of the ADC (see the RANGE (Input) section).

The PGA uses a very highly matched network of resistors for programmable gain configurations. Matchingbetween these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gainerror low across all channels and input ranges.



Mag

nitu

de (

dB)

-10

-8

-6

-4

-2

0

100 1k 10k 100k

D046

± 5 V± 10 V

Input Frequency (Hz)G

roup

Del

ay (P

s)0

5

10

15

20

25

30

1 10 100 1k 10k 100k

D047

± 5 V± 10 V

28




Feature Description (continued)7.3.5 Third-Order, Low-Pass Filter (LPF)In order to mitigate the noise of the front-end amplifiers and gain resistors of the PGA, each analog input channelof the ADS8598S features a third-order, Butterworth antialiasing, low-pass filter (LPF) at the output of the PGA.Figure 55 and Figure 56 (respectively) show the magnitude and phase response of the analog antialiasing filter.For maximum performance, the –3-dB cutoff frequency for the antialiasing filter is designed to be equal to 24 kHzfor the ±10-V range and 16 kHz for the ±5-V range.

Figure 55. Third-Order LPF Magnitude Response Figure 56. Third-Order LPF Phase Response

7.3.6 ADC DriverIn order to meet the performance of an 18-bit, SAR ADC at the maximum sampling rate (200 kSPS per channel),the capacitors at the input of the ADC must be successfully charged and discharged during the acquisition timewindow. The inputs of the ADC must settle to better than 18-bit accuracy before any sampled analog voltagegets converted. This drive requirement at the inputs of the ADC necessitates the use of a high-bandwidth, low-noise, and stable amplifier buffer. The ADS8598S features an integrated input driver as part of the signal chainfor each analog input. This integrated input driver eliminates the need for any external amplifier, thus simplifyingthe signal chain design.


29




Feature Description (continued)7.3.7 Digital Filter and NoiseThe ADS8598S features an optional digital averaging filter that can be used in slower throughput applicationsrequiring lower noise and higher dynamic range. As explained in Table 1, the oversampling ratio of the digitalfilter is determined by the configuration of the OS[2:0] pins. The overall throughput of the ADC decreasesproportionally with increase in the oversampling ratio.

Table 1. Oversampling Bit Decoding

OS[2:0] OSRATIOSNR

±10-V INPUT(dB)

SNR±5-V INPUT

(dB)

3-dB BANDWIDTH±10-V INPUT

(kHz)

3-dB BANDWIDTH±5-V INPUT

(kHz)

MAX THROUGHPUTPER CHANNEL

(kSPS)000 No OS 94.04 93.25 24 16 200001 2 95.95 94.91 23 15.7 100010 4 96.93 95.7 19.2 14.5 50011 8 99.04 97.35 11.2 10.6 25100 16 101.41 99.03 5.6 5.6 12.5101 32 103.5 100.76 2.8 2.8 6.25110 64 104.53 101.76 1.4 1.4 3.125111 Invalid — — — — —

In oversampling mode (see the Oversampling Mode of Operation section), the ADC takes the first sample foreach channel at the rising edge of the CONVSTA, CONVSTB signals. After converting the first sample, thesubsequent samples are taken by an internally generated sampling control signal. The samples are thenaveraged to reduce the noise of the signal chain as well as to improve the SNR of the ADC. The final output isalso decimated to provide a 18-bit output for each channel. Table 1 lists the typical SNR performance for boththe ±10-V and ±5-V input ranges, including the –3-dB bandwidth and proportional maximum throughput perchannel. When the oversampling ratio increases, there is a proportional improvement in the SNR performanceand decrease in the bandwidth of the input filter.

7.3.8 ReferenceThe ADS8598S can operate with either an internal voltage reference or an external voltage reference using aninternal gain amplifier. The internal or external reference selection is determined by an external REFSEL pin, asexplained in the REFSEL (Input) section. The REFIN/REFOUT pin outputs the internal band-gap voltage (ininternal reference mode) or functions as an input for the external reference voltage (in external reference mode).In both cases, the on-chip amplifier is always enabled. Use this internal amplifier to gain the reference voltageand drive the actual reference input of the internal ADC core for maximizing performance. The REFCAPA (pin45) and REFCAPB (pin 44) pins must be shorted together externally and a ceramic capacitor of 10 µF (minimum)must be connected between this node and REFGND (pin 43) to ensure that the internal reference buffer isoperating as closed loop. Place this capacitor as close as possible to the device to achieve rated performance.


REFIO Initial Acuuracy (mV)

Num

ber

of H

its

050

100150200250300350400450500550600650700

-2.5 -2.2 -1.6 -1 -0.4 0.2 0.8 1.4 2 2.5

D048

ADC

2.5-V VREF

REFCAPB

REFIN/REFOUT

AGND

10 PFREFGND

10 PF

REFSEL

AVDD

REFCAPA

DVDD

30




7.3.8.1 Internal ReferenceThe device has an internal 2.5-V (nominal value) band-gap reference. In order to select the internal reference,the REFSEL pin must be tied high or connected to DVDD. When the internal reference is used, REFIN/REFOUT(pin 42) becomes an output pin with the internal reference value. A 10-μF (minimum) decoupling capacitor, asshown in Figure 57, is recommended to be placed between the REFIN/REFOUT pin and REFGND (pin 43). Thecapacitor must be placed as close to the REFIN/REFOUT pin as possible. The output impedance of the internalband-gap creates a low-pass filter with this capacitor to band-limit the noise of the band-gap output. The use of asmaller capacitor increases the reference noise in the system, thus degrading SNR and SINAD performance. Donot use the REFIN/REFOUT pin to drive external ac or dc loads because of the limited current output capabilityof the pin. The REFIN/REFOUT pin can be used as a reference source if followed by a suitable op amp buffer.

Figure 57. Device Connections for Using an Internal 2.5-V Reference

The device internal reference is factory trimmed to a maximum initial accuracy of ±2.5 mV. The histogram inFigure 58 shows the distribution of the internal voltage reference output taken from more than 2100 devices.

Figure 58. Internal Reference Accuracy at Room Temperature Histogram

The initial accuracy specification for the internal reference can be degraded if the die is exposed to anymechanical, thermal, or environmental stress (such as humidity). Heating the device when being soldered to aprinted circuit board (PCB) and any subsequent solder reflow is a primary cause for shifts in the VREF value. Themain cause of thermal hysteresis is a change in die stress and therefore is a function of the package, die-attachmaterial, and molding compound, as well as the layout of the device itself.



RE

FIO

Vol

tage

(V

)

-40 -7 26 59 92 1252.495

2.497

2.499

2.501

2.503

2.505

D049

AVDD = 4.75 VAVDD = 5 VAVDD = 5.25 V

0

5

10

15

20

25

30

-4 -3 -2 -1 0 1

Num

ber

of D

evic

es

Error in REFIO Voltage (mV) C065

31




In order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the suggestedmanufacturer reflow profile, as explained in the AN-2029 Handling & Process Recommendations applicationreport. The internal voltage reference output is measured before and after the reflow process and Figure 59shows the typical shift in value. Although all tested units exhibit a positive shift in the output voltages, negativeshifts are also possible. The histogram in Figure 59 shows the typical shift for exposure to a single reflow profile.Exposure to multiple reflows, which is common on PCBs with surface-mount components on both sides, causesadditional shifts in the output voltage. If the PCB is to be exposed to multiple reflows, solder the ADS8598S inthe last pass to minimize device exposure to thermal stress.

Figure 59. Solder Heat Shift Distribution Histogram

The internal reference is also temperature compensated to provide excellent temperature drift over an extendedindustrial temperature range of –40°C to +125°C. Figure 60 shows the variation of the internal reference voltageacross temperature for different values of the AVDD supply voltage. The typical specified value of the referencevoltage drift over temperature is 7.5 ppm/°C.

Figure 60. Variation of Internal Reference Output (REFIN/REFOUT) vs Free-Air Temperature and Supply

7.3.8.2 External ReferenceFor applications that require a reference voltage with lower temperature drift or a common reference voltage formultiple devices, the ADS8598S offers a provision to use an external reference, using the internal buffer to drivethe ADC reference pin. In order to select the external reference mode, either tie the REFSEL pin low or connectthis pin to AGND. In this mode, an external 2.5-V reference must be applied at REFIN/REFOUT (pin 42), whichbecomes a high-impedance input pin. Any low-drift, small-size external reference can be used in this modebecause the internal buffer is optimally designed to handle the dynamic loading on the ADC reference input. Theoutput of the external reference must be filtered to minimize the resulting effect of the reference noise on systemperformance. Figure 61 illustrates a typical connection diagram for this mode.

http://www.ti.com/product/ads8598s?qgpn=ads8598shttp://www.ti.comhttp://www.ti.com/product/ads8598s?qgpn=ads8598shttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SBAS827&partnum=ADS8598Shttp://www.ti.com/lit/pdf/SNOA550


RE

FC

AP

Vol

tage

(V

)

-40 -7 26 59 92 1253.99

3.995

4

4.005

4.01

D051

AVDD = 4.75 VAVDD = 5 VAVDD = 5.25 V

REFCAP Drift (ppm/qC)

Num

ber

of h

its

0

1

2

3

4

5

6

7

8

0 0.665 1.325 1.985 2.645 3.305 4

D052

ADC

2.5-V VREF

REFCAPB

REFIN/REFOUT

AGND

10 PF

REFGND

CREF

REFSEL

AVDD

REF5025(Refer to Device

Datasheet for Detailed Pin Configuration)

AVDD

OUT

REFCAPA


32




Figure 61. Device Connections for Using an External 2.5-V Reference

For closed-loop operation of the internal reference buffer, the REFCAPA and REFCAPB pins must be externallyshorted together. The output of the internal reference buffer appears at the REFCAP pin. A minimumcapacitance of 10 µF must be placed between the REFCAPA, REFCAPB pins and REFGND (pin 43). Place thiscapacitor as close as possible to the REFCAPA and REFCAPB pins. Do not use this internal reference buffer todrive external ac or dc loads because of the limited current output capability.

Figure 62 shows that the performance of the internal buffer output is very stable across the entire operatingtemperature range of –40°C to +125°C. Figure 63 shows that the typical specified value of the reference bufferdrift over temperature is 5 ppm/°C.

Figure 62. Variation of Reference Buffer Output(REFCAPA, REFCAPB) vs Free-Air Temperature and

Supply

Number of samples = 30

Figure 63. Reference Buffer Temperature Drift Histogram

7.3.8.3 Supplying One VREF to Multiple DevicesFor applications that require multiple ADS8598S devices, using the same reference voltage source for all ADCshelps eliminate any potential errors in the system resulting from mismatch between multiple reference sources.

Figure 64 illustrates the recommended connection diagram for an application that uses one device in internalreference mode and provides the reference source for other devices. The device used as source of the voltagereference is bypassed by a 10-µF capacitor on the REFIN/REFOUT pin, whereas the other devices are bypassedwith a 100-nF capacitor.


REFSEL

REFIN / REFOUT

100 nF

ADS8598S

REFSEL

REFIN / REFOUT

100 nF

ADS8598S

REFSEL

REFIN / REFOUT

100 nF

ADS8598S

REFGND REFGND REFGND

CREF

REF5025(Refer to Device

Datasheet for Detailed Pin Configuration)

AVDD

OUT


REFSEL

DVDD

REFIN / REFOUT

10PF

ADS8598S

REFSEL

REFIN / REFOUT

100nF

ADS8598S

REFSEL

REFIN / REFOUT

100nF

ADS8598S

REFGND REFGND REFGND

Configured as Output Configured as Input Configured as Input

33




Figure 64. Multiple Devices Connected With an Internal Reference From one Device

Figure 65 shows the recommended connection diagram for an application that uses an external voltagereference (such as the REF5025) to provide the reference source for multiple devices.

Figure 65. Multiple Devices Connected Using an External Reference

7.3.9 ADC Transfer FunctionThe ADS8598S is a multichannel device that supports two single-ended, bipolar input ranges of ±10 V and ±5 Von all input channels. The device outputs 18 bits of conversion data in binary two's complement format for bothbipolar input ranges. The format for the output codes is the same across all analog channels.

Figure 66 depicts the ideal transfer characteristic for each ADC channel for all input ranges. The full-scale range(FSR) for each input signal is equal to the difference between the positive full-scale (PFS) input voltage and thenegative full-scale (NFS) input voltage. The LSB size is equal to FSR / 218 = FSR / 262144 because theresolution of the ADC is 18 bits. Table 2 lists the LSB values corresponding to the different input ranges.

http://www.ti.com/product/ads8598s?qgpn=ads8598shttp://www.ti.comhttp://www.ti.com/product/ads8598s?qgpn=ads8598shttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SBAS827&partnum=ADS8598Shttp://www.ti.com/product/REF5025

1000 «�«�0000(20000h)

0111 «�«�1111(1FFFFh)

0000 «�«�0000(00000h)

PFS ± 1.5LSB

0V-0.5LSBNFS+0.5LSB

AD

C O

utpu

t Cod

e

Analog Input (AIN_nP t AIN_nGND)

NFS PFS

FSR = PFS - NFS

34




Figure 66. 18-Bit ADC Transfer Function (Two's Complement Binary Format)

Table 2. ADC LSB Values for Different Input Ranges

INPUT RANGE (V) POSITIVE FULL-SCALE(V)NEGATIVE FULL-SCALE

(V) FULL-SCALE RANGE (V) LSB (µV)

±10 10 –10 20 76.295±5 5 –5 10 38.1475

7.3.10 ADS8598S Device Family ComparisonThe ADS8598S belongs to a family of pin-compatible devices. Table 3 lists the devices from this family alongwith their features.

Table 3. Device Family ComparisonPRODUCT RESOLUTION (Bits) CHANNELS SAMPLE RATE (kSPS)ADS8598H 18 8, single-ended 500ADS8588H 16 8, single-ended 500ADS8588S 16 8, single-ended 200ADS8586S 16 6, single-ended 250ADS8584S 16 4, single-ended 330ADS8578S 14 8, single-ended 200

http://www.ti.com/product/ads8598s?qgpn=ads8598shttp://www.ti.comhttp://www.ti.com/product/ads8598s?qgpn=ads8598shttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SBAS827&partnum=ADS8598Shttp://www.ti.com/product/ADS8598Hhttp://www.ti.com/product/ADS8588Hhttp://www.ti.com/product/ADS8588Shttp://www.ti.com/product/ADS8586Shttp://www.ti.com/product/ADS8584Shttp://www.ti.com/product/ADS8578S

35




7.4 Device Functional Modes

7.4.1 Device Interface: Pin Description

7.4.1.1 REFSEL (Input)The REFSEL pin is a digital input pin that enables selection between the internal and external reference mode ofoperation for the device. If the REFSEL pin is set to logic high, then the internal reference is enabled andselected. If this pin is set to logic low, then the internal band-gap reference circuit is disabled and powered down.In this mode, an extern