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PA workshop using ADS
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This document is owned by Agilent Technologies, but is no longer kept current and may contain obsolete or
inaccurate references. We regret any inconvenience this may cause. For the latest information on Agilent’s
line of EEsof electronic design automation (EDA) products and services, please go to:
www.agilent.com/fi nd/eesof
Agilent EEsof EDA
Power Amplifier Design using ADS
PA Workshop
Page 1
Wilfredo Rivas-Torres
Technical Support Application Engineer
October 12, 2004
Outline
• Introduction
• DC and Loadline analysis
• Bias and Stability
• LoadPull
• Matching using Smith Chart Utility
• SourcePull
ADS Power Amp DesignPage 2
• SourcePull
• PA Characterization – Did we meet the specification?
• Optimize/Fine Tune the design
• Test Design with real world modulated signals
• Layout
Why do we need a Power Amplifier?
Power Amplifiers (PA) are in the transmitting chain of a
wireless system. They are the final amplification stage before
the signal is transmitted, and therefore must produce enough
output power to overcome channel losses between the
transmitter and the receiver.
ADS Power Amp DesignPage 3
OSC
MODBaseband PADriver
Basic Transmitter
PA requirements
• The PA is typically the primary consumer of power in a transmitter. A major design requirement is how efficiently the PA can convert DC power to RF output power.
• The design engineer has to often concern himself with the Efficiency of the Power Amplifier. Notice that efficiency translates into either lower operation cost (e.g. cellular
ADS Power Amp DesignPage 4
translates into either lower operation cost (e.g. cellular basestation) or longer battery life (e.g. wireless handheld).
• PA linearity is another important requirement, the input/ output relationship must be linear to preserve the signal integrity.
• The design of PAs often involves the tradeoff of efficiency and linearity.
PA Design Requirement
• RF Output Power: 50 W PEP
• Input Drive Level : 1 W
• Output Load (RL): 50 Ω
• Efficiency (η) > 50%
ADS Power Amp DesignPage 5
• Efficiency (η) > 50%
• Bias Voltage: 28 V
• Device: MRF9045M
DC Curves
FET Curve Tracer
VJFSL_MRF_MET_MODEL
MRF1
MODEL=MRF9045M
V_DC
SRC1Vdc=VDS
V_DC
SRC2Vdc=VGS
VARVAR1
VGS =0 V
VDS =0 V
EqnVar
I_Probe
IDS
ADS Power Amp DesignPage 6
Set drain and gate voltagesweep limits as needed.
ParamSweep
Sweep1
Step=0.1
Stop=5.0
Start=2.5
SweepPlan="SwpPlan1"
PARAMETER SWEEP
DisplayTemplate
disptemp1
"FET_curve_tracer"
TempDisp
FSL_TECH_INCLUDE
FTI
FSL_TECH_INCLUDE
DC
DC1
Step=0.1
Stop=28*2
Start=0
SweepVar="VDS"
DC
DC Curves
1
2
3
4
5
IDS.i, A
VDsat IQ
Load_Line
ADS Power Amp DesignPage 7
5 10 15 20 25 30 35 40 45 50 550 60
1
0
VDS
VDsat IQ
m3
VDsatVDS=IDS.i=0.562VGS=3.800000
0.600IQVDS=IDS.i=0.717VGS=3.800000
28.000m3VDS=IDS.i=0.004VGS=2.500000
33.400
Bias and Stability
MRF9045M_AMP
X2
VD
sc_mrt_MC_GRM40C0G050_J_19960828
C25
PART_NUM=GRM40C0G330J050 33pF
Port
P3
Num=3
MLIN
TL20
L=100 mil
W=63.668898 mil
Subst="MSub1"
MLIN
TL21
L=100 mil
W=63.668898 mil
Subst="MSub1"
sc_mrt_MC_GRM40C0G050_D_19960828
C20
PART_NUM=GRM40C0G100D050 10pF
sc_spr_293D_A025_X9_19960828
C19
PART_NUM=293D474X9025A2 0.47uFMLIN
TL1
L=2194.444882 mil
W=63.670079 mil
Subst="MSub1"
sc_mrt_MC_GRM40C0G050_J_19960828
C8
PART_NUM=GRM40C0G330J050 33pF
sr_avx_CR_10_K_19960828
R13
PART_NUM=CR10-150K 15 Ohm
Port
P2
Num=2
ADS Power Amp DesignPage 8
VG VJ
sr_avx_CR_10_K_19960828
R12
PART_NUM=CR10-680K 68 Ohm
MSUB
MSub1
Rough=0 mil
TanD=0.002
T=2.8 mil
Hu=3.9e+034 mil
Cond=5.8E+08
Mur=1
Er=4.2
H=33.6 mil
MSub
FSL_MRF_MET_MODEL
MRF1
CTH=-1
RTH=-1
TSNK=25
MODEL=MRF9045M
sc_mrt_MC_GRM40C0G050_J_19960828
C17
PART_NUM=GRM40C0G330J050 33pF
MLIN
TL23
L=100 mil
W=63.668898 mil
Subst="MSub1"
MLIN
TL22
L=100 mil
W=63.668898 mil
Subst="MSub1"
sc_mrt_MC_GRM40C0G050_D_19960828
C23
PART_NUM=GRM40C0G100D050 10pF
sc_spr_293D_A025_X9_19960828
C24
PART_NUM=293D474X9025A2 0.47uF
Port
P4
Num=4
sc_mrt_MC_GRM40C0G050_J_19960828
C7
PART_NUM=GRM40C0G330J050 33pF
sc_mrt_MC_GRM40C0G050_J_19960828
C3
PART_NUM=GRM40C0G330J050 33pF
sl_tok_LL2012-F_J_19960828
L2
PART_NUM=LL2012-F82NJ 82 nH
Port
P1
Num=1
Stability Analysis
VDD
VGG
MRF9045M_AMP
X1
S-PARAMETERS FSL_TECH_INCLUDE
P_1Tone
PORT1
Freq=fss
P=polar(dbmtow (-60),0)
Z=50 Ohm
Num=1
Term
R3
Z=50 Ohm
Num=2
ADS Power Amp DesignPage 9
VGGVDD
S_Param
SP2
Step=1.0 MHz
Stop=3000 MHz
Start=1 MHzI_Probe
IDD
I_Probe
IGG
V_DC
SRC2
Vdc=VGS
V_DC
SRC1
Vdc=VDS
VAR
VAR3
VGS =3.8 V
VDS =28 V
EqnVar
FSL_TECH_INCLUDE
FTI
MuPrime
MuPrime1
MuPrime1=mu_prime(S)
MuPrime
Mu
Mu1
Mu1=mu(S)
Mu
StabMeas
StabMeas1
StabMeas1=stab_meas(S)
StabMeas
StabFact
StabFact1
StabFact1=stab_fact(S)
StabFact
Stability Analysis
1E2
1E3
1E4
3E4
StabFact1
ADS Power Amp DesignPage 10
0.5 1.0 1.5 2.0 2.50.0 3.0
1E1
1E2
1
freq, GHz
StabFact1
Impedance Matching
• The need for matching circuits is because amplifiers, in order to perform in a certain way(e.g. maximize output power), must be presented with a certain impedance at both the load and the source ports.
• For example in order to deliver maximum power to the load RL the transistor must have termination Zs and ZL.
ADS Power Amp DesignPage 11
transistor must have termination Zs and ZL.
• The input matching network is designed to transform the generator impedance Rs to the optimum source impedance Zs.
• The output matching network transform the load termination RL
(50 Ω) to the optimum load impedance ZL.
• A LoadPull measurement will help the designer determine the optimum load impedance ZL.
LoadPull Setup
v load
Vs_high
ParamSw eep
Sw eep2
PARAMETER SWEEP
HarmonicBalance
HB1
Order[1]=15
Freq[1]=RFfreq
HARMONIC BALANCE
P_1ToneMRF9045M_AMP
I_Probe
Iload
I_Probe
Is_high
S1P_Eqn
V_DC
SRC1
Vdc=Vhigh
ADS Power Amp DesignPage 12
Vs_low
Set these values:
Set Load and Source impedances atharmonic frequencies
VAR
Sw eepEquations
Z0=50
pts=100
s11_center =-0.6 +j*0.1
s11_rho =0.75
EqnVar
FSL_TECH_INCLUDE
FTI
FSL_TECH_INCLUDE
VAR
STIMULUS
Vlow =3.8
Vhigh=28.0
RFfreq=760 MHz
Pavs=30 _dBm
EqnVar
VAR
VAR2
Z_s_5 =Z0 + j*0
Z_s_4 = Z0 + j*0
Z_s_3 = Z0 + j*0
Z_s_2 = Z0 + j*0
Z_s_fund =1.0 + j*0
Z_l_5 = Z0 + j*0Z_l_4 = Z0 + j*0
Z_l_3 = Z0 + j*0
Z_l_2 =Z0 + j*0
EqnVar
P_1Tone
PORT1
Freq=RFfreq
P=dbmtow (Pavs)
Z=Z_s
Num=1
I_Probe
Is_low
V_DC
SRC2
Vdc=Vlow
MRF9045M_AMP
X2
S1P_Eqn
S1
S[1,1]=LoadTuner
Z[1]=Z0
Examples
Search
LoadPull Contours
m2indep(m2)=Pdel_contours_p=0.914 / 171.170level=44.195857, number=1impedance = 2.265 + j3.852
6
Pdel_contours_p
PAE_contours_p
ADS Power Amp DesignPage 13
m1indep(m1)=PAE_contours_p=0.914 / 171.180level=47.552308, number=1impedance = 2.265 + j3.848
6
indep(Pdel_contours_p) (0.000 to 46.000)
Pdel_contours_p
indep(PAE_contours_p) (0.000 to 18.000)
PAE_contours_p
Matching using Smith Chart Utility
ADS Power Amp DesignPage 14
Matching using Smith Chart Utility
ADS Power Amp DesignPage 15
Output Match
Port
P2
Num=2
Port
P1
Num=1
C
C3
C=27.689016 pF
C
C2
C=2.307137 pF
TLIN
TL3
F=760 MHz
E=25.92
Z=22.85 Ohm
TLIN
TL2
F=760 MHz
E=32.25
Z=50 Ohm
TLIN
TL1
F=760 MHz
E=8.891
Z=50 Ohm
C
C1
C=12.975203 pF
ADS Power Amp DesignPage 16
DA_SmithChartMatch1_output_match_design
DA_SmithChartMatch1
Z0=50 Ohm
Zl=(2.300-j*3.800) Ohm
Zs=50 Ohm
F=760 MHz
SourcePull ContoursPAE_contours_p
Pdel_contours_p
m2indep(m2)=Pdel_contours_p=0.960 / 174.023level=46.038749, number=1impedance = 1.016 + j2.609
4
ADS Power Amp DesignPage 17
indep(PAE_contours_p) (0.000 to 77.000)
PAE_contours_p
indep(Pdel_contours_p) (0.000 to 66.000)
Pdel_contours_p
m1indep(m1)=PAE_contours_p=-0.952 + j0.100level=58.130703, number=1impedance = 1.096 + j2.618
4
Matching Circuits
PortP1
Num=1
MLIN
TL7
L=596.716535 mil
W=199.971654 mil
Subst="MSub1"
MLIN
TL8
L=786.342520 mil
W=63.670079 mil
Subst="MSub1"
MLIN
TL9
L=216.786614 mil
W=63.670079 mil
Subst="MSub1"
sc_mrt_MC_GRM40C0G050_D_19960828
C28PART_NUM=GRM40C0G090D050 9pF
Port
P2Num=2
sc_mrt_MC_GRM40C0G050_J_19960828
C22PART_NUM=GRM40C0G150J050 15pF
sc_mrt_MC_GRM40C0G050_C_19960828
C21PART_NUM=GRM40C0G020C050 2pF
Output Match
ADS Power Amp DesignPage 18
sc_mrt_MC_GRM40C0G050_J_19960828
C26
PART_NUM=GRM40C0G220J050 22pF
sc_mrt_MC_GRM40C0G050_C_19960828
C25
PART_NUM=GRM40C0G020C050 2pF
MLIN
TL18
L=802.433071 mil
W=63.670079 mil
Subst="MSub1"
MLIN
TL17
L=414.385827 mil
W=199.971654 mil
Subst="MSub1"
Port
P2
Num=2
MLIN
TL16
L=205.546063 mil
W=63.670079 mil
Subst="MSub1"
Port
P1
Num=1
sc_mrt_MC_GRM40C0G050_D_19960828
C24
PART_NUM=GRM40C0G090D050 9pF
Input Match
Complete Design Power Sweep
Vin
Vloadinput_match output_match
V_DC
SRC1
Vdc=VDS
I_Probe
Iload
I_Probe
Iin
ADS Power Amp DesignPage 19
Vloadinput_match
X5 MRF9045M_AMP
X4
output_match
X3
Iload
R
R1
R=50 OhmVAR
VAR1
Pin=30
VGS =3.8 V
VDS =28 V
EqnVarVAR
VAR2
fo=760.0 MHz
EqnVar
FSL_TECH_INCLUDE
FTI
FSL_TECH_INCLUDEHarmonicBalance
HB1
Step=1
Stop=40
Start=-30
SweepVar="Pin"
Order[1]=15
Freq[1]=fo
HARMONIC BALANCE
P_1Tone
PORT1
Vdc=
Freq=fo
P=dbmtow(Pin)
Z=50.0 OhmNum=1
Iin
V_DCSRC2
Vdc=VGS
Power Compression Curve
40
60
Pdel_dBm
Output
OutputPin=Pdel_dBm=45.570
30.000
ADS Power Amp DesignPage 20
-20 -10 0 10 20 30-30 40
0
20
-20
Pin
Pdel_dBm
Gain Compression Curve
14
16
18
GainComp
LinearGain
GainCompind Delta=dep Delta=-1.771 delta mode ON
60.00 LinearGainPin=Gp=17.341
-30.000
ADS Power Amp DesignPage 21
-20 -10 0 10 20 30-30 40
8
10
12
14
6
Pin
Gp
Power Added Efficiency
30
40
50
60
PAE
m1 m1Pin=PAE=49.618
30.000
ADS Power Amp DesignPage 22
-20 -10 0 10 20 30-30 40
10
20
0
Pin
Getting ready to Optimize the PA
• The next step is to optimize the design to meet the requirements.
• The Designer can take the opportunity to see if other requirements, such
as layout will require any changes before proceeding to optimize.
• Example: we notice that the transistor pads are rather wide and the Tlines
leading up to it are not the same width.
• Since the Tlines are much narrower, we could add a taper so we have a
nice transition.
ADS Power Amp DesignPage 23
nice transition.
• We included a MTAPER at the input and output side
dBm(Vload[1])
41.549
MTAPER
Taper2
L=100.0 mil
W2=63.670079 mil
W1=199.971654 mil
Subst="MSub1"
Optimization Setup
Goal
Goal2
Weight=
Max=-40
Min=
SimInstanceName="HB1"
Expr="dBm(Vload[2])-dBm(Vload[1])"
GOAL
Goal
Goal1
Weight=
Max=
Min=47.0
SimInstanceName="HB1"
Expr="dBm(Vload[1])"
GOAL
Optim
Optim1
NormalizeGoals=no
FinalAnalysis="None"
DesiredError=0.0
MaxIters=25
OptimType=Gradient
OPTIM
ADS Power Amp DesignPage 24
RangeMax[1]=
RangeMin[1]=
RangeVar[1]=
Weight=
RangeMax[1]=
RangeMin[1]=
RangeVar[1]=
Weight=
SaveCurrentEF=no
UseAllGoals=yes
UseAllOptVars=yes
SaveAllIterations=no
SaveNominal=no
UpdateDataset=yes
SaveOptimVars=no
SaveGoals=yes
SaveSolns=yes
SetBestValues=yes
NormalizeGoals=no
Optimization Results
InitialEF
67.187
FinalEF
0.000
optIter Goal1 Goal2
ADS Power Amp DesignPage 25
10 47.003 -40.017
MLIN
TL39
L=2194.444882 mil opt 250 mil to 3500 mil
W=63.670079 mil
Subst="MSub1"
MLIN
T L39
L=551 .591 m il op t 250 m il to 3500 m il
W =63 .670079 m il
Subs t= "MSub1"
Before After
Optimization Values
TL39.L*1e5/2.54
551.591
TL15.L*1e5/2.54
247.144
TL30.L*1e5/2.54
814.900
TL7.L*1e5/2.54
320.449
TL8.L*1e5/2.54
622.341
ADS Power Amp DesignPage 26
TL10.L*1e5/2.54
244.711
TL31.L*1e5/2.54
202.643
TL32.L*1e5/2.54
184.709
TL9.L*1e5/2.54
248.635
PA Results
20
40
60
Pdel_dBm
m1 m1Pin=Pdel_dBm=47.003
30.000
ADS Power Amp DesignPage 27
-20 -10 0 10 20 30-30 40
0
-20
Pin
Pdel_dBm
Power Added Efficiency
40
60
80
PAE
m3
m3Pin=PAE=56.736
30.000
ADS Power Amp DesignPage 28
-20 -10 0 10 20 30-30 40
20
0
Pin
Gain Compression Curve
-6
-4
-2
0
Gp-Gp[0]
m4m4Pin=Gp-Gp[0]=-0.728
30.000
ADS Power Amp DesignPage 29
-20 -10 0 10 20 30-30 40
-8
-10
Pin
Gp-Gp[0]
Complex Modulated Signal
-40
-20
0
20
40
16 QAM Spectrum (dBm)
ADS Power Amp DesignPage 30
759.75 760.00 760.25759.50 760.50
-80
-60
-40
-100
Frequency (MHz)
16 QAM Spectrum (dBm)
16 QAM Modulated Source
LPF_RaisedCosineTimed
L4
Delay=16/bit_rate
SquareRoot=Yes
Type=Model w ith pulse equalization
ExcessBw=0.5
CornerFreq=bit_rate/8
Loss=0.0SymbolConverter
S3
CodeOut=pam4Out
CodeIn=nrzIn
Delay=0 sec
SymbolTime=2/bit_rate
ADS Power Amp DesignPage 31
SpectrumAnalyzer
S9
WindowConstant=0.0
Window=none
Stop=DefaultTimeStop
Start=DefaultTimeStart
RLoad=DefaultRLoad
Plot=None
QAM_Mod
Q1
PhaseImbalance=0
GainImbalance=0
Phase=0
VRef=1.0 V
Pow er=Pc
FCarrier=Fc
SymbolConverter
S4
CodeOut=pam4Out
CodeIn=nrzIn
Delay=0 sec
SymbolTime=2/bit_rate
LPF_RaisedCosineTimed
L5
Delay=16/bit_rate
SquareRoot=Yes
Type=Model w ith pulse equalization
ExcessBw=0.5
CornerFreq=bit_rate/8
Loss=0.0
Data
D1
Repeat=Yes
SequencePattern=23
Type=Prbs
UserPattern=""
BitTime=1/bit_rate
TStep=Tstep
SymbolSplitter
S1
Delay=-1
SymbolTime=1/bit_rate
DSP and Analog Circuits Setup
• Create a subcircuit with your analog design.
• You need to add either Circuit Envelope or Transient controller to the analog circuit.
• We use Circuit Envelope specifically with our PA since we have a Modulated Carrier.
• Circuit Envelope will also allow the use of Fast Cosim (Automatic
ADS Power Amp DesignPage 32
• Circuit Envelope will also allow the use of Fast Cosim (Automatic Verification Modeling – AVM). This will dramatically increase the simulation speed.
• In the DSP schematic we will create the Modulated Carrier, feed it to the PA and collect the signal samples and spectrum.
• The DSP schematic contains a Envelope Output Selector component used for interfacing between circuit subnetwork output and the signal processing components.
TimedSink
RF_in
Stop=DefaultT imeStop
Start=DefaultT imeStartPlot=Rectangular
TimedSink
Qout
ControlSimulation=YESStop=DefaultT imeStop
Start=DefaultT imeStartPlot=Rectangular
SpectrumAnalyzer
S9
WindowConstant=0.0
Window=noneStop=DefaultT imeStopStart=DefaultT imeStart
RLoad=DefaultRLoadPlot=None
Ptolemy Cosim Schematic
PA
ADS Power Amp DesignPage 33
TimedSink
RF_out
ControlSimulation=YESStop=DefaultT imeStop
Start=DefaultT imeStartPlot=Rectangular
MRF9045M_AMP_CE2
X1
SplitterRF
S10
ControlSimulation=YESStop=DefaultT imeStop
EnvOutShort
O1OutFreq=Fc
TimedSink
Iout
ControlSimulation=YESStop=DefaultT imeStop
Start=DefaultT imeStartPlot=Rectangular
MatchedLoss
M1Loss=17.0
SplitterRF
S7
PhaseShiftRF
P1PhaseShift=360-168
QAM_Demod
Q2
PhaseImbalance=0.0GainImbalance=0.0Phase=0.0
Sensitivity=0.1*(10**((25-Pow)/20))RefFreq=Fc
QAM_src
X2Pc=Pow
SpectrumAnalyzer
S8
WindowConstant=0.0
Window=noneStop=DefaultT imeStopStart=DefaultT imeStart
RLoad=DefaultRLoadPlot=None
QAM Source
Fast Cosim Improvements
Simulation Time Benchmark:
Total bits: 1024 bits
AVM disabled : 410 sec
AVM enabled: 13 sec
AVM data reuse: 5.5 sec
--------------
AVM data reuse (16 Kbits): 17.5 sec
ADS Power Amp DesignPage 34
--------------
AVM data reuse (16 Kbits): 17.5 sec
Cosimulation Results - Spectrum
-60
-40
-20
0
20
-60
-40
-20
0
20
Carrier Power
30 dBm
Carrier Power
25 dBm
ADS Power Amp DesignPage 35
759.5 760.0 760.5759.0 761.0
-80
-60
-100
freq, MHz
759.5 760.0 760.5759.0 761.0
-80
-100
freq, MHz
Cosimulation Results - Constellation
0.0
0.5
1.0
1.5
0.0
0.5
1.0
1.5
Carrier Power
30 dBm
Carrier Power
25 dBm
ADS Power Amp DesignPage 36
-1.0 -0.5 0.0 0.5 1.0-1.5 1.5
-1.0
-0.5
0.0
-1.5
-1.0 -0.5 0.0 0.5 1.0-1.5 1.5
-1.0
-0.5
0.0
-1.5
Cosimulation Results
peakP_out
47.969
peak_avg_out
3.516
avgPout
44.453
Carrier Power
30 dBm
peakP_in
32.163
peak_avg_in
4.951
avgPin
27.212
ADS Power Amp DesignPage 37
Carrier Power
25 dBm
peakP_in
30.000
peak_avg_in
7.788
avgPin
22.212
peakP_out
44.715
peak_avg_out
4.832
avgPout
39.883
Cosimulation Results – CCDF
1E-2
1E-1
9E-1
1E-2
1E-1
9E-1
Carrier Power
30 dBm
Carrier Power
25 dBm
ADS Power Amp DesignPage 38
-6 -4 -2 0 2 4-8 6
1E-4
1E-3
1E-2
1E-5
dB
-6 -4 -2 0 2 4-8 6
1E-4
1E-3
1E-2
1E-5
dB
EVM vs. Power Measurement
VAR
VAR3
Pow=30 _dBm
Fc=760 MHz
Tstop=num_bits/bit_rate
Tstep=1/(bit_rate*oversample)
EqnVar VAR
VAR2
num_bits=4096*4
oversample=4
bit_rate=1.0 MHz
EqnVar
EVM_WithRef
Ref
tes t EVM Ref
RES
R2
R=50 Ohm
ADS Power Amp DesignPage 39
ParamSweep
Sweep1
Step=1
Stop=30
Start=18
SimInstanceName[6]=
SimInstanceName[5]=
SimInstanceName[4]=
SimInstanceName[3]=
SimInstanceName[2]=
SimInstanceName[1]="DF1"
SweepVar="Pow"
PARAMETER SWEEP
DF
DF1
SavedEquationName[1]="Tstep"
DefaultTimeStop=Tstop
DefaultTimeStart=0
DefaultNumericStop=100
DefaultNumericStart=0
QAM_src
X2
Pc=Pow
EVM_WithRef
E2
SymbolRate=0.25 MHz
MeasType=EVM_rms
NumBursts=2
SymDelayBound=-1
SampPerSym=16
SymBurstLen=1024
StartSym=10
RES
R1
R=50 Ohm
EnvOutShort
O1
OutFreq=Fc
MRF9045M_AMP_CE2
X1
SplitterRF
S7
EVM vs. Power Results
3
4
5
EVM (%)
EVM vs. Carrier Power
ADS Power Amp DesignPage 40
20 22 24 26 2818 30
1
2
0
Power (dBm)
EVM (%)
ADS to VSA link
VARVarFSL_TECH_INCLUDE
FSL_TECH_INCLUDE
RES
R1
R=50 Ohm
VSA_89600_1_Sink
V1
SetFreqProp=YES
RestoreHW=NO
SetupFile="C:\Program Files\Agilent\89600 VSA\Vector\User\PA_demod.set"
SamplesPerSymbol=16
TStep=Tstep
VSATitle="Simulation output"
VSA
QAM_src
X2
Pc=Pow
EnvOutShort
O1
OutFreq=Fc
MRF9045M_AMP_CE2
X1
ADS Power Amp DesignPage 41
VAR
VAR3
Pow=30 _dBm
Fc=760 MHz
Tstop=num_bits/bit_rate
Tstep=1/(bit_rate*oversample)
EqnVar
VAR
VAR2
num_bits=1024*16
oversample=4
bit_rate=1.0 MHz
EqnVar
FSL_TECH_INCLUDE
FTI
DF
DF1
SavedEquationName[1]="Tstep"
DefaultTimeStop=Tstop
DefaultTimeStart=0
DefaultNumericStop=100
DefaultNumericStart=0
VSA Spectrum from ADS Cosim
ADS Power Amp DesignPage 42
VSA Constellation from ADS Cosim
Carrier Power
30 dBm
ADS Power Amp DesignPage 43
VSA Constellation from ADS Cosim
Carrier Power
30 dBm
ADS Power Amp DesignPage 44
VSA EVM from ADS Cosim
Carrier Power
30 dBm
ADS Power Amp DesignPage 45
PA Layout
sc_mr t _MC_G RM40C0G 050_J_19960828
C17
PART_NUM=GRM40C0G 330J050 33pF
Por t
P2
Num=2
sr _avx_CR_10_K_19960828
R13
PART_NUM=CR10- 150K 15 O hm
MTAPER
Taper 1
L=100. 0 m il
W2=63. 670079 m il
W1=199. 971654 m il
Subst =" MSub1"
MTAPER
Taper 2
L=100. 0 m il
W2=63. 670079 m il
W1=199. 971654 m il
Subst ="MSub1"
sc_mr t _MC_GRM40C0G 050_D_19960828
C26
PART_NUM =GRM40C0G 090D050 9pF
sc_m r t _MC_G RM40C0G 050_J_19960828
C24
PART_NUM=GRM 40C0G 150J050 15pF
MLI N
TL30
L=814. 898 m il opt 250 m il t o 1000 m il
W=63. 670079 m il
Subst ="MSub1"
MLI N
TL8
L=622. 343 m il opt 100 m il t o 750 m il
W=63. 670079 m il
Subst ="M Sub1"
MLI N
TL15
L=247. 144 m il opt 50 m il t o 500 m il
W=63. 670079 m il
Subst ="MSub1"
MLI N
TL32
L=184. 709 m il opt 100 m il t o 500 m il
W=63. 670079 m il
Subst ="M Sub1"
MLI N
TL31
L=202. 643 m il opt 75 m il t o 750 m il
W=199. 971654 m il
Subst ="MSub1"
MLI N
TL7
L=320. 449 m il opt 75 m il t o 500 m il
W=199. 971654 m il
Subst ="MSub1"
MLI N
TL9
L=248. 635 m il opt 75 m il t o 500 m il
W=63. 670079 m il
Subst ="M Sub1"
MLI N
TL10
L=244. 711 m il opt 50 m il t o 500 m il
W=63. 670079 m il
Subst ="M Sub1"
MTEE_ADS
Tee1
W3=63. 668898 m il
W2=199. 971654 m il
W1=199. 971654 m il
Subst ="M Sub1"
M TEE_ADS
Tee2
W3=63. 670079 m il
W2=199. 971654 m il
W1=199. 971654 m il
Subst ="MSub1"
MLI N
TL39
L=551. 591 m il opt 250 m il t o 3500 m il
W=63. 670079 m il
Subst ="MSub1"
sc_mr t _MC_GRM40C0G 050_C_19960828
C25
PART_NUM=G RM40C0G 020C050 2pF
MLI N
TL41
L=253. 4234 m il
W=63. 6689 m il
Subst ="MSUB1"
M CURVE2
Cur ve2
Nmode=2
Radius=100. 0 m il
Angle=90
W=63. 668898 m il
Subst ="MSub1"
sc_mr t _M C_GRM40C0G 050_D_19960828
C20
PART_NUM=GRM40C0G 100D050 10pF
M LI N
TL42
L=440 m il
W=63. 668898 m il
Subst ="MSub1"
sc_spr _293D_A025_X9_19960828
C19
PART_NUM=293D474X9025A2 0. 47uF
Por t
P3
Num =3
MLI N
TL20
L=225 m il
W=63. 668898 m il
Subst ="MSub1"
MLI N
TL21
L=200 m il
W=63. 668898 m il
Subst ="M Sub1"
ADS Power Amp DesignPage 46
sc_mr t _MC_GRM 40C0G 050_J_19960828
C18
PART_NUM=GRM40C0G 220J050 22pF
MRF9045_ar t
Q 1
Por t
P1
Num=1
sc_mr t _MC_GRM40C0G 050_J_19960828
C3
PART_NUM=G RM40C0G 330J050 33pF sr _avx_CR_10_K_19960828
R12
PART_NUM =CR10- 150K 15 O hm
L=100. 0 m il
sc_mr t _MC_GRM40C0G 050_C_19960828
C28
PART_NUM =GRM40C0G 020C050 2pF
sc_mr t _MC_GRM 40C0G 050_D_19960828
C27
PART_NUM=GRM40C0G 090D050 9pF
L=814. 898 m il opt 250 m il t o 1000 m il L=247. 144 m il opt 50 m il t o 500 m il L=184. 709 m il opt 100 m il t o 500 m il L=202. 643 m il opt 75 m il t o 750 m il W3=63. 668898 m il
MSUB
MSub1
Rough=0 m il
TanD=0. 002
T=2. 8 m il
Hu=3. 9e+034 m il
Cond=5. 8E+08
Mur =1
Er =4. 2
H=33. 6 m il
MSub
SMT_Pad
Pad2
PO =0 m il
SM_Layer ="solder _m ask"
SMO =5. 0 m il
PadLayer =" cond"
L=40. 0 m il
W=70. 0 m il
SMT_Pad
SMT_Pad
Pad1
PO =0 m il
SM_Layer ="solder _m ask"
SMO =5. 0 m il
PadLayer ="cond"
L=40. 0 m il
W=50. 0 m il
SMT_Pad
SMT_Pad
Pad3
PO =0 m il
SM_Layer ="solder _m ask"
SMO =5. 0 m il
PadLayer ="cond"
L=30. 0 m il
W=30. 0 m il
SMT_Pad
sl_t ok_LL2012-F_J_19960828
L2
PART_NUM =LL2012-F82NJ 82 nH
MLI N
TL43
L=90 m il
W=40 m il
Subst ="M SUB1"
MLI N
TL22
L=200 m il
W=63. 668898 m il
Subst =" MSub1"
MLI N
TL23
L=350 m il
W=63. 668898 m il
Subst =" MSub1"
Por t
P4
Num=4
MLI N
TL40
L=200 m il
W=63. 668898 m il
Subst ="M Sub1"
sc_spr _293D_A025_X9_19960828
C23
PART_NUM=293D474X9025A2 0. 47uF
sc_mr t _MC_GRM40C0G 050_D_19960828
C22
PART_NUM =GRM40C0G 100D050 10pF
MCURVE2
Cur ve1
Nmode=2
Radius=100. 0 m il
Angle=90
W=63. 668898 m il
Subst ="MSub1"
sc_mr t _MC_G RM40C0G 050_J_19960828
C21
PART_NUM=GRM40C0G 330J050 33pF
MLI N
TL1
L=100 m il
W=63. 668898 m il
Subst ="M SUB1"
MLI N
TL44
L=315. 0248 m il
W=63. 668898 m il
Subst ="M SUB1"
PA Layout – Generated from Schematic
ADS Power Amp DesignPage 47
PA Layout – Ground Fill
ADS Power Amp DesignPage 48
Other Possibilities
• Run an EM Cosimulation – include layout effects in the simulation.
Optimize design if necessary.
• Run Loadpull for IP3 or ACPR. The optimum load would then be a
compromise between all the requirements.
• Use Connection Manager and real PA to validate design and compare
ADS Power Amp DesignPage 49
• Use Connection Manager and real PA to validate design and compare
vs. simulated results.
• Create a behavioral data model that can be used to protect you IP yet
give access to your design results.
If there is any topic about PA Design and ADS you wish to
discuss email me: [email protected]
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