ADMOL, Dresden, Germany February 2004 1 Konstantin Likharev Stony Brook University Acknowledgments: W. Chen, E. Cimpoiasu, S. Fölling J. Lee, X. Liu, J

1ADMOL, Dresden, Germany February 2004

Konstantin LikharevStony Brook University

Acknowledgments: W. Chen, E. Cimpoiasu, S. Fölling

J. Lee, X. Liu, J. Lukens, X. Ma, A. Mayr, I. Muckra, Ö. Türel

Discussions: P. Adams, J. Barhen, L. Chua T. Ishii, V. Protopopescu, T. Sejnowski

Support: DOE, NSF

References: - K. L., “Electronics Below 10 nm”, in Giga and Nano Challenges in Microelectronics (Elsevier, Amsterdam, 2003), pp. 27-68- Ö. Türel et al., “Nanoelectronic Neuromorphic Networks: New Results”,

http://rsfq1.physics.sunysb.edu/~likharev/nano/Budapest.pdf

CMOL: Devices, Circuits, and ArchitecturesCMOL: Devices, Circuits, and Architectures


CMOS TECHNOLOGY

Pentium 4 processor:

• 42 million transistors

• 0.13 m design rules

• > 3 GHz clock frequency

DRAM memories:

4 Gb chips demonstrated

(~ 109 transistors/cm2)


VOLTAGE GAIN

(!)

V. Sverdlov, T. Walls, and KKL, IEEE T-ED 50, 1926 (2003)


PROBLEM: FAB SENSITIVITY

ND = 31020 cm-3

~0.4nm

50 mV

V. Sverdlov, T. Walls, and KKL, IEEE T-ED 50, 1926 (2003)


ULTIMATE CMOS PROSPECTSRANGE

Pessimistic Optimistic

Minimum half-pitch: 45 nm 20 nm

(Yr. 2010) (Yr. 2016)Transistor density:

5109 cm-2 31010 cm-2

5-transistor device density: 1109 cm-2 6109 cm-2


CORTICAL CIRCUITRY

Brain:

~ 21010 neural cells

~ few1014 synapses

Areal density: Cells: ~ 1.5107 cm-2

Synapses: ~ 1.01011 cm-2 axon

dendrite

synapse

Each synapse is an “active device”!


TRANSISTORS: SET vs FET

gate

drainsource

Choice: G e2/

FET SET

G G


SINGLE-ELECTRON TRANSISTOR

Averin and Likharev, 1985 (theory)

Fulton and Dolan, 1987 (experiment)

source drain

islandC1

C2

C0

Vg

V

gate

-2 -1 0 1 2-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Vt (for Q

0 = 0)

Qe = 0

Qe = e/2

C1 = C

2 = C/2

R1 = R

2 = R/2

kBT = 0.01 e

2/C

-2 -1 0 1 2-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

-2 -1 0 1 2-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

-2 -1 0 1 2-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

-2 -1 0 1 2-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Cur

rent

I (e

/RC

)

-2 -1 0 1 2-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Source-drain Voltage V (e/C)

(b)


0.1 1 10 100 100010

-19

10-18

10-17

10-16

10-15

C

Isla

nd

Ca

paci

tan

ce (

F)

Island Diameter (nm)

0.1 1 10 100 10001E-3

0.01

0.1

1

10

Ec

En

erg

y (e

V)


0.1 1 10 100 10001E-3

0.01

0.1

1

10

Ek

En

erg

y (e

V)


0.1 1 10 100 10001E-3

0.01

0.1

1

10

Ea

En

erg

y (e

V)


SET PROBLEM #1: FABRICATION

kB300 K

Ec 102 kBT


SINGLE-ELECTRON SINGLE-MOLECULE TRANSISTORS

see also:

- E. S. Soldatov et al. JETP Lett. 64, 556 (1996)

- H. Park et al. Nature 407, 57 (2000)

- N. Zhitenev, H. Meng, and Z. Bao PRB 88, 226801 (2002)

J. Park et al. Nature 417, 722 (2002)


1

-ne

VS VD

2

single-electron transistor

C0

single-electron trap-0.1 0.0 0.1 0.2 0.3

-0.1

0.0

0.1

0.2

0.3

Curr

en

t (e

/RC

)

Voltage (e/C)

Cc/C = 2C0/C = 1Q1 = -0.425eQ2 = -0.2ekBT/(e2/C) = 0.001

n = 0

n = 1

Vinj

S. Fölling, Ö. Türel, and K.L., 2001

“quasi-fuzzy”dynamics: dp/dt = (1-p) -p,

= 0 exp{e(V-S)/kBTef},

Cc

SINGLE-ELECTRON LATCHING SWITCH


P. Dresselhaus et al., 1994

Al/AlOx/Al structure stored an electron for > 12 hrs (at T < 1 K)

SINGLE-ELECTRON LATCHING SWITCH:

low-T prototype


SINGLE-ELECTRON LATCHING SWITCH:

possible molecular implementation

N

O

O

N

O

O

R

NN

O

O

O

O

R

R

N

R

C

R

R

N

R

R

C

O

R

N

R

C

R

R

O O

O

R = hexyl

naphthalenediimide group as a transistor

perylenediimide group as a trap

Courtesy A. Mayr (SBU/Chemistry)

(C6H13-)


CMOL CONCEPT

CMOSstack

CMOSwiringand

plugs

goldnanowire

levels(nanoimprint)

MOSFET

self-assembledmolecular devices

I/O pin

Si wafer


- memories (both embedded and stand-alone)

CMOL: POSSIBLE APPLICATIONS


TOWARD CMOL-TYPE MEMORIES

J. Heath and M. Ratner, Phys. Today, May 2003

(picture F. Krausz, HPL)

Y. Chen et al. APL 82, 1610 (2003)


- memories (both embedded and stand-alone)

- Boolean logic (??)

- neuromorphic circuits (“CrossNets”)

CMOL: POSSIBLE APPLICATIONS


CROSSNET: GENERAL STRUCTURE(feedforward option)

somaj

somak

jk+

jk-

+

+-

-

wjk = {-1, 0, +1}


CROSSNET SPECIES

x = y = const = M = 1/tan2x = y = Mx = y = const = M

FlossBar RandBar InBar

Maximum Connectivity: 4M (for RandBar, on the average)


Synapse footprint (33 switches per synapse):

As = 2(8F8F)2 for F = 2 nm: As ~ 500 nm2

Synapse density: ~ 21011 cm-2 (@ 61012 cm-2 bits/cm2)

Neural cell density (recurrent network, connectivity 104):

~5107 cm-2 (cf. 1.5107 cm-2 in bio)

Speed (intercell latency): ~ 20 ns @ 100 W/cm2 (R ~ 1010 )

or: ~ 2,000 ns @ 1 W/cm2 (R ~ 1012 )

(cf. ~10 ms in bio)

Performance (for 100 W/cm2):

~ 31012 cm-2 / 20 ns ~ 1020 ops/cm2-s

(cf. ~1016 bits/cm2-s for Prescott)

CROSSNETS: ULTIMATE PERFORMANCE ESTIMATE


- binary synaptic weight (for single device)

- randomness (“fuzziness”) of switching

- synaptic weight adjustment• two-terminal devices,• access via 2 nanowires (+ global back gate)

CROSSNET TRAINING CHALLENGES

dp/dt = (1-p) -p, = 0 exp{e(V-S)/kBTef},


“GRAY CELL” (SOMA)(fire-rate model, feedforward network)

effective linear gain:g = GRL/R

Training mode: Working mode:

+

-

G

RL

from external tutor

+-


WEIGHT IMPORTINTO RECURRENT INBAR

operation mode:

+-

+-

rowselect/unselect

(i) column select/unselect(ii) data to write

semi-selected

fullyselected

semi-selected

un-selected

un-selected


HOPFIELD-MODE IMAGE RECOGNITION: DYNAMICS

original B/W image

(1 of 3 taught)

random 40% bits flipped(t = 0)

t/0 = 1 2 3 4 5

where 0 MRLC0


HOPFIELD-MODE OPERATION:DEFECT TOLERANCE

InBar CrossNetN = 1664M = 25g/gt = 5

99% fidelity @ 85% bad

devices!


FEEDFORWARD NETWORKS:SYNAPSE DISCRETENESS EFFECT

O. Turel et al., 2004

100 cells per layer

averaged over 100 random weight vectors

>98% fidelity at L = 37


MULTI-VALUED SYNAPSES

Training mode: Working mode:

Iout = (Vj /R)iniNumber of levels: L = 2n2+1

V0xj

V0xj

Vd V0

RL

(V0)j +Vs

(V0)j +Vs

(V0)j

(V0)k


CROSSNET SYSTEM HIERARCHY

I/O SYSTEMSENSOR/

ACTUATOR SYSTEM

WORLD

TUTOR

HIGH SPEED BUS SYSTEM

SOMA SOMA SOMA

“flat”CrossNet

array

Self-evolution possible ?


CONCLUSIONS

CMOS: - approaching the end of Moore’s Law

CMOL: - the future of microelectronics?

CrossNets:- natural for CMOL

- ultimately high density @ high speed

- “quasi-fuzzy” (controlled randomness)

- may reproduce: Hopfield networks, feedforward perceptrons

- suitable for globally reinforced training ?

- (promise of) self-evolution ?


THANK YOU!THANK YOU!

Suggestions/comments to:

[email protected]


CANDIDATE MOLECULES FOR SELF-ASSEMBLING SET

oligo(phenyleneethynylene) wirediimide groupthiol group

N

R

R

NN

O

O

O

O

R = hexyl

N

R

R

C C

n n

n = 3

NN

O

O

O

O

R2

R2

R1

R1

SH

R1

R1

R2

R2

R1

R1

HS

R1

R1

NN

O

O

O

O

R2

R2

R1

R1

R2

R2

R1

R1

NN

O

O

O

O

R2

R2

R2

R2

NN

O

O

O

O

R2

R2

R2

R2

SHHS

R1 = n-hexyl; R2 = i-Pr


SELF-ASSEMBLING SETs first results

supporting nanowire structure(Au on Si/SiO2)

I-V curves typical for single-electron transistors


RECURRENT CROSSNET

somaj

somak

+

+-

-

+

+-

-

“synaptic plaquettes”

(each serves 4 cell pairs)


CROSSNETs: TRAINING

Njal (>72 GFLOPS Linpack) - 165 processors

- 81 node Ethernet - 40 node Myrinet

Acknowledgment: DoD’s DURIP program, AFOSR

Challenges… …and means

-deeply recurrent network (backprop, etc. impossible)

-no access to individual synaptic weight

- possibly, large system sizenecessary for interesting tasks


CROSSNET STATISTICS

“Small-world” networks: l ln(N/Mlong)

The World Wide Web: l 3

InBar: l L/3M = (N/9M)1/2

RandBar: l (N/4M)1/2/ln(L/2)

Example:N =107, M = 103

l 5 (cf. the Web)

L2 = (M+1)N


RECURRENT CROSSNETS: CHAOTIC DYNAMICS

Effective gain g

xj(t)

g/gc = 1.0

1.1

2.0

3.0

O. Turel, I. Muckra & K.L., 2003

time (R0C0)

M = 16

axon saturation level

256256 InBarg/gc =1.5

M = 16


GLOBAL REINFORCEMENT TRAINING (PLANS ONLY)

- Self-evolution: xj = xj(t)

- Inputs: xj(t) = xj

i(t) + xje(t)

- Outputs: xk (t)

- Training:

change (quasi-) global shift S

INPUT

OUTPUT

“HIDDENCELL

FIELD”


INBAR-BASED BLOCK

column address decoder

and drivers

line

address

decoder

and

drivers

sense

amps

and

address

coder

bus

drivers

high speed, long distance bus system

bus

drivers

Documents

ADMOL, Dresden, Germany February 2004 1 Konstantin Likharev Stony Brook University Acknowledgments: W. Chen, E. Cimpoiasu, S. Fölling J. Lee, X. Liu, J