ADM-SDEV-BASE/XCKU060 User Manual V1 user manual_v1_6.… · C43 R22 C42 C41 R24 R25 C46 R23 L2 C44 C45 U6 C49 C52 C48 R26 R27 C50 R600 C53 C47 R28 C56 R30 R32 C54 R29 R31 C51 C55

ADM-SDEV-BASE/XCKU060User ManualDocument Revision: 1.6

19th May 2020

ADM-SDEV-BASE/XCKU060 User ManualV1.6 - 19th May 2020

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Table Of Contents

1 Introduction ...................................................................................................................................... 1 1.1 Key Features ................................................................................................................................. 2 1.2 References & Specifications .......................................................................................................... 2 1.3 Environmental & Specifications ..................................................................................................... 22 Installation ........................................................................................................................................ 3 2.1 Software Installation ...................................................................................................................... 3 2.2 Hardware Installation ..................................................................................................................... 3 2.2.1 Handling Instructions ................................................................................................................. 3 2.2.2 Power Supply ............................................................................................................................. 3 2.2.3 Cooling Requirements ............................................................................................................... 3 2.2.4 Configuration FMC Board .......................................................................................................... 33 Functional Description .................................................................................................................... 4 3.1 Overview ........................................................................................................................................ 4 3.1.1 Switch Definitions ...................................................................................................................... 5 3.1.2 Status LED Definitions ............................................................................................................... 6 3.1.3 User LEDs - ADA-SDEV-KIT2 only ............................................................................................ 7 3.2 JTAG Interface ............................................................................................................................... 8 3.2.1 On-board Interface ..................................................................................................................... 8 3.2.2 JTAG Voltages ........................................................................................................................... 8 3.3 Clocks ............................................................................................................................................ 9 3.3.1 Reference Clocks (REFCLK400M and FABRIC_CLK) ............................................................ 10 3.3.2 Programmable Clocks (PROGCLK0 and PROGCLK1) ........................................................... 10 3.3.3 Module to Carrier Global Clocks (CLK_M2C) .......................................................................... 10 3.3.4 Module to Carrier MGTREF Clocks (GBTCLK_M2C) .............................................................. 11 3.4 Configuration ............................................................................................................................... 12 3.4.1 Configuration From ADM-SDEV-CFG1 Flash Memory ............................................................ 12 3.4.1.1 Building and Programming Configuration Images ............................................................... 12 3.4.2 Configuration via JTAG ............................................................................................................ 13 3.5 Health Monitoring ......................................................................................................................... 14 3.5.1 Automatic Temperature Monitoring .......................................................................................... 15 3.5.2 Microcontroller Status LEDs .................................................................................................... 15 3.6 FPGA ........................................................................................................................................... 16 3.6.1 I/O Bank Voltages .................................................................................................................... 16 3.6.2 Target MGT Links .................................................................................................................... 16 3.7 Memory Interfaces ....................................................................................................................... 18 3.8 FMC Interfaces ............................................................................................................................ 19 3.8.1 Low Pin Count (LPC) FMC, J1 ................................................................................................ 19 3.8.2 Configuration FMC, J2 ............................................................................................................. 19 3.8.3 High Pin Count FMC+, J3 ........................................................................................................ 19 3.8.4 FMC VADJ Power Supplies ..................................................................................................... 20

Appendix A Rev1 PCB Top View ....................................................................................................................... 21

List of Tables

Table 1 References ........................................................................................................................................ 2Table 2 Switch Definitions .............................................................................................................................. 5Table 3 Status LED Definitions ....................................................................................................................... 6Table 4 User LED FPGA pin locations ............................................................................................................ 7Table 5 DDR REFCLK Connections ............................................................................................................. 10


Table 6 PROGCLK0 Connections ................................................................................................................ 10Table 7 PROGCLK1 Connections ................................................................................................................ 10Table 8 CLK_M2C Connections ................................................................................................................... 11Table 9 GCLK_M2C Connections ................................................................................................................. 11Table 10 Voltage and Temperature Monitors .................................................................................................. 14Table 11 Temperature Limits .......................................................................................................................... 15Table 12 Status LED Definitions ..................................................................................................................... 15Table 13 Target FPGA IO Banks .................................................................................................................... 16Table 14 Target MGT Links ............................................................................................................................ 16Table 15 LPC FMC Groups (J1) ..................................................................................................................... 19Table 16 Config FMC Groups (J2) .................................................................................................................. 19Table 17 FMC+ Groups (J3) ........................................................................................................................... 19

List of Figures

Figure 1 ADM-SDEV-BASE/XCKU060 Top View (rev2 board shown) ............................................................. 1Figure 2 ADM-SDEV-BASE/XCKU060 Block Diagram .................................................................................... 4Figure 3 Status LED Locations ........................................................................................................................ 6Figure 4 User LED Locations ........................................................................................................................... 7Figure 5 JTAG Boundary Scan Chain .............................................................................................................. 8Figure 6 Clocks ................................................................................................................................................ 9Figure 7 Flash Address Map .......................................................................................................................... 12Figure 8 MGT Links ....................................................................................................................................... 17Figure 9 DRAM Banks ................................................................................................................................... 18Figure 10 ADM-SDEV-BASE/XCKU060 Top View (rev1 board shown) ........................................................... 21


1 IntroductionThe ADM-SDEV-BASE/XCKU060 is the base board at the core of the ADA-SDEV-KIT and ADA-SDEV-KIT2space FPGA development kits. These kits enable customers interested in space grade FPGAs to prototype theirapplications on a compatible XCKU060-1I device.

The ADA-SDEV-KIT2 contains an ADM-SDEV-BASE/XCKU060 rev 2 board, while the ADA-SDEV-KIT containsan ADM-SDEV-BASE/XCKU060 rev 1 board.

The differences between revisons are as follows:• The FPGA core power supply on the rev 2 board was uprated to 36A, on the rev 1 board this supply is

rated at 24A.• The rev 2 revision board has user controlled LEDs, a feature not present on the rev 1 board.

Note: Other than the differences listed above, rev 1 and rev 2 revision boards are functionally identical. Unlessstated otherwise all sections of this user manual apply equally to both revisions.

TP8

TP4

TP1

C558

H2

JP1

TP3

C555

C557

C556

H1

F1

C18

C20

C28

U104

FM2

TP2

R16C580

C581

C554

C559

FM1

U4

D10

C6

C400

R338

H4

J3

H3

C19

C21

C577

C575

C574

C569

D11

D12

C7

C31

R17

C34

D13

U3

L1

R14

R599

C33

R19

C35

U2

D14

D15

R15

C32

C576

C572

C573

TP7

C568

C17

C16

C15

C14

C13

R9

H6

H5

H7

C25C24C23

C525

C527

TP5

TP6

C27

C26

C22

C524

C523

C29

L23

C530

R11

R10

C30

R12

R13

U85

C528

R528

R18

R536

R537

J1

R20

C37

C36

C40

U5

C39

C38

R21

C43

R22

C42

C41

R24

R25

C46

R23

C44

L2

C45

U6

C49

C52

C48

C50

R27

R26

R600

C53

C47

R28

C56

R30

R32

C54

R29

R31

C51

C55

R33

C57

C58

J4

C60

C59

C61

R34

C62

C63

H8

L3

TP10

C64

R35

C69

C67

C68

U8

TP9

C65

U7

C66

R36

R38

L4

C71

C74

R41

U9

R37

C73

C70

U10

C76

U12

U11

C75

R40

R39

R598

C72

R42

H9

R52

C93

C80

C79

L6

C87

C88

C85

C86

L5

C84

C83

C81

C82

R43

C77

C89

C78

C96

C97

R58

L7

C91

C92

R44

C90

C95

R51 R56

R49

R50 R55

R48

C94

R46

R47

L8

R45

R59

R57

C103

C101

R54

R53

TP14

TP13

U13

C106

C102

C105

C100

C99

C104

C98

R65

R68

R64

R63 R67

R62

R66

R61

R60

C107

C108

U18

R69

TP16

U16

U15

U14

R71

R70

C112

U17

H10

C111

C110

C109

C123

C122

R75

R74

TP17

R72

TP15

C120

C121

C118

C119

C116

C117

R73

TP18

J2

H11

TP19

TP20

R78

C125

L11

C124

L10

R76

L9

U19

H12

R84

C132

R82

R80

R597

C127

C131

R81

R83

C126

C130

R77

R79

C129

C128

R85

C134

C140

C139

C133

C138

C137

C136

C135

C141

U22

U21

U20

R89

R86

R87

R88

R93

R92

R91

R90

C142

C146

C143

C148

C147

C145

U24

R94 R96

R95

U23

R97C144

R103

C158

C157

C156

R102

C155

C154

C153

R100

R106

R101

C152

C151

C150

C149

R105

R99

R98

C160

R110

R109

R108

R107

R104

C159

C161

TP21

J5

C513

L21

C172

L20

H13

R114

C514

C173

C515

L22

U25

C518

C517

C519

C174

L14

U27

C192

C193

C191

C579

C545

SW1

C181

C578

C546

C516

R344

R345

C175

R524

R340

R538

C544

C547

C183

C533

R343

R539

C536

R341

R342

R541

C532

R112

R346

C162

R111

R339

C167

R119

R540

C535

C548

U103

C549

C197

C534

C520

R525

C531

C163

R113

C169

C166

SW2

R126

TP23

TP22

H15

L16

C199

C198

U30

R125

R124

U31

U47

U46

H14

TP24

TP11

SW3

R357

R358

TP12

R128

R127

R137

U32

JP2

H17

D7

R129

D6

D5

U33

D4

D3

D2

D1

F2

FM3

H16

FM4

CEM ASSY

AOI

AB

CONFIG FMC ONLY

A1

SERIAL NUMBER

SwitchesCONFIG FMC SocketLPC FMC Socket

KU060 FPGA

ON/OFF

Switch

HPC

FMC+

Socket

DDR3 SODIMM Socket

ATX Power Conenctor

User LEDs

Figure 1 : ADM-SDEV-BASE/XCKU060 Top View (rev2 board shown)

Page 1Introductionad-ug-1360_v1_6.pdf


1.1 Key FeaturesKey Features

• Custom Form Factor• Modular design structure• Powered via an external power supply• Fitted with XCKU060-1FFVA1517I FPGA device as standard• PCB footprint compatible with QRKU060-CNA1509 (Contact factory for details)• 1x FMC+ HPC and 1x FMC LPC interfaces• 1x FMC form factor configuration interface - clearly labelled "XRTC-Standard Config-FMC Only"• DDR3 (with ECC) SODIMM connector to banks 66,67,68 for DDR3 support• A JTAG header to allow Vivado Hardware Manager configuration and debug (requires ADM-SDEV-CFG1

board)• Programmable clock generation, controlled by I2C connected to the FMC config daughter base board and

the FPGA• Heatsink and Fan on top of KU060 FPGA

1.2 References & Specifications

ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) Standard, July 2008, VITA, ISBN 1-885731-49-3

ANSI/VITA 57.4 FPGA Mezzanine Card Plus(FMC+) Standard, March 2016, VITA, Draft

ad-ug-0080 ADA-SDEV-KIT Configuration Guide, Nov 2018, Alpha-Data, v1.0

ad-ug-0081 ADA-SDEV-KIT production Test Overview, Sep 2019, Alpha-Data, v1.2

ad-ug-1361 ADA-SDEV-CFG1 User Manual, Nov 2018, Alpha-Data, v1.0

Table 1 : References

1.3 Environmental & SpecificationsThe operational temperature range of the ADA-SDEV-BASE board is outlined in Temperature Limits.

Note: Note: The ADA-SDEV-KIT and ADA-SDEV-KIT2 are designed for use as development platforms only, are notspace graded platforms and are not suitable for flight or radiation testing.

Page 2 Introductionad-ug-1360_v1_6.pdf


2 Installation2.1 Software Installation

Please refer to the Alpha-Data support site for access to system monitoring utilities, documentation and FPGAreference designs.

2.2 Hardware Installation

2.2.1 Handling Instructions

The components on this board can be damaged by electrostatic discharge (ESD). To prevent damage, observeESD precautions:

- Always wear a wrist-strap when handling the card- Hold the board by the edges- Avoid touching any components- Store in ESD safe bag.

2.2.2 Power Supply

The base board is designed to be powered via an external ATX power supply, connected via the standard 24-pinATX12V 2.x power connector J5.

This external ATX power supply must be capable of providing a minimum of 20A (100W) on the +5V rail.

In its default configuration the ADA-SDEV-BASE board draws all of its power from the +5V rail.

Some ATX power supplies may not turn on without a minimum load on the +3.3V rail. Please contact the factoryfor further details. A list of power supplies that have been verified to work with the ADA-SDEV-KIT shall bemaintained in document ad-ug-0081.

2.2.3 Cooling Requirements

The power dissipation of the board is highly dependent on the Target FPGA application. A power estimatorspreadsheet is available on request from Alpha Data. This should be used in conjunction with Xilinx powerestimation tools to determine the exact current requirements for each power rail.

The board is supplied with an active air cooled heatsink.

The board features system monitoring that measures the board and FPGA temperature. It also includes aself-protection mechanism that will clear the target FPGA configuration if an over-temperature condition isdetected.

See Section 3.5 for further details.

2.2.4 Configuration FMC Board

Prior to applying power the configuration FMC board (ADM-SDEV-CFG1 or similar) should be fitted into theConfig FMC Socket (J2).

Page 3Installationad-ug-1360_v1_6.pdf


3 Functional Description3.1 Overview

XCKU060-FFVA1517-1-IOr

XQRKU060-CNA1509FMC+

#3HPC

FMC#1

LPC

Q227

Q228

Q224

Q225

Q226

Q128

Q127

Q126

JTAG

45

44

66 67 68

47

24

48

25

46

64 65

x2

x4

x4

x3

x4

x4

x4

x4

x1

PowerSupplies

ProgrammableClock

Generator

DDR3 SODIMM

FMC #2 Config

x4

Serial IOIPASS PCIe x1

2x SATAClock SMA System

Monitor

USB

QSPI

Figure 2 : ADM-SDEV-BASE/XCKU060 Block Diagram

Page 4 Functional Descriptionad-ug-1360_v1_6.pdf


3.1.1 Switch Definitions

There is a sliding switch situated on the bottom right corner of the board, plus a set of eight DIP switches and apush button switch placed on the top right corner of the board. Their functions are described in SwitchDefinitions.

Note: All switches are OFF by default. Factory Configuration switch must be in the OFF position for normaloperation.

Switch Ref. Function ON State Off State

SW1 (pushbutton) Reset System Reset Normal Operation

SW2-1 Reserved - Normal Operation


SW2-3 Config Disable Configuration of the FPGA is disabled. Normal Operation.

SW2-4 FPGA User 1 -FPGA Bank 64 User defined User defined.

SW2-5 FPGA User 2 -FPGA Bank 24 User defined User defined.


SW2-7 FactoryConfiguration - Normal Operation


SW3 (sliding) POWER ON/OFF PSU ON (position A) PSU OFF (position B)

Table 2 : Switch Definitions

Page 5Functional Descriptionad-ug-1360_v1_6.pdf


3.1.2 Status LED Definitions

The position and description of the board status LEDs are shown in Status LED Locations:

D1 D2 D3 D4 D5 D6 D7

Figure 3 : Status LED Locations

Comp. Ref. Function ON State Off State

D1(Green) Status 0 See Status LED Definitions

D2(Red) Status 1 See Status LED Definitions

D3(Red) Internal PowerFault Internal Power supply fault Normal operation

D4(Green) FPGA Done FPGA is configured FPGA is unconfigured

D5(Red) Reserved forfuture use - -

D6(Green) Reserved forfuture use - -

D7(Green) ATX PSUStatus Normal operation ATX PSU Off

Table 3 : Status LED Definitions



3.1.3 User LEDs - ADA-SDEV-KIT2 only

There are six user defined LEDs available on the board ,their positions are shown in User LED Locations:

D10-D15

Figure 4 : User LED Locations

Comp. Ref. Pin Loc

D10(Green) AH31

D11(Green) AH32

D12(Green) AE30

D13(Green) AF30

D14(Green) AH28

D15(Green) AJ28

Table 4 : User LED FPGA pin locations

Note: User LEDs are only present on ADA-SDEV-KIT2 kits, i.e. base board pcb revision 2 onwards. No user LEDsare available on ADA-SDEV-KIT.



3.2 JTAG Interface

3.2.1 On-board Interface

A JTAG boundary scan chain can be accessed via a standard connector on the config FMC (J2). This allows theconnection of the Xilinx JTAG cable for FPGA debug using the Xilinx toolchain.

The JTAG chain starts on the config FMC board and passes through the FPGA, the LPC FMC (J1) (if fitted) andthe FMC+ (J3) (if fitted).

The scan chain is shown in JTAG Boundary Scan Chain:

FPGAXCKU060

LPCFMC(J1)

FMC1_PRESENT#

Level ShiftFMC2_VIO –> 3V3

En#

FMC1_TDI

FMC1_TDO

FPGA_TDI

HDR_TDO

Level Shift3V3 -> FMC2_VIO

FMC2_TDI

FMC2_TDO

ConfigFMC(J2)

FMC+(J3)

FMC3_PRESENT#

Level ShiftFMC2_VIO –> 3V3

En#

FMC3_TDI

FMC3_TDO

FPGA_TDO

Figure 5 : JTAG Boundary Scan Chain

At each stage the clock signal on this JTAG interface (TCK) has a parallel termination (49.9Ω + 22pF to ground)located at the far end of the line.

3.2.2 JTAG Voltages

The Vcc supply provided to the JTAG cable on the config FMC is +3.3V and is protected by a poly fuse rated at375mA.

The JTAG signals on all of the FMC boards use 3.3V signals and are connected through level translators to theADM-SDEV-BASE board scan chain.

The voltage level of the JTAG chain on the ADM-SDEV-BASE board is set to the config FMC adjustable voltageFMC2_VIO.



3.3 ClocksThe ADA-SDEV-BASE board provides a wide variety of clocking options. In addition to the and clocks routedfrom the FMC connectors, the board has 2 user-programmable clock generators. These clocks can be combinedwith the FPGA's internal PLLs to suit a wide variety of communication protocols.

A complete overview of the clock routing on the ADA-SDEV-BASE is given in Clocks. A description of eachclock follows.

UltrascaleMGT/ Banks

MGT228REFCLK0

REFCLK1

MGT227REFCLK0

REFCLK1

MGT226REFCLK0

REFCLK1

MGT225REFCLK0

REFCLK1

MGT224REFCLK0

REFCLK1

MGT128REFCLK0

REFCLK1

MGT127REFCLK0

REFCLK1

UserProgrammable

Source 0

MGT126REFCLK0

REFCLK1

Bank 67(DDRBanks

66,67,68)

Bank 25

Bank 46

200MHzSource

400MHzSource

FABRIC_CLK

REFCLK_400

Bank 44

Bank 45

Bank 24

Bank 64

Bank 65

Bank 47

Bank 48

UserProgrammable

Source 1

LPCFMC(J1)

CFGFMC(J2)

FMC+(J3)

CLK1_M2C_0/1

PROGCLK0

PROGCLK1

GBTCLK1_0_M2C

CLK2_M2C_0/1

CLK2_M2C_2/3

GBTCLK2_0_M2C

CLK3_M2C_0/1

CLK3_M2C_2/3

GBTCLK3_3_M2C

GBTCLK3_4_M2C

GBTCLK3_5_M2C

GBTCLK3_0_M2C

GBTCLK3_1_M2C

GBTCLK3_2_M2C

Figure 6 : Clocks



3.3.1 Reference Clocks (REFCLK400M and FABRIC_CLK)

The fixed reference clocks REFCLK400M and FABRIC_CLK are differential HSTL signals.

REFCLK400M is used as the input clock for the DDR SDRAM interface.

FABRIC_CLK is used as the reference clock for the IO delay control block (IDELAYCTRL).

Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin

REFCLK400M 400 MHz IO BANK 67 HSTL H18 H17

FABRIC_CLK 200 MHz IO BANK 67 HSTL H19 G19

Table 5 : DDR REFCLK Connections

3.3.2 Programmable Clocks (PROGCLK0 and PROGCLK1)

There are two programable clock sources that are forwarded throughout the FPGA. These clocks areprogrammable through the Alpha Data ADA-SDEV-BASE SDK. PROGCLK0 and PROGCLK1 are generated by adedicated programmable clock generator IC and offer extremely high frequency resolutions (1ppm increments).


PROGCLK0[0] 5 - 400 MHz IO BANK 45 LVDS AL27 AL28

PROGCLK0[1] 5 - 400 MHz MGTREFCLK1_224 LVDS AP10 AP9

PROGCLK0[2] 5 - 400 MHz MGTREFCLK1_127 LVDS V32 V33

PROGCLK0[3] 5 - 400 MHz IO BANK25 LVDS AN36 AN37

Table 6 : PROGCLK0 ConnectionsNote: PROGCLK0[3:0] are all buffered copies of the same clock signal. The default (factory set) frequency ofPROGCLK0 = 400MHz.


PROGCLK1[0] 5 - 400 MHz MGTREFCLK1_225 LVDS AK10 AK9

PROGCLK1[1] 5 - 400 MHz IO BANK 64 LVDS AP19 AP18

PROGCLK1[2] 5 - 400 MHz IO BANK 48 LVDS J26 H26

PROGCLK1[3] 5 - 400 MHz MGTREFCLK1_226 LVDS AC8 AC7

Table 7 : PROGCLK1 ConnectionsNote: PROGCLK1[3:0] are all buffered copies of the same clock signal. The default (factory set) frequency ofPROGCLK1 = 150MHz.

3.3.3 Module to Carrier Global Clocks (CLK_M2C)

Each connected FMC board can generate a number of differential Global clocks (as per the FMC standard).They each connect to an global clock input on the FPGA.



FMC Signal Frequency FPGA Input IO Standard "P" pin "N" pin

1 CLK1_M2C_0 Variable Bank 44 LVDS AM22 AN22




2 CLK2_M2C_2 Variable Bank 64 LVDS AL19 AL18

2 CLK2_M2C_3 Variable Bank 64 LVDS AL17 AM17

3 CLK3_M2C_0 Variable Bank 46 LVDS H36 G36

3 CLK3_M2C_1 Variable Bank 46 LVDS G37 F37

3 CLK3_M2C_2 Variable Bank 47 LVDS F32 E32

3 CLK3_M2C_3 Variable Bank 47 LVDS F33 E33

Table 8 : CLK_M2C Connections

3.3.4 Module to Carrier MGTREF Clocks (GBTCLK_M2C)

Each connected FMC board can generate a number of differential MGT Reference clocks (as per the FMCstandard). They each connect to an MGTREFCLK input on the FPGA.

FMC Signal Frequency FPGA Input IO Standard "P" pin "N" pin

1 GBTCLK1_0_M2C Variable MGTREFCLK_225 LVDS AM10 AM9

2 GBTCLK2_0_M2C Variable MGTREFCLK_224 LVDS AT10 AT9

3 GBTCLK3_0_M2C Variable MGTREFCLK_226 LVDS AH10 AH9

3 GBTCLK3_1_M2C Variable MGTREFCLK_227 LVDS AE8 AE7

3 GBTCLK3_2_M2C Variable MGTREFCLK_228 LVDS AA8 AA7

3 GBTCLK3_3_M2C Variable MGTREFCLK_126 LVDS AD32 AD33

3 GBTCLK3_4_M2C Variable MGTREFCLK_127 LVDS Y32 Y33

3 GBTCLK3_5_M2C Variable MGTREFCLK_128 LVDS T32 T33

Table 9 : GCLK_M2C Connections



3.4 ConfigurationThere are two main ways of configuring the FPGA on the ADM-SDEV-BASE:

• From Flash memory on the config FMC board, at power-on, as described in Section 3.4.1

• Using a Xilinx Platform JTAG cable connected to the programming header on the config FMC boardSection 3.4.2

3.4.1 Configuration From ADM-SDEV-CFG1 Flash Memory

The FPGA can be automatically configured at power-on from two 256 Mbit QSPI flash memory device configuredas an x8 SPI device (Micron part numbers MT25QU256ABA8E12-1SIT). These flash devices are typicallydivided into two regions of 32 MiByte each, where each region is sufficiently large to hold an uncompressedbitstream for the FPGA.

It is possible to use Multiboot with a fallback image on this hardware. The master SPI configuration interface andthe Fallback MultiBoot are discussed in detail in Xilinx UG570.

The flash address map is as detailed below:

Dat

a R

egio

n

Region 0Default(32 MiB)

Region 1Multi-boot

(32 MiB)

Start Address (Bytes)0x000_0000

0x200_0000

Figure 7 : Flash Address Map

At power-on, the FPGA attempts to configure itself automatically in serial master mode based on the contents ofthe header in the programing file. See Xilinx UG570 MultiBoot for details.

Note: If an over-temperature alert is detected from the System Monitor, the FPGA will be cleared by pulsing itsPROG signal. See Automatic Temperature Monitoring.

3.4.1.1 Building and Programming Configuration Images

Generate a bitfile with these constraints (see xapp1233):• set_property BITSTREAM.GENERAL.COMPRESS TRUE [ current_design ]• set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-1 [current_design]• set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]• set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]• set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]• set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]• set_property CFGBVS GND [ current_design ]• set_property CONFIG_VOLTAGE 1.8 [ current_design ]• set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]

Generate an MCS file with these properties (write_cfgmem):• -format MCS• -size 64• -interface SPIx8



• -loadbit "up 0x0000000 <directory/to/file/filename.bit>" (0th location)• -loadbit "up 0x2000000 <directory/to/file/filename.bit>" (1st location, optional)

Program with vivado hardware manager with these settings (see xapp1233):• SPI part: mt25qu256-spi-x1_x2_x4_x8• State of non-config mem I/O pins: Pull-none• Target the four files generated from the write_cfgmem tcl command.

3.4.2 Configuration via JTAG

A Xilinx Platform Programming Cable may be attached to the programming header on the Config FMC board.This permits the FPGA to be reconfigured using the Xilinx Vivado Hardware Manager via JTAG. The device willbe automatically recognized in Vivado Hardware Manager.

For more detailed instructions, please see “Programming the FPGA Device” section of Xilinx UG908: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug908-vivado-programming-debugging.pdf



3.5 Health MonitoringThe ADA-SDEV-BASE has the ability to monitor temperature and voltage to maintain a check on the operationof the board. The monitoring is implemented using the Atmel AVR microcontroller.

Control algorithms within the microcontroller automatically checks line voltages and on board temperatures.

The following voltage rails and temperatures are monitored:

Monitor Name Purpose Units

12.0V ADC00 Board Input Supply V



FMC2_VIO ADC03 Config FMC I/O voltage V

2.5V ADC04 Level Translation V

1.8V ADC05 FPGA IO Voltage (VCCO) V

0.95V ADC06 Target FPGA Core Supply (VccINT) V

1.8V ADC07 Target Transceiver Power (AVCC_AUX) V

1.5V ADC08 DDR SDRAM, Target FPGA memory I/O V

1.2V ADC09 Target Transceiver Power (AVTT) V

1.0V ADC10 Target Transceiver Power (AVCC) V

12.0V Current ADC11 12V Supply Current Reading A

5.0V Current ADC12 5V Supply Current Reading A

3.3V Current ADC13 3.3V Supply Current Reading A

Temp1 TMP00 micrcontroller on-die temperature deg C

Temp2 TMP01 Board temperature sensor on-die temperature deg C

Temp3 TMP02 FPGA on-die temperature deg C

Table 10 : Voltage and Temperature MonitorsNote: The "Name" column contains the name assigned to each sensor in the display-sensors utility report.



3.5.1 Automatic Temperature Monitoring

At power-up, the control logic sets the temperature limits and resets the temperature sensor's over-temperatureinterrupt.

The temperature limits are shown below :

.FPGA Board

Min Max Min Max

Industrial -40 degC +100 degC -40 degC +100 degC

Table 11 : Temperature LimitsImportant:

If any temperature limit is exceeded, the FPGA is automatically cleared. This is indicated by the Green LED(FPGA Configured) switching off and the two status LEDs showing a temperature fault indication.

The purpose of this mechanism is to protect the card from damage due to over-temperature.

3.5.2 Microcontroller Status LEDs

LEDs D2 (Red) and D1 (Green) indicate the microcontroller status.

LEDs Status

Green Running and no alarms

Green + Red Standby (Powered off)

Flashing Green + Flashing Red(together) Attention - critical alarm active

Flashing Green + Flashing Red(alternating) Service Mode

Flashing Green + Red Attention - alarm active

Red Missing application firmware orinvalid firmware

Flashing Red FPGA configuration cleared toprotect board

Table 12 : Status LED Definitions



3.6 FPGA

3.6.1 I/O Bank Voltages

The FPGA IO is arranged in banks, each with their own supply pins. The bank numbers, their voltage andfunction are shown in Target FPGA IO Banks. Full details of the IOSTANDARD required for each signal aregiven in the ADA-SDEV-BASE SDK.

IO Banks Voltage Purpose

0, 65 FMC2_VIO_B Configuration, JTAG

44, 45 FMC1_VADJ LPC FMC GPIO

24, 64 FMC2_VADJ Config FMC GPIO

25, 46, 47 FMC3_VADJ FMC+ GPIO

48 FMC3_VIO_B FMC+ GPIO

66, 67, 68 1.5V DDR SODIMM

Table 13 : Target FPGA IO Banks

3.6.2 Target MGT Links

There are a total of 32 Multi-Gigabit Transceiver (MGT) links connected to the FPGA:

Links Width Connection

FMC1_DP(3:0) 4 links to LPC FMC Socket (J1)

FMC2_DP(3:0) 4 links to Config FMC Socket (J2)

FMC3_DP(23:0) 24 links to FMC+ Socket (J3)

Table 14 : Target MGT LinksNote: link FMC2_DP(1) is unavailable on the CNA1509 package device.

The connections of these links are shown in MGT Links:

For MGT Clocking see Clocks:



Kintex UltrascaleMGT

MGT126

MGT127

MGT227

MGT226

MGT225

MGT224

ConfigFMC(J2)

FMC+(J3)

MGT128

MGT228

FMC2_DP(3:0)

FMC1_DP(3:0)LPCFMC(J1)

FMC3_DP(3:0)

FMC3_DP(7:4)

FMC3_DP(11:8)

FMC3_DP(15:12)

FMC3_DP(19:16)

FMC3_DP(23:20)

Figure 8 : MGT Links



3.7 Memory InterfacesThe ADA-SDEV-BASE has a single SODIMM socket, capable of supporting a DDR3 (with ECC) SODIMMmodule, spread across 3 FPGA IO banks (66/67/68).

The memory banks are arranged for compatibility with the Xilinx Memory Interface Generator (MIG). DRAMBanks Shows the FPGA banks used. Full details of the interface, signaling standards and an example designare provided in the ADA-SDEV-BASE SDK.

Kintex Ultrascale

Bank67

DDR SODIMM

400MHzREFCLK

Bank68

Bank66

200MHzIDELAYCLK

Figure 9 : DRAM Banks



3.8 FMC InterfacesThe ADA-SDEV-BASE board has 3 FMC sockets, J1, J2 and J3. Their interfaces are described below.

3.8.1 Low Pin Count (LPC) FMC, J1

Connector J1 is for general purpose IO.

Group FPGABank Name Function

FMC1_LA_0 44FMC1_LA(16:2) 15 diff. Pairs / 30 single-ended

FMC1_LA_CC (1:0) 2x Regional Clocks / GPIO pairs / 4 single-ended



Table 15 : LPC FMC Groups (J1)

3.8.2 Configuration FMC, J2

Connector J2 is used for the FPGA configuration interface plus also for general purpose IO.


CONFIG 0,65 Various FPGA Configuration Interface





Table 16 : Config FMC Groups (J2)

3.8.3 High Pin Count FMC+, J3

Connector J3 is used for general purpose IO.






FMC3_HA_0 25,46

FMC3_HA(16:2) 15 diff. Pairs / 30 single-ended

FMC3_HA_CC (1:0) 2x Regional Clocks / GPIO pairs / 4 single-ended

FMC3_HA(23:18) 6 diff. Pairs / 12 single-ended

FMC3_HA_CC (17) Regional Clock / GPIO pair / 2 single-ended

FMC3_HB_0 48 FMC3_HB(5:1) 5 diff. Pairs / 10 single-ended

Table 17 : FMC+ Groups (J3) (continued on next page)




FMC3_HB_0 48

FMC3_HB(16:7) 10 diff. Pairs / 20 single-ended

FMC3_HB(21:18) 4 diff. Pairs / 8 single-ended

FMC3_HB_CC (0) Regional Clock / GPIO pair / 2 single-ended



Table 17 : FMC+ Groups (J3)

3.8.4 FMC VADJ Power Supplies

The ADM-SDEV-BASE/XCKU060 board is fully compliant with the VITA 57.1 standard. This means that any FMCcard that is used with the board should have an EEPROM on board programmed according to the IPMI formatdefined in the VITA 57.1 FMC specification.

The IPMI specification notes that an FMC board should use a 2K EEPROM which is compatible with 24C02devices. This EEPROM must be available to be queried at power on in order that the FMC slot VADJ voltage canthen be set up and turned on.

If this specification is not followed, the VADJ voltage to the FMC slot in question will not automatically power up(it will correctly remain at 0V).

Note: In the event that this EEPROM is not present on the FMC board, an alternative method of configuring the FMCVADJ power supply is also possible. The use of this alternative method is not recommended practice. Pleasecontact Alpha Data support for further details if required.



Appendix A: Rev1 PCB Top View

ON/OFF

Switch

Figure 10 : ADM-SDEV-BASE/XCKU060 Top View (rev1 board shown)

Page 21Rev1 PCB Top Viewad-ug-1360_v1_6.pdf


Revision HistoryDate Revision Nature of Change

12 Sep 2018 0.1 Initial Draft

21 Sep 2018 0.2 Updated after review

27 Nov 2018 1.0 First Release

28 Aug 2019 1.1 Updated sensor table to include sensor name

23 Sep 2019 1.2 Updated references table and section on ATX power supply

11 Oct 2019 1.3 Corrected error in release date of previous version

29 Feb 2020 1.4 Added mention of new user LEDs on Rev 2 pcb

18 May 2020 1.5 Added definition of differences between rev1 and rev2 pcbs

19 May 2020 1.6Added section regarding turn on of FMC ADJ powersupplies.

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Telephone: (303) 954 8768Fax: (866) 820 9956 - toll freeemail: [email protected]: http://www.alpha-data.com

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