Adic Theory

8/2/2019 Adic Theory

1/20

SSPMs COLLEGE OF ENGINEERING

ELECTRICAL DEPARTMENT

SUB:-ADIC SEM:-EVEN

------------------------------------------------------------------------------------------------------------

EXPERIMENT NO:-1

Aim :- Study the Basic gate and verify their truth table.

Apparatu :- Bread Board, Led, Connecting wire.

Components:-IC 7408 AND Gate

IC 7432 OR Gate

IC 7404 NOT Gate

IC 7400 NAND GateIC 7402 NOR Gate

Theory :- Basic Gate :-

NOT GATE:-1) The inverter (NOT circuit) performs a basic logic function called inversion or

complementation. 2) The inverter changes on logic level to its opposite level.AND GATE:-1) The AND gate perform logical addition, more commonly known as the AND function.2) The operation of the OR gate is such that the output is high only when all of i/ps are high3) When any of the i/ps are low the output is low.OR GATE:-

1)The OR gate perform logical multiplication, more commonly known as the OR function.2)An OR gate produces a high on the output when any of the inputs is high3)The output is low only when all of inputs are low.

Universal Gate:-

NAND GATE:-1) The term NAND is a contraction of NOT-AND and implies an AND function with

complemented output.

2) The logical operation of NAND gate is such that a low output occurs only when all input arehigh

3) When any of the inputs is low, the output will be high.NOR GATE:-1) The term NOR is a contraction of NOT-OR and implies an OR function with an inverted

output.

2) The logic operation of the NOR gate is that a low output occurs when any of its i/ps is high3) Only when all of its inputs are low, the output is high.

Procedure:-1) Mount the ICs on bread board2) Connect Vcc to pin no.14 and ground to pin no.73) Give i/p to respective i/p pin, which is indicate in pin diagram4) Now apply all conditions one by one and check output from respective o/p pin.5) Verify the truth table. The o/p LED glows when o/p is high, otherwise LED off.


2/20

Circuit Diagram & Truth Table:-

A) NOT Gate:- (IC 7404)Symbol (NOT Gate) A A

Pin Diagram :-+Vcc 14 13 12 11 10 9 8

1 2 3 4 5 6 7 GND

B) AND Gate:- (IC 7408)

Symbol (AND Gate)A

B Y= A.B

Pin Diagram:-+Vcc14 13 12 11 10 9 8

1 2 3 4 5 6 7 GNDC) OR Gate:- (IC 7432)

Symbol (OR Gate) A Y = A+B

BPin Diagram:-

+Vcc14 13 12 11 10 9 8

1 2 3 4 5 6 7 GND

D) NAND Gate:- (IC 7400)

Symbol (NAND Gate)

AB Y= A.B

Pin Diagram:-+Vcc14 13 12 11 10 9 8

1 2 3 4 5 6 7 GND

A Y=A

0 1

1 0

A B Y=A.B

0 0 0

0 1 0

1 0 01 1 1

A B Y=A+B0 0 0

0 1 1

1 0 1

1 1 1

A B Y=A.B0 0 1

0 1 1

1 0 1

1 1 0

IC 7404

IC 7408

IC 7432

IC 7400


3/20

E) NOR Gate:- (IC 7402)

Symbol (NOR Gate)A

B Y = A+B

Pin Diagram:-

+Vcc14 13 12 11 10 9 8

1 2 3 4 5 6 7 GND

Result :-

A) NOT Gate:-1) When high level is applied to an inverter i/p, low level is appear on its o/p and vice versa.

B) AND Gate :-1) Output of this gate is high only when all of the i/ps are high.

2) When any of the i/p is low, o/p is low.

C) OR Gate:-1) Output of OR gate is high, when any of i/p is high.

2) o/p is low only when all of i/ps are low.

D) NAND Gate:-1) Low o/p occurs only when all i/ps are high.

2) When any of i/p is low, o/p is high.

E) NOR Gate:-1) Low o/p occurs only when any of its i/p is high.

2) Only when all of its i/p low, o/p is high.

Conclusion:-Thus from above experiment we studied operation of NOT, AND, OR, NAND & NOR gate also

verify its truth table.

List of Questions:-1) Which IC is used for implementation of OR gate.2) Draw the symbol for NOR gate.3) When all inputs to the NAND gate are high then output is at which logic level.4) Give the truth table for AND gate.

A B Y=A+B

0 0 1

0 1 0

1 0 0

1 1 0

IC 7402


4/20



SUB:-ADIC SEM:-EVEN

------------------------------------------------------------------------------------------------------------

EXPERIMENT NO :-2

Aim:- To implement X-OR and X-NOR using universal gate (NAND & NOR)

Apparatus:- Bread Board, Logic trainer kit, Connecting wire.

Components:-IC 7400 NAND Gate

IC 7402 NOR Gate

Theory :-

Universal Gate :The NAND and NOR gates are the universal gates since any logic function can be implemented

using NAND and NOR gate.

Procedure:-1) Mount the ICs on bread board2) Connect Vcc to pin no.14 and ground to pin no.73) Give i/p to respective i/p pin, which is indicate in pin diagram4) Now apply all conditions one by one and check output from respective o/p pin.5) At o/p side, if light glow then o/p is high otherwise low.6) Note down the o/p for all condition and verify the standard truth table.


A) X-OR Gate using NAND gate :-

B) X-NOR Gate using NAND gate:-


5/20

C) X-OR Gate using NOR gate :-

D) X-NOR Gate using NOR gate :-

Truth table :-For X-OR Gate: - For X-NOR Gate:-

Result :-A) X-OR Gate:-

1) The o/p is high only when odd number of inputs are highB) X-NOR Gate:-

1) The o/p is high only when even number of i/ps is high or when all i/p are zeroes.Conclusion :-

Thus, we studied implementation of X-OR & X-NOR gate by using NAND & NOR gate which

are known as universal gate.

List of Questions:-1) What is mean by universal gate.2) Which gates act as universal gates.3) Implement X-NOR gate using NAND gate.4) Give the truth table for X-OR gate.

A B Y=A+B

0 0 0

0 1 1

1 0 1

1 1 0

A B Y=A.B

0 0 1

0 1 0

1 0 01 1 1


6/20



SUB:-ADIC SEM:-EVEN

------------------------------------------------------------------------------------------------------------

EXPERIMENT NO :-3

Aim :- Implementing a binary to gray and gray to binary code converter using gate ICs.

Apparatus :- Bread Board, Logic trainer kit, Connecting wire.

Components:-

IC 7486 E-OR Gate

Theory :-Binary to Gray code converter:-

The gray code is often used in digital system because it has the advantages that only one

bit in the numerical representation changes between successive numbers.

B4 B3 B2 B1

G4 G3 G2 G1

Gray to Binary code converter

G4 G3 G2 G1

B4 B3 B2 B1

Procedure:-1) Mount the ICs on bread board2) Connect Vcc to pin no.14 and ground to pin no.73)

Give i/p to respective i/p pin, which is indicate in pin diagram

4) Now apply all conditions one by one and check output from respective o/p pin.5) At o/p side, if light glow then o/p is high otherwise output is low.6) Note down the o/p for all condition and verify it with standard truth table.


A) Binary to Gray code converter :-D C B A

G0

G1

G2

G3


7/20

Decimal Binary Code Gray Code

D C B A G3 G2 G1 G0

0 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 1

2 0 0 1 0 0 0 1 1

3 0 0 1 1 0 0 1 0

4 0 1 0 0 0 1 1 0

5 0 1 0 1 0 1 1 1

6 0 1 1 0 0 1 0 1

7 0 1 1 1 0 1 0 0

8 1 0 0 0 1 1 0 0

9 1 0 0 1 1 1 0 1

10 1 0 1 0 1 1 1 1

11 1 0 1 1 1 1 1 0

12 1 1 0 0 1 0 1 0

13 1 1 0 1 1 0 1 1

14 1 1 1 0 1 0 0 1

15 1 1 1 1 1 0 0 0

B) Gray to Binary code converter:-G3 G2 G1 G0

A

B

C

D

Decimal Binary Code Gray Code

D C B A G3 G2 G1 G0

0 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 1

2 0 0 1 1 0 0 1 0

3 0 0 1 0 0 0 1 1

4 0 1 1 0 0 1 0 0

5 0 1 1 1 0 1 0 1

6 0 1 0 1 0 1 1 07 0 1 0 0 0 1 1 1

8 1 1 0 0 1 0 0 0

9 1 1 0 1 1 0 0 1

10 1 1 1 1 1 0 1 0

11 1 1 1 0 1 0 1 1

12 1 0 1 0 1 1 0 0

13 1 0 1 1 1 1 0 1

14 1 0 0 1 1 1 1 0

15 1 0 0 0 1 1 1 1


8/20

Result:-

A) Binary to Gray code converter.i) Lower bit of gray code (Go) is given by X-OR combination of lower two bit of Binary code

(B+A)

ii) Second lower bit of gray code (G1) is given by X-OR combination of middle two bit of Binarycode (C+B)

iii) Third lower bit of gray code (G2) is given by X-OR combination of higher two bit of Binarycode (D+C)

iv) Higher bit of gray code (G3) is given by direct higher bit of binary code (D)B) Gray to Binary code converter.

i)Lower bit of Binary code (A) is given by X-OR combination of all bit of gray code(G3+G2+G1+G0)

ii) Second lower bit of Binary code (B) is given by X-OR combination of Higher three bit ofgray code (G3+G2+G1)

iii) Third lower bit of Binary code (C) is given by X-OR combination of higher two bit ofgray code (G3+G2)

iv) Higher bit of Binary code (D) is given by direct higher bit of gray code (G3)

Conclusion :-

Thus, we implement here binary to Gray code and Gray to Binary code converter using gate IC.

List of Questions:-

1. What is advantages of gray code2. How binary number is converted in to gray code3. How gray number is converted into binary code


9/20



SUB:-ADIC SEM:-EVEN

------------------------------------------------------------------------------------------------------------

EXPERIMENT NO :-4

Aim :- Simplifying 3,4 variable logic function and implementing them using gate ICs.


Components:-IC 7408 AND Gate (1)

IC 7432 OR Gate (1)IC 7404 NOT Gate (1)

IC 7402 NOR Gate. (2)

Theory :- To simplify 4 variables K-map.

1) No.of variables = 42) No.of cell = 2 No.of variables.= 24

= 16

3) Basic K-map for 4 variablem0 m1 m3 m2

m4 m5 m7 m6

m12 m13 m15 m14

m8 m9 m11 m10

ORepresent complement of variable

1Variable it self4) Enter the given min terms (value 1) in basic K-map which are given in expression.5) Perform the grouping of1s in k-map. Priority to octal, Quad, pair then single.6) Find out equation for each group which provides simplified equation for given function.

Procedure:-1) Mount the ICs on bread board2) Connect Vcc to pin no.14 and ground to pin no.73) Give i/p to respective i/p pin, which is indicate in pin diagram4) Now apply all conditions one by one and check output from respective o/p pin.5) At o/p side, if light glow then o/p is high otherwise output is low.6) Note down the o/p for all condition and verify it with standard truth table.


10/20

Circuit Diagram :-

I) F(W,X,Y,Z) = W Y + X Z + WXZImplementation of above logic function using AND/OR gate.

II) F (A,B,C,D) = A B + C DImplementation of above logic function using NOR gate.

Result :-

1) Whatever minterms are present in both logic function, for that minterms output is high2) Also which dont care output, use as logic 1 output for that term is high.3) Output for remaining term is low.

Conclusion :-

Thus, we studied simplification of 4 variable logic function and implementation of them

using AND/OR & all NOR gate ICs.


11/20

List of Questions:-1) How many cells are required to implement the k-map for 4 variable.2) How may total number of input combinations are possible for 3 variable.3) What do you mean by SOP & POS.4) How the grouping is made in k-map.


12/20



SUB:-ADIC SEM:-EVEN

------------------------------------------------------------------------------------------------------------

EXPERIMENT NO :-5

Aim :- Implementing full adder using gates and multiplexer.Apparatus :- Bread Board, Logic trainer kit, Connecting wire.

Components:-

IC 7408 AND Gate (1)

IC 7432 OR Gate (1)IC 7404 NOT Gate (1)

IC 7486 X-OR Gate. (1)

IC 74153 Dual 4:1 mux (1)

Theory :- Full Adder :-

A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It

consists of three inputs and two outputs. Two of the input variables, denoted by A and B, represent the

two significant bits to be added, third input Cin, represents the carry from the previous lower significant

position.

Procedure:-

1) Mount the ICs on bread board2) Connect Vcc to pin no.14 and ground to pin no.73) Design circuit as shown in fig. And give input to the IC.4) Now apply all conditions one by one and check output from respective o/p pin.5) At o/p side, if light glow then o/p is high otherwise output is low.6) Note down the o/p for all condition and verify it with standard truth table.

Circuit Diagram & Truth table:-Full Adder using logic gates:-

For carry:-

A AB

B

AB + ACin

ACin

Cin Carry=AB+Bcin+CinA

BCin

For sum:-

A A + B

BSum = A + B + Cin

Cin


13/20

Truth table :-

Inputs Outputs

A B Cin Carry Sum

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Full adder using Dual 4:1 Mux :-

Logic 0 +Vcc GND Logic 0 +Vcc GND

Logic 1

Logic 1 carry

For Carry For Sum

Result :-

1) Output for carry is low, when inputs are 0,1,2 & 4 where as it is high only when inputsare 3,5,6,7.

2) Output for sum is low when inputs are 0,3,5 & 6 whereas it is high only when inputs are1,2,4,7.

Conclusion:-

From above experiment we studied full adder using logic gate and multiplexer.

I

C

7

4

1

5

3

I

C

7

4

1

5

3


14/20

List of Questions:-

1. What is diierence between full & half adder?2. Give the equation of carry, of full adder3. Give the equation of sum ,of full adder4.

What is MUX?


15/20



SUB:-ADIC SEM:-EVEN

------------------------------------------------------------------------------------------------------------

EXPERIMENT NO:-6

Aim :- Constructing flip-flop like SR & D using all NAND gates.


Components:-IC 7400 NAND Gate (2)

Theory :-

FlipFlops (f/f) :-The basic digital memory unit is known as flip-flops (f/f). It has two states which are 1 & 0.

Thus we can obtain it using NAND gate. Here we study two types of f/f as

1) SR F/F 2) D F/F

1)

SR F/F :- The SR F/F has two i/ps i.e. S and R & two o/ps i.e. Q & Q, which are alwayscomplimentary to each other. The circuit has two stable stages i.e. Q = 0 & Q = 1.

2) D F/F :- Looking at the truth table of the SR F/F we can realize that when both i/ps are same theo/p either does not change or it is invalid. In many practical applications, these i/p conditions can

be avoided by making them complement of each other. This modified SR F/F is known as D F/F.

Procedure:-1) Mount the ICs on bread board2) Connect Vcc to pin no.14 and ground to pin no.73) Design circuit as shown in fig. And give input to the IC.4) Now apply all conditions one by one and check output from respective o/p pin.5) At o/p side, if light glow then o/p is high otherwise output is low.6) Note down the o/p for all condition and verify it with standard truth table.

Circuit Diagram & Truth table:-

1) SR F/F :-R

Q

QS

Truth table

S R Q Q State

0 0 Race Race Indeterminate

0 1 0 1 Reset

1 0 1 0 Set

1 1 NC NC No Change


16/20

Symbol :-

i/p o/p

2) D F/F :-D Q

EN

Q

Symbol:-

i/p o/p

Result :-

1) SR F/F are basic memory unit used to store single bit of information.2) The drawbacks of SR F/F can be avoided using D F/F whose o/p delays by one clock pulse.

Conclusion :-

Hence, here we studied SR & D flip-flops using all NAND gates.

List of Questions:-

1. What is mean by flip-flop2. Draw the gate implementation of SR F/F using NAND gate.3. Give the truth table of SR F/F using NAND gate.4. Draw the symbol of D F/F5. Give the truth table of D F/F using NAND gate

Truth table

EN D Q Q State

1 0 0 1 Reset

1 1 1 0 Set

0 x NC NC No Change

S Q

R Q

D Q

EN Q


17/20



SUB:-ADIC SEM:-EVEN

------------------------------------------------------------------------------------------------------------

EXPERIMENT NO:-7

Aim :- To study designing a mod N counter where n < 14 using D flip-flops.


Components:-IC 7474 Dual D flip-flop (2)

IC 7408 Quad 2 AND Gate (2)IC 7432 Quad 2-OR Gate (1)

Theory :-

Design of a synchronous MOD-6 counter using clocked D f/f :-Design with clocked D f/f is slightly simple process them designing with other f/f.

Since a o/p of D f/f follow D i/p next state & f/f i/p column are same & it is not necessary to referexcitation table & data the f/f i/p column in transition state.

Procedure:-1) Mount the ICs on bread board2) Connect Vcc to pin no.14 and ground to pin no.73) Design circuit as shown in fig. And give input to the IC.4) Now apply all conditions one by one and check output from respective o/p pin.5) At o/p side, if light glow then o/p is high otherwise output is low.6) Note down the o/p for all condition and verify it with standard truth table.

Circuit Diagram & Truth table:-Implement the counter:-

Clock

DA QA


18/20

Truth table:-

Pin Configuration of IC 7474

Result:-

1) The procedure of implementing counters using D flip flops is simpler.2) It requires more circuitry to determine flip flop inputs

Conclusion:-

Thus we studied design of synchronous mod-6 counter using clocked D flip-flops.

List of Questions:-

1. What is relation between no. of F/F & counter ?2. What do you mean by Counter?3. What is clock?4. The term mod indicates what?

Present State Next State

QA QB QC QA+1 QB+1 QC+1

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 01 0 0 1 0 1

1 0 1 0 0 0

1 1 0 x x x

1 1 1 x x x

I

C

7

4

7

4


19/20



SUB:-ADIC SEM:-EVE

----------------------------------------------------------------------------------------------------------

EXPERIMENT NO:-8

Aim :- To study Decade Binary Counter using IC 7490.


Components:-IC 7490 Decade Binary Counter

Theory :-

Decade Binary Counter:-The binary counter has maximum no. of states equal to 2

n. where n is the no. of f/f s in

the counter. Counter can be designed to have a no. of states in their sequence that is less than 2n. In

decade counter the sequence is truncated up to the states 0000 (0 in decimal) through 1001 ( 9 in decimal)

These type of counter are very useful in display application in which BCD number are used.

The truncation in the count sequence is achieved by resting the counter at particular count

instead of going through all of its normal states. In case of BCD decade counter is reset back to the 0000

states after the 1001 state. The resetting of counter is done with the help of reset inputs of each f/f. These

inputs are activated when desired state is reacted. In case of BCD decade counter reset is i/p activated

using NAND gate when 1010 state is reached.

9IC 7490 (Decade Binary Counter) :-IC 7490 is a decade binary counter. It consists of four master slave f/fs & additional

gating to provide a divide by two counter & a three stage binary counters for which the count type lengthis divided by five. Since the o/p from the divided by two section is not internally to the two section is not

internally to the succeeding stages, the devices may be operated in various counting modes.

Procedure:-1) Mount the ICs on bread board2)

Connect Vcc to pin no.5 and ground to pin no.10.3) Give clock pulses at pin no.14 (A i/p) & pin no.12 (QA) connect externally to pin no.1 ( Bi/p)

4) Pin no.2, 3 & 6, 7 connect to ground.5) Take o/p from pin no.12 (QA), 9 (QB), 8 (QC) & 11 (QD) and give it to LED.

Circuit Diagram & Truth table:-

Pin configuration of IC 7490

Input A NC QA Qo GND QB QC

Input B Ro(1) Ro(2) NC Vcc Rg(1) Rg(2)

14 13 12 11 10 9 8

1 2 3 4 5 6 7


20/20

7490 as Decade CounterVcc

(5)

(2)

(3)

(14) (6)

Input ACLK 1N (7)

(12) (1) (9) (8) (11)

Input (B)

QA QB QC QD

Truth Table:-

Present State Next State

An Bn Cn Dn An+1 Bn+1 Cn+1 Dn+1

0 0 0 0 0 0 0 1

0 0 0 1 0 0 1 0

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

Result:-In Decade Binary Counter we get output from 0000 (0 in decimal) to 1001 (9 in decimal)

Conclusion:-Thus we studied Decade Binary Counter using IC 7490.

List of Questions:-1. For decade binary counter which IC is used?2. What is the last i/p to decade counter?3. Why is it called as decade binary counter?4. The binary counter has MUX no. of states equal to 2n, n represent what?

2

(MOD -2)

5

(MOD -5)

Documents

Adic Theory