Adiabatic Quantum Programming at ORNL: Workflow ... · Adiabatic Quantum Programming at ORNL: Workflow Environments and HPC Integration APIs QuellE Current/Future D-Wave QPUs Expose

1 billings7893ORNL is managed by UT-Battelle for the US Department of Energy

Adiabatic Quantum Programming at ORNL:Workflow Environments and HPC Integration APIs

Alex McCaskey

Systems and Software Lead

Quantum Computing Institute

Oak Ridge National Laboratory

[email protected]

D-Wave Qubits Users Conference

September 28, 2016

2 Presentation_nameAdiabatic Quantum Programming at ORNL: Workflow Environments and HPC Integration APIs

Outline

• How ORNL approaches adiabatic quantum programming

• AQC Workflow Environment - JADE• QuellE - AQC - HPC Integration API• Focus on Compilation Improvements

ORNL Quantum Computing

Institute

Computer Science

Mathematics

Modeling and Simulation

Experimental Studies

Material Science

Physics

Imaging and Characterization

Electrical Engineering

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What can we do with current QPUs?Treat QPUs as accelerators within a larger HPC

environment

Adiabatic Quantum Programming at ORNL: Workflow Environments and HPC Integration APIs

“In order to turn mature quantum technologies into information-processing devices that can meet DOE needs, it is paramount to develop comprehensive software architecturesfor quantum computers” - ASCR Quantum Computing Workshop Report

???

Software

R&D

D-Wave QPUDOE-relevant scientific

computing tasks stand

to benefit from quantum

acceleration

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Improving AQC Programming through High-Level Workflow Environments...


D-Wave

QPU

Integrated Development Environments• Eclipse-based development environment for reducing

problems to programs– Multi-stage parameter setting, graph processing– Map QUBO to ISING, – Embed ISING into Hardware– Server-client connection with QPU, simulator– Remote connection to D-Wave QPU

Logical connectivity

Embedding

D-Wave unit cell


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JADE Component Architecture


JADE is composed of 3 main pieces

Sapphire manages AQC

Program execution -

numerical simulations

(local or remote

clusters/Titan), or the D-

Wave QPU itself

JADED represents the JADE

Data Layer - responsible for

the creation of user-specified

Entities - Problems,

Processors, Programs

NiCE (now called Eclipse

ICE) provides the

graphical computational

workflow and workbench

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JADED - The Jade Data Layer


1. Basic CRUD-style interface to manage Entities

1. Entities are extensible abstraction for user specified Problems, Processors, and Programs

1. These Entities leverage a home-grown Graph library whose vertex and edge type are extensible

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JADED Implemented Entities In Depth


Provides Reduction of Higher Level

problems to QUBO

Produce QUBO Graph to be fed into

Processor Embedding routines

Enables Construction of General

AQC Processor Graph

Embedding mechanism is extensible,

and users can specify custom Noise

models

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JADED Implemented Entities In Depth


Program encapsulates the

Problem and Embedding

to create a single

runnable-unit

Persistence to XML to be

executed through the

Sapphire component

Programs can be Logical

(solve an optimization

problem) or Physical (just

study Hamiltonian

dynamics)

Custom Annealing Schedules!

IsingParameters subclasses Graph with

custom vertices/edges that evolve

according to user-defined functions

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JADE/JADED in Action Through NiCE


High-level Problem programming through efficient UIs

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JADE/JADED in Action Through NiCE


Create a Program Launch Configuration

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Sapphire - Executing Adiabatic Quantum Programs


Sapphire handles the

execution of Programs

created by JADED

Program Executions can

be through custom

Simulations, or the

physical D-Wave QPU

Sapphire is a pluggableframework for

Simulations

We have implementations for

PETSc enabled Simulations,

and a simple Runge-Kutta

Simulation

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Sapphire In Action


Program Execution through simulations or D-Wave QPU

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Improving AQC Programming through Native HPC Programming Runtime Libraries...


QuellECurrent/Future

D-Wave QPUs

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Tighter HPC Integration - QuellE


QuellECurrent/Future

D-Wave QPUs

Expose quantum resources to HPC application developers!

QuellE Package Structure

• C++, natively parallel (MPI, OpenMP)

• Soon to be open-source and

on GitHub

• Enables inline quantum execution within classical HPC workflows

• QuellE seeks to alleviate AQC programming bottleneck - minor

graph embedding compilation

step

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QuellEGraph - Leveraging Existing State-of-the-art Graph Libraries


QuellE starts by providing a

general interface to existing C++

graph libraries

Currently QuellE has support for

the Boost Graph Library and the

Parallel Boost Graph Library

Requires MPI Communicator

instance - these graphs leverage

parallelism where applicable

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AQCProblem - Expose Problem-Specific QUBO Mapping


IAQCProblem is an interface that

enables the reduction of high-level

optimization problems to QUBO

form

QuellE provides an extension

mechanism that makes it easy for

3rd party developers to inject new

IAQCProblems

We view this a great avenue for

QuellE collaboration!

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EmbeddingAlgorithm - Enable Custom Minor Graph Embedding Computations


The IEmbeddingAlgorithm

interface enables the injection of

custom minor graph embedding

routines into QuellE

QuellE also provides an extension

mechanism that makes it easy for

3rd party developers to inject new

IEmbeddingAlgorithms

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Improving AQC Compilation with QuellE


Implemented parallel

CMR with distributed,

shared, and hybrid

memory models - as a

new

IEmbeddingAlgorithm

P0 P1 P2 P3

DistributedCostMatrix(g,j) =

d(i,0)

….......

d(i,N)

d(i,0)

….......

d(i,N)

d(i,0)

….......

d(i,N)

d(i,0)

….......

Each process computes paths

to subset of all adjacent vertex

models

d(i,N)


Minor set cover embedding

Minor set cover (MSC): • set of minors defined for a graph• contain all minors of a graph as

elements or subgraphs of elements

For a given virtual hardware: deterministic embedding• Pre-compute and store set of hardware graph minors• During embedding step: search set and identify a minor which

contains logic graph as subgraph• Isomorphically mapping logic graph into a stored minor gives a

hardware embedding

For complete bipartite graph KN,N

• MSC has finite size N• Contains KN+1

[Hamilton (2016)]

Example: MSC for K4,4


MSC embedding K9 in Chimera(2,2,4)Virtual hardware: Chimera(n,n,c)

has minor Knc,nc [Goodrich (2016)]

MSC of Knc,nc contains Knc+1

Each vertex in the minor is a subtree of 2 hardware qubits

Each vertex in K9 is a subtree of 2 or 4 hardware qubits

Finding a minor which

contains the logic

graph as a subgraph

gives the embedding

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QuellE In Use


We also provide a QuellE

Compiler

QuellE enables the integration

of a D-Wave Execution within

existing applications done in a

few lines of code

Next steps… A QuellE runtime executable -

qrt. Takes as input the compiled output from

qcc

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Summary


• ORNL/DOE targeting QPUs as HPC accelerators

• Programming abstractions will be key to promote adoption of QPUs into current scientific computing workflows

• QuellE and JADE are first steps toward providing adequate abstractions to the AQC programming workflow

• QuellE will soon be open sourced - looking to collaborate with anyone and everyone for new IAQCProblems and IEmbeddingAlgorithms!

Any Questions?

Thank you for your time!


Minor set cover embedding (Extra Slide)

For MSC of bipartite virtual hardware

• Logical qubits embed into subtrees of size (N) or (2N) only

• MSC can be constructed using simple greedy algorithm

• Embedding of KN+1 requires full hardware

• Definition of MSC dependent on choice of hardware, virtual

hardware

From Hamilton et al. AQC 2016

Timing Plot? I’m trying to get some timing done for Travis - embedding into single

minor, searching MSC then embedding, etc.

Should be done by Sunday, if it looks good I’ll add it in

Otherwise this is just an extraneous slide with extra info

-Kathleen

Documents

Adiabatic Quantum Programming at ORNL: Workflow ... · Adiabatic Quantum Programming at ORNL: Workflow Environments and HPC Integration APIs QuellE Current/Future D-Wave QPUs Expose