Addressing Modes v123

8/8/2019 Addressing Modes v123

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DSP C5000DSP C5000

Chapter 3Chapter 3

Addressing ModesAddressing Modes

Copyright 2003 Texas Instruments. All rights reserved.Copyright 2003 Texas Instruments. All rights reserved.


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Copyright 2003 Texas Instruments. All rights reserved.ESIEE, Slide 2

Obj ectivesObj ectives

Present the main addressing modes andPresent the main addressing modes andallocation of sectionsallocation of sectionsPresent the main addressing modes of Present the main addressing modes of the C54 familythe C54 family

Present the main addressing modes of Present the main addressing modes of the C55 familythe C55 familyExplain how to use these addressingExplain how to use these addressing

modesmodesDo exercises to practice using theDo exercises to practice using thedifferent addressing modesdifferent addressing modes


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O utlineO utline

Generalities on addressing modesGeneralities on addressing modes

C54C54xx

C5C55x5x


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Addressing Modes: What are the Pro b lems?Addressing Modes: What are the Pro b lems?

Specify operands per instruction:Specify operands per instruction:A single instruction can access severalA single instruction can access severaloperands at a time thanks to the manyoperands at a time thanks to the manyinternal data busses,internal data busses,

But how do we specify many addresses usingBut how do we specify many addresses usinga small num ber of b its?a small num ber of b its?

Repeated processing on an array of data:Repeated processing on an array of data:Many DSP operations are repeated on anMany DSP operations are repeated on anarray of data stored at contiguous addressesarray of data stored at contiguous addressesin data memory.in data memory.There are cases where it is useful to be a b leThere are cases where it is useful to be a b leto modify the addresses as part of theto modify the addresses as part of the

instruction (increment or decrement).instruction (increment or decrement).


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Main Addressing Modes of C5000 FamilyMain Addressing Modes of C5000 Family

ImmediateImmediate addressingaddressingAb soluteAb solute addressingaddressingDirectDirect addressingaddressing

IndirectIndirect addressing by registeraddressing by registerSupport for circular indirect addressingSupport for circular indirect addressing

DefinitionDefinition

Access to Memory Mapped RegistersAccess to Memory Mapped RegistersMMRsMMRs


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Allocating SectionsAllocating Sections


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ExampleExample

RAM x[3]

RAM y

C5000CPU

System Diagram

DROM init[3]

EPROM EPROM (code)(code)

y = x1 + x0 + x2Algorithm

How do we allocate the proper sections?

Allocate sections (code, constants, vars)

Setup addressing modesAdd the values (x1 + x0 + x2)Store the result (y)

Procedure


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Writing relocata b le codeWriting relocata b le code

TheThe programmerprogrammer should not have to give theshould not have to give theexact addressexact addresses es::

where to read the code in program memory,where to read the code in program memory,where to read the data in data memory.where to read the data in data memory.

The assem bler allows to use sym bolic addressesThe assem bler allows to use sym bolic addresses. .The assem bler and the linker work with C O FFThe assem bler and the linker work with C O FFfiles:files:

C O FF = Common Obj ect File Format.C O FF = Common Obj ect File Format.In C O FF files, specialized sectionsIn C O FF files, specialized sections are usedare used for code,for code,varia b les or constants.varia b les or constants.The programmer specifies in a command file for theThe programmer specifies in a command file for thelinker where the different sections should belinker where the different sections should beallocated in the memory of the system.allocated in the memory of the system.


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Definition of SectionsDefinition of Sections

Different sections for code, vars, constants.Different sections for code, vars, constants.The sections can b e initialized or not.The sections can b e initialized or not.

An initialized section is filled with code orAn initialized section is filled with code orconstant values.constant values.An uninitialized section reserves memoryAn uninitialized section reserves memoryspace for a varia b le.space for a varia b le.

The sections can have default names orThe sections can have default names ornames given b y the programmer.names given b y the programmer.


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Definition and names of SectionsDefinition and names of SectionsThe programmer uses specialThe programmer uses special directivesdirectives toto

identify the sections.identify the sections.

code VariablesCode or

constants

Namedsections, namegiven by user

.sect .usect

Unnamedsections,

default name.text .data .bss

Initialized sectionsUnitializedsections,

reserve spacefor data


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ExampleExample of sectionsof sections

Initialized named section: InitializationInitialized named section: Initializationof constants. Definition of address t b lof constants. Definition of address t b l

Uninitialized named section: x[3], y[1],Uninitialized named section: x[3], y[1],Definition of address x and y.Definition of address x and y.

Initialized named section: codeInitialized named section: code

RAM x[3]

RAM y

54xCPU

System Diagram

DROM tbl[3]

EPROM code

How are these sectionsplaced into the memoryareas shown?

x .usect "vars",3y .usect "result",1

.sect init"tbl .int 1,2,3

.sect code


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C54x Addressing ModesC54x Addressing Modes


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Format of Data and Instructions, InternalFormat of Data and Instructions, InternalBusses of the C54x FamilyBusses of the C54x Family

In the C54x DSP, the data and programIn the C54x DSP, the data and programmemories are organized in 16memories are organized in 16- -b it words.b it words.Data busses have a 16Data busses have a 16- -b it width.b it width.

Data and instructions are generally of sizeData and instructions are generally of sizeN=16 b its.N=16 b its.Some instructions may take several 16Some instructions may take several 16- -b itb itwords.words.Some data operands may b e dou b leSome data operands may b e dou b leprecision and occupy 2 words.precision and occupy 2 words.Internal busses: 2 data read, 1Internal busses: 2 data read, 1 data writedata write


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Terms from the Users GuideTerms from the Users Guide

Term hat it mea s

mem 16-bit sin le data memor

p ma 16-bit immediate program memory address (0 - 65,535)This includes extended program memory devices

d ma d 16-bit immediate data memory address (0 - 65,535)

Ymem 16-bit dual data-memory operand used in dual-operand instructions.Read throu h bus.

Xmem 16-bit dual data memory operand used in dual-operand instructionsand some sin le-o erand instructions. Read throu h D bus.

PA 16-bit port (I/O) immediate address (0 - 65,535)

src Source accumulator or B d st Destination accumulator ( or B)

lk 16-bit lon


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Immediate Addressing ModeImmediate Addressing Mode ##

Instruction contains the value of theInstruction contains the value of theoperand. Value is preceded b yoperand. Value is preceded b y #.#.Example:Example:

Add the value 4 to the content of Add the value 4 to the content of accumulator A.accumulator A.

Useful for initializations.Useful for initializations.Long (16 b its) or short values:Long (16 b its) or short values:

For long values: instruction uses 2 words.For long values: instruction uses 2 words.

ADD ADD #4,A #4,A


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Immediate Addressing ModeImmediate Addressing Mode ##

16 b it value16 b it value2 words, 2 cycles2 words, 2 cyclesInitialization of Initialization of ARiARi forforexampleexample

Short valueShort value3, 5, 8, 9 b its constant3, 5, 8, 9 b its constant1 word, 1 cycle1 word, 1 cycleTo initialize shortTo initialize shortlength registers or b itlength registers or b itfields:fields:

DP, ASM DP, ASM

Not always availa b leNot always availa b le

Example:ST M #1234h,AR2Load AR2 with the value1234h.

Example:

LD #6, DPLoad DP with the value 6.


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ExampleExample: : MMR MMR (Memory Mapped Registers)(Memory Mapped Registers)and Immediate Addressingand Immediate Addressing

STM (STore to Memory-mapped

register) stores an immediatevalue to the specified MMR orScratch address.

#tbl is the 16- b it address of thefirst element of the array tbl .



.sect code

start: ST M #tbl,AR1ST M #x,AR2

0000

0060

007

s

cratc

MMR = Memory Mapped Registers

S cratch memory


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Direct Addressing ModeDirect Addressing Mode @@

Direct addressing = random access fromDirect addressing = random access froma specified base address.a specified base address.The instruction contains an offset relativeThe instruction contains an offset relativeto the base address.to the base address.

The base address can be the b eginningThe base address can be the b eginningof a data memory page or the stack of a data memory page or the stack pointer.pointer.

The data memory is virtually divided inThe data memory is virtually divided in512512 pages of 128 wordspages of 128 words (512x128 = 2(512x128 = 2 1616))..

Data PageData Page DPDP relative direct addressrelative direct addressCPL bit (ComPiler Mode b it) = 0 in ST1CPL bit (ComPiler Mode b it) = 0 in ST1

Stack PointerStack Pointer SPSP relative direct addressrelative direct address

CPL bit = 1 in ST1CPL bit = 1 in ST1


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Data memory pagesData memory pages

Page 0

Data memorye

0000

0080

0100

Add resses i Dec

0

128

256

65 535

Page 1

Page 2

Page 511

128 or d s

128 or d s

128 or d s

128 or d s

512 Pages


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For DP relative mode:For DP relative mode:The 16 b it address is split into 9 MSB andThe 16 b it address is split into 9 MSB and7 LSB.7 LSB.

The 7 LSB of the operand address are givenThe 7 LSB of the operand address are givenin the instructionin the instruction, ,

The 9 MSB are in the DP registerThe 9 MSB are in the DP register. .

For SP relative modeFor SP relative modeThe 7 bits given in the instruction areThe 7 bits given in the instruction areused as an offset from the SP to o b tainused as an offset from the SP to o b tainthe addressthe address. .

In b oth cases, only 7 b its are used inIn b oth cases, only 7 b its are used inthe instruction for the operandthe instruction for the operand

address.address.


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O pcode I=0 dma

15 - 8 7 6 - 0

7-b it dma9-b it DP

InstructionInstruction

DP relative, CPL = 0DP relative, CPL = 0

AddressAddress

SP relative, CPL = 1SP relative, CPL = 1

16- b it Stack Pointer

7-b it dma+

16- b it Data Memory AddressAddressAddress

9-b it DPDP registerDP register

SP RegisterSP Register


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Direct Addressing ModeDirect Addressing Mode @@, example, example

Page 0

Data memoryex

0000

0080

0100

Addresses in Dec

0

128

256

65 535

Page 1

Page 2

Page 511

128 ords

128 ords

128 ords

128 ords

01

127

Page 3 to 510

DP = 2DP = 2, page 2, page 2

O ffset in theO ffset in theinstruction =instruction = 1 1

Address = 0101Address = 0101in hexadecimalin hexadecimal


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ExampleExample

This instruction loads the upper9 b its of address x into DP (in ST0)

CPL = 0

To be sure that x and x+1 are in thesame page: use Blocking.

LD @x+1,A ADD @x,A ADD @x+2,A



.sect code

start: ST M #tbl,AR1ST M #x,AR2

LD #x,DP


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Direct Addressing ModeDirect Addressing Mode @, DP relative@, DP relative

When DP is initialized, it allows singleWhen DP is initialized, it allows single- -word singleword single- -cycle instructions with easycycle instructions with easyto understand sym bols for addresses.to understand sym bols for addresses.Defines 512 pages (selected b y the 9 b itsDefines 512 pages (selected b y the 9 b itsof DP) of 128 words (selected b y the 7of DP) of 128 words (selected b y the 7

b its in instruction) in data memory.b its in instruction) in data memory.CPL is reset b y:CPL is reset b y:

RSB X CPL ; CPL = 0 on resetRSB X CPL ; CPL = 0 on reset

BlockingBlocking of data in the same pageof data in the same pageIn the linker command file:In the linker command file:

.bss : > RAM BL O CK = 128.bss : > RAM BL O CK = 128

In the assem bler fileIn the assem bler file.bss x, 2,.bss x, 2, 11 ; specify all varia b les in one page; specify all varia b les in one page


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Direct Addressing ModeDirect Addressing Mode @, SP relative@, SP relative

Used by the C compilerUsed by the C compilerUseful for stack b ased operationsUseful for stack b ased operationsControlled by the CPL b it. Set b y:Controlled by the CPL b it. Set b y:

SSB X CPLSSB X CPL


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Indirect Addressing ModeIndirect Addressing Mode *ARi*ARi

Compati b le withCompati b le with pointerspointers in C.in C.8 ARi8 ARi Auxiliary Registers to store theAuxiliary Registers to store theaddresses of the operands.addresses of the operands. They areThey areused as pointers.used as pointers.

2 ARAU2 ARAU = Auxiliary Registers= Auxiliary RegistersArithmetic Units to realize operationsArithmetic Units to realize operationson the addresses stored in the ARi.on the addresses stored in the ARi.1 operand (Smem) or 2 operands1 operand (Smem) or 2 operands(Xmem, Ymem) can b e specified b y(Xmem, Ymem) can b e specified b yindirect addressing in 1 instruction.indirect addressing in 1 instruction.Very efficient for DSP operations.Very efficient for DSP operations.


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Indirect addressing modeIndirect addressing mode *ARi*ARi

AR0AR0 can be used as an index.can be used as an index.Support forSupport for circularcircular addressingaddressing

details in next slidesdetails in next slides

Bit ReversedBit Reversed BR BR addressing for FFTaddressing for FFTARi can b e modified during theARi can b e modified during theinstructioninstruction

The possi b le modifications or operations onThe possi b le modifications or operations on

ARi depend on the num ber of operandsARi depend on the num ber of operandsspecified by indirect addressing in thespecified by indirect addressing in theinstruction.instruction.

Pointers (ARi) must b e initialized beforePointers (ARi) must b e initialized before

use.use.


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Circular buffer and addressing on C54xCircular buffer and addressing on C54x

Data Memo ryStart_address =

xxxxxxxxxxx00000

ARi

End_address =xxxxxxxxxxx11111

00010

AR i BK

N= 0=1 1 1 1 0


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Circular addressing with C54xCircular addressing with C54xCircular indirect addressing mode:Circular indirect addressing mode: %%

*ARi*ARi--%, *ARi+%, *ARi%, *ARi+%, *ARi- -0%, *ARi+0%,0%, *ARi+0%,*ARi(lk)%*ARi(lk)%In dual operand mode Xmem, Ymem:In dual operand mode Xmem, Ymem:

*ARi+0%*ARi+0% only valid modeonly valid modeTo perform a decrement, store a negative valueTo perform a decrement, store a negative valuein AR0.in AR0.

BK BK register:register:Stores the size N of the circular buffer.Stores the size N of the circular buffer.Must be initialized before use.Must be initialized before use.There may be several circular buffers atThere may be several circular buffers atdifferent addresses at the same time butdifferent addresses at the same time but

with the same length.with the same length.


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Limitations on Start Addresses of CircularLimitations on Start Addresses of CircularBuffersBuffers

If N is written on n b b its in b inary, theIf N is written on n b b its in b inary, thestart address must have its n b LSB at 0:start address must have its n b LSB at 0:Examples:Examples:

for N=32, 6 LSB of start address =0for N=32, 6 LSB of start address =0

for N=30, 5 LSB of start address =0for N=30, 5 LSB of start address =0

To access a circular buffer:To access a circular buffer:Initialize BK with N (n b b its)Initialize BK with N (n b b its)

Choose 1 ARi as a pointerChoose 1 ARi as a pointerThe effective start address of the buffer is theThe effective start address of the buffer is thevalue in ARi with its n b LSB at 0.value in ARi with its n b LSB at 0.

The end address = start addess +NThe end address = start addess +N- -1.1.


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Indirect Addressing:Indirect Addressing: ARi Specifications andARi Specifications andO ptions for ModificationO ptions for Modification

For a single operand Smem:For a single operand Smem:16 possi b le options for Smem,16 possi b le options for Smem,4 bits for the option + 3 b its for the ARi.4 bits for the option + 3 b its for the ARi.

The address is specified by 4 + 3 = 7 b its.The address is specified by 4 + 3 = 7 b its.For 2 operands Xmem, Ymem:For 2 operands Xmem, Ymem:

O nly 4 ARi can be used: AR2 to AR5.O nly 4 ARi can be used: AR2 to AR5.O nly 4 possi b le options for the operationsO nly 4 possi b le options for the operationson the ARi.on the ARi.Each address needs 2 + 2 = 4 b its, so 2x4=8Each address needs 2 + 2 = 4 b its, so 2x4=8bits are necessary for the 2 addresses.b its are necessary for the 2 addresses.


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Indirect Addressing O ptions forIndirect Addressing O ptions for ARiARimodifications,modifications, Single operand SmemSingle operand Smem

o odification *ARn no modification to ARn

O ption Synta Action Affected by:

Absol te *(lk) 16-bit lk is sed as an absol te addressSee Absol te Addressing

P re-modify *ARn (lk) *(ARn ), ARn nc anged* ARn (lk) *(ARn ), ARn c anged* ARn (lk) *(ARn ), ARn c anged - circ lar* ARn pre-increment by 1, d ring rite only

it-Reversed *ARn 0 post inc. ARn by AR0 it reverse carry AR0*ARn-0 post dec. ARn by AR0 i t reverse carry ( size/2)

irc lar *ARn post increment by 1 - circ lar*ARn - post decrement by 1 - circ lar*ARn 0 post increment by AR0 - circ lar , AR0*ARn-0 post decrement by AR0 - circ lar

Inde ed *ARn 0 post increment by AR0 AR0*ARn-0 post decrement by AR0

Increment / *ARn post increment by 1ecrement *ARn- post decrement by 1


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Indirect Addressing O ptions forIndirect Addressing O ptions for ARiARifor Dou b le O perand Xmem and Ymemfor Dou b le O perand Xmem and Ymem

o odification *ARn no modification to ARn

O ption nta Action Affected b :

ircular *ARn 0 post increment by AR0 - circular , AR0

Increment / *ARn post increment b y 1Decrement *ARn- ost decrement b 1


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Indirect Addressing ModeIndirect Addressing Mode *ARi*ARi

There are latencies to consider:There are latencies to consider:no latencyno latency STM, MVDK STM, MVDK

1 cycle1 cycle MVDM, MVKD, MVDDMVDM, MVKD, MVDD2 cycles2 cycles STLM, ST, etcSTLM, ST, etc

ARi are read/modified in access phase, so theARi are read/modified in access phase, so thede bugger will appear to show ARs changing early.de bugger will appear to show ARs changing early.CMPT must = 0 ( b it5, ST1)CMPT must = 0 ( b it5, ST1)

is 0 on resetis 0 on resetis forced to 0 with RSB X CMPTis forced to 0 with RSB X CMPT

CMPT (Compati b ility Mode Bit) = 1 allowsCMPT (Compati b ility Mode Bit) = 1 allowsC2x/C2xx/C5x styled ARP operation for ARs.C2x/C2xx/C5x styled ARP operation for ARs.But this mode is discouraged.But this mode is discouraged.


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ExampleExample

Initialization of AR1 and AR2.

Copy the values from ta b le in DR O Mto RAM (via A). Indirect addressingallows sequential access to data.

RAM x[3]

RAM y

54xCPU

System Diagram

DROM tbl[3]

EPROM code



.sect codestart: ST M #tbl,AR1

ST M #x,AR2

LD @x+1,A

ADD @x,A ADD @x+2,A

LD #x,DP

LD *AR1+,A ST L A,*AR2+ ;...


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Ab solute Addressing ModeAb solute Addressing Mode *()*()

Allows us to specify a complete operandAllows us to specify a complete operandaddress in an instruction.address in an instruction. *(Address)*(Address)The address can b e in data, program orThe address can b e in data, program orIO memory. 16 b its.IO memory. 16 b its.

2 words, 2 cycles.2 words, 2 cycles. Data MemoryAddr Data

. .

. .x: 01FF 1000

y: 0200 0500. .. .

0 0 0 0 0 0 1 0 0 0 Acc A 0 0 0 0 0 0 1 5 0 0

.datax: .word 1000h

y: .word 0500h.textLD *(x),A

ADD *(y),A


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ExampleExample

RAM x[3]

RAM y

54xCPU

System DiagramDROM

tbl[3]

EPROM code

Save accumulator A at address y

X .usect "vars",3Y .usect "result",1

.sect init"

tbl .int 1,2,3

.sect codeS tart: ST M #tbl,AR1

ST M #x,AR2

LD @x+1,A ADD @x,A ADD @x+2,A

LD #x,DP

LD *AR1+,A ST L A,*AR2+ ;...

ST L A,*(y)


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MMR Memory Mapped RegistersMMR Memory Mapped Registers AddressingAddressingMMRs are in page 0 of data memory.MMRs are in page 0 of data memory.

They can be accessed by some specific MMR They can be accessed by some specific MMR instructions allowing simple access to page 0.instructions allowing simple access to page 0.In these cases DP, SP and CPL are ignoredIn these cases DP, SP and CPL are ignored

0000h

0060h

007Fh

MMRs

Scratch

Tip: use the .mmregs directiveto allow MMR names to beinterpreted as addresses

LDM, ST LM MMR m AccST M # p MMR PSH M, POPM MMR m S tack

MVDM, MVMD MMR m Dmem MVMM AR,S P m AR, S P


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MMR Memory Mapped RegistersMMR Memory Mapped Registers

Addr.

Name (Hex) DescriptionIMR 0000 Interrupt Mask Register

IFR 0001 Interrupt Flag Register

----- 2 - 5 Reserved

ST0 0006 Status 0 Register

ST1 0007 Status 1 Register

AL 0008 A accumulator low (A[15:00])AH 0009 A accumulator high (A[31:16])

AG 000A A accumulator guard (A[39:32])

BL 000B B accumulator low (B[15:00])

BH 000C B accumulator high (B[31:16])

BG 000D B accumulator guard (B[39:32])

T 000E Temporary Register

TRN 000F Transition Register

Addr.

Name (Hex) DescriptionAR0 0010 Address Register 0

AR1 0011 Address Register 1




AR5 0015 Address Register 5AR6 0016 Address Register 6


SP 0018 Stack Pointer Register

BK 0019 Circular Size Register

BRC 001A Block Repeat Counter

RSA 001B Block Repeat Start Address

REA 001C Block Repeat End Address

PMST 001D PMST Register

------- 01E-01F Reserved

Note: XPC and Peripheral MMR locations are device dependent


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Exercise on Addressing Modes of C54xExercise on Addressing Modes of C54xGiven : DP=0 DP=4 DP=6Address/Data (HE X) 60 20 200 100 300 100CPL=0 61 120 201 60 301 30

CMPT=0 62 202 40 302 60

Program A B DP AR0 AR1 AR2LD #0,DPST M #2,AR0ST M #200h,AR1ST M #300h,AR2LD @61h,A

ADD *AR1+,A S UB @60h,A,B

ADD *AR1+,B,A LD #6,DP

ADD @1,A

ADD *AR2+,A S UB *AR2+,A S UB #32,A

ADD *AR1-0,A,BS UB *AR2-0,B,A ST L A,62h

120

260

390

380

Addr Mode


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Exercise on Addressing Modes of C54xExercise on Addressing Modes of C54xGiven : DP=0 DP=4 DP=6Address/Data (HE X) 60 20 200 100 300 100CPL=0 61 120 201 60 301 30CMPT=0 62 202 40 302 60

Program A B DP AR0 AR1 AR2 LD #0,DPST M #2,AR0ST M #200h,AR1ST M #300h,AR2LD @61h,A

ADD *AR1+,A S UB @60h,A,B

ADD *AR1+,B,A LD #6,DP

ADD @1,A ADD *AR2+,A

S UB *AR2+,A S UB #32,A

ADD *AR1-0,A,BS UB *AR2-0,B,A ST L A,62h

Addr Mode

120

260

390

380

IMMED 0 MMR MMR MMR DIRECT

INDIREC T 220 201DIRECT 200

INDIREC T 202IMMED 6DIRECT 290

INDIREC T 301INDIREC T 360 302

IMMED 340INDIREC T 200INDIRECT 320 300

DIRECT


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C55x Addressing ModesC55x Addressing Modes


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Format of Data and Instructions, InternalFormat of Data and Instructions, InternalBusses for the C55x FamilyBusses for the C55x Family

Unified programUnified program- -data memory map:data memory map:b yteb yte--aligned for program and wordaligned for program and word- -aligned for data.aligned for data.Has a varia b le length instruction set (8Has a varia b le length instruction set (8- -1616--2424--3232--4040--48 b its).48 b its).

Program address bus: 24 b its, 16 M bytesProgram address bus: 24 b its, 16 M bytes4 instructions bytes are fetched at a time4 instructions bytes are fetched at a time6 bytes are decoded at a time6 bytes are decoded at a time

Internal data b usses: 3 data read, 2 dataInternal data b usses: 3 data read, 2 datawritewriteData addresses: 8 Mwords of 16 b itsData addresses: 8 Mwords of 16 b itssegmented into 64K pages,segmented into 64K pages, 2323--b it address.b it address.A 24A 24--b it address is automatically generatedb it address is automatically generatedby the hardware by adding a LSB = 0.by the hardware by adding a LSB = 0.


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C55x Addressing ModesC55x Addressing ModesDirectDirect

IndirectIndirectAb soluteAb soluteMMR MMR

Loading constants in registers (e.g.Loading constants in registers (e.g.immediate)immediate)

y = x0 + xy = x0 + x11 + x+ x22

AlgorithmAlgorithm

RAM RAM x[x[33]]

RAM RAM yy

II PPDD A A

55xx55xxCPUCPU

System DiagramSystem Diagram

ROM ROM tbl[tbl[3 3]]

y = x0 + xy = x0 + x11 ++xx22

This algorithm will again be usedThis algorithm will again be usedas an example for the differentas an example for the differentaddressing modes.addressing modes.


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Loading Constants in RegistersLoading Constants in Registers ##

Used for initialization of registers.Used for initialization of registers.Used to be called immediate addressingUsed to be called immediate addressing

Addressing registers:Addressing registers:1616--b its long:b its long: ARi, DP, CDP (CoefficientARi, DP, CDP (CoefficientData Pointer)Data Pointer)2323--b its long:b its long: XARi, XDP, XCDPXARi, XDP, XCDPThe 7 MSB of Xreg specify the 64K page.The 7 MSB of Xreg specify the 64K page.

TheThe ARAUARAU auxiliary Registerauxiliary RegisterArithmetic Unit is 16 b its wide: updateArithmetic Unit is 16 b its wide: updateof ARi and CDP are done modulo 64K.of ARi and CDP are done modulo 64K.Initialization example:Initialization example: AMOV AMOV #adr, X AR3#adr, X AR3


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ExampleExamplexx .usect vars,4.usect vars,4yy .usect vars,1.usect vars,1

.sect init.sect inittbltbl .int 1,2,3,4.int 1,2,3,4

.sect code.sect code

indir: AMOV #x, X AR0indir: AMOV #x, X AR0

AMOV #tbl, X AR6 AMOV #tbl, X AR6

RAM RAM x[x[33]]

RAM RAM yy

II PPDD A A

55xx55xxCPUCPU

ROM ROM tbl[tbl[3 3]]

y = x0 + xy = x0 + x11 ++xx22

== 2323--b it addressb it address

1616--b it ARnbit ARn2323--b it XARnbit XARn

XX


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Gives the instruction a positive 7 b itGives the instruction a positive 7 b itoffset from DP (nonoffset from DP (non- -aligned).aligned).

In the case where the b it CPL=0 in ST1.In the case where the b it CPL=0 in ST1.Calculation in the ARAU modulo 64K Calculation in the ARAU modulo 64K

77--b it @xbit @x

==

++2323--b it addressb it address

1616--b it DPbit DP2323--b it XDPbit XDP

XX


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ExampleExamplexx .usect vars,4.usect vars,4yy .usect vars,1.usect vars,1

.sect init.sect inittbltbl .int 1,2,3,4.int 1,2,3,4

.sect code.sect code

How is XDP initialized?How is XDP initialized?

RAM RAM

x[x[33]]RAM RAM

yy

II PPDD A A

55xx55xxCPUCPU

ROM ROM

tbl[tbl[3 3]]

y = x0 + xy = x0 + x11 ++xx22

ADD: MOV @(x+0),AC0 ADD @(x+1),AC0 ADD @(x+2),AC0


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ExampleExample

Constant value containedConstant value contained

in instruction opcodein instruction opcode((--x)x) used in instruction to tellused in instruction to tellthethe assem blerassem bler H O W to create theH O W to create the77--b it offset from nonb it offset from non- -aligned XDPaligned XDP

A in AM O V means in ADA in AM O V means in AD- -phase.phase.

The MDP has to be reloadedThe MDP has to be reloadedevery time we cross a 64K page.every time we cross a 64K page.

dir: AMOV #x, DP

x .usect vars,4y .usect vars,1

.sect inittbl .int 1,2,3,4

.sect code

ADD: MOV @(x+0-x),AC0 ADD @(x+1-x),AC0 ADD @(x+2-x),AC0


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DirectiveDirective .dp.dp for Direct Addressingfor Direct Addressing

Instead of using (Instead of using (- -x) to help the assem blerx) to help the assem blercalculate the proper 7calculate the proper 7- -b it offset,b it offset,We can use the directiveWe can use the directive .dp.dp to set the base addressto set the base addressfor the assem bler calculation of the 7for the assem bler calculation of the 7- -b it offset.b it offset.

.dp base_address.dp base_address

The @addr in the instruction isThe @addr in the instruction isinterpreted as a 23interpreted as a 23- -b it address.b it address.

The .dp provides a compileThe .dp provides a compile- -timeb

asetimeb

aseaddress.address.

The assem bler determines the 7The assem bler determines the 7- -b itb itoffset by: (@addroffset by: (@addr- -.dp_value)&7F.dp_value)&7F

.dp xdir: AMOV #x, XDP



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I di Add i O i f P iI di Add i O i f P i ARiARi


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Indirect Addressing O ptions for PointerIndirect Addressing O ptions for Pointer ARiARiModificationsModifications

Assumes ST2_55Assumes ST2_55 ARMSARMS =0 and ST1_55=0 and ST1_55 C54CMC54CM =0.=0.

The reset condition is C54CM=1.The reset condition is C54CM=1.

*ARn( T 0/1) No Modify w/offset *ARn(#k16) No Modify w/offset

*(ARn +/- T 0/1) Post Modify (+/- by T0/1)

*+/- ARn (+/-) Pre Modify *+ ARn(#k16) (+ #k16) Pre Modify *(ARn +/- T 0B) Bit reversed using T0*CDP No Modify *CDP(#k16) No Modify w/offset *CDP +/- Post Modify (+/-) *+CDP(#k16) (+ #k16) Pre Modify

*ARn No Modify

*ARn + /- Post Modify (+ /-)


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Address Register Mode Select Bit ARMSAddress Register Mode Select Bit ARMS

ARMS b it = b it 15 of ST2_55ARMS b it = b it 15 of ST2_55ARMS=0 at reset DSP modeARMS=0 at reset DSP modeFor ARMS=1, C O NTR O L modeFor ARMS=1, C O NTR O L mode

T1 cannot be used as offsetT1 cannot be used as offsetNo bit reversed addressingNo bit reversed addressingNew mode:New mode:

*ARi(short(#k3))*ARi(short(#k3)) oror *SP(short(#k3))*SP(short(#k3))

Useful for the C compilerUseful for the C compilerThe C compiler sets ARMS = 1.The C compiler sets ARMS = 1.


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Modifying TAs RegistersModifying TAs Registers

TAx registers = T0TAx registers = T0- -3, AR03, AR0--77..Special instructions:Special instructions:

AAADD,ADD, AASUB,SUB, AAM O VM O VCan be used to modify TAs registersCan be used to modify TAs registersduring the address (AD) phase of theduring the address (AD) phase of thepipeline, while instructions without Apipeline, while instructions without Aoperates during the execution ( X) phase.operates during the execution ( X) phase.They only work on the TAx registers.They only work on the TAx registers.

ExamplesExamples: : AADD #const,AR1 A S UB AR1, T 0 AMOV #k23, X AR2


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ExampleExample

+ ++ +

RAM RAM x[4]x[4]

RAM RAM yy

II PPDD A A

55xx55xxCPUCPU

ROM ROM tbl[4]tbl[4]

y = x0 + xy = x0 + x11 ++x1x1

x .usect vars,4y .usect vars,1


.sect code

.dp x

dir: AMOV #x, XDP


indir: AMOV #x, X AR0

AMOV #tbl, X AR6

COPY: MOV *AR6+, AR0+ MOV *AR6+,*AR0+ MOV *AR6 ,*AR0


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Circular Buffer Addressing ModeCircular Buffer Addressing Mode

== Buffer Start Address

== Buffer Length BKzz[15:0]

O ffset into Buffer ==

BS Axx[15:0] Xeven[22:16]

== Calculated Address BS Axx + ARn/CDP Xeven[22:16] ARn/CDP++


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Circular Buffer Addressing ModeCircular Buffer Addressing Mode

Offset Xeven

Buffer

StartAddress

Block sizeRegister

AR0AR1AR2AR3AR4AR5AR6AR7CPD XCDP[22:16] BSAC BKC

XAR0[22:16]

XAR2[22:16]

XAR4[22:16]

XAR6[22:16]

BK03

BK03

BSA01

BSA01

BSA01

BSA01

The even XARn (i.e. 0,2,4,6) determines the 64K PageThe even XARn (i.e. 0,2,4,6) determines the 64K Page

S l ti g Ci l Li Add i gS l ti g Ci l Li Add i g


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Selecting Circular or Linear AddressingSelecting Circular or Linear AddressingModeMode

Use the LSB of Status word ST2_55Use the LSB of Status word ST2_55

00 lliinn eeaa rr mm oodd ee 11 cciirr cc llaa rr mm oodd ee

22 _ _ 5555

AAR R 77

AAR R 66

AAR R 55

AAR R 44

AAR R 33

AAR R 22

AAR R 11

AAR R 00

PPLL

CC

oo t t hh ee r r bb i i t t ss oo r r r r ss vv d d

00 11 22 33 44 55 66 77 88 99 1155

dd eef f aa lltt

Set or resetSet or reset statusstatus b its:b its: BBSS EETT A A R R 55 LLCC ;; A A R R 55 ii nn cc ii rr cc uu ll aa rr m m oo d d ee BBCCLLR R A A R R 33 LLCC ;; A A R R 33 ii nn ll ii nn ee aa rr m m oo d d ee

ffff


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Circular Buffer ExerciseCircular Buffer ExerciseUse AR4 as a circular pointer to x{5}:Use AR4 as a circular pointer to x{5}:

AA R R 44 77 11 99 66

22

00 11

22

33

44

xx

AA R R 44

..sect datax .int 7,1,9,6,2 ;init data

.sect code __________________ ;init AR

__________________ ;init start addr __________________ ;init length __________________ ;init AR4 to top __________________ ;set AR4 to circ

MOV #3,T0 ;index

MOV *(AR4+T0),AC0 ;AC0=

_ _ 7 __, AR4=

_ 3 _ _ _ _ MOV *+AR4(#4h),AC1 ;AC1 = _ 9 __, AR4 = _ 2 _ _ _ _ MOV *AR4(T0),AC2 ;AC2 = _ 7 __, AR4 = _ 2 __

AMOV #x, AR4

MOV #x,BSA45 MOV #5,BK47 MOV #0,AR4

BSET AR4LC

R esults areR esults arecumulativecumulative

Comparison of C54x andComparison of C54x and C55x circularC55x circular


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Comparison of C54x andComparison of C54x and C55x circularC55x circularaddressing modesaddressing modes

3 BK registers in C55 X instead of 1 in3 BK registers in C55 X instead of 1 inC54x: allows for several simultaneousC54x: allows for several simultaneouscircular b uffers with different size.circular b uffers with different size.In C54x, circular addressing mode isIn C54x, circular addressing mode isspecified in indirect addressing type %specified in indirect addressing type %in the instructionsin the instructions. .In C55x, the mode in set in statusIn C55x, the mode in set in statusregister ST2_55 for each register (linearregister ST2_55 for each register (linearor circular).or circular). No memory alignmentNo memory alignmentconstraint.constraint.

Ab l Add iAb l Add i ( )( )


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Ab solute AddressingAb solute Addressing *(#)*(#)

*(#)*(#) = 23 b it address= 23 b it addressFast: no initialization,Fast: no initialization,But long instruction b ecause it containsBut long instruction b ecause it containsthe 23 b it address.the 23 b it address.If the address is in the 64K work page, itIf the address is in the 64K work page, itis possi b le to specify a 16is possi b le to specify a 16- -b it onlyb it onlyaddress:address:

abs16*(#la bel)abs16*(#la bel)

E lE l


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ExampleExample

RAM RAM

x[4]x[4]

RAM RAM yy

II PPDD A A

55xx55xxCPUCPU

ROM ROM

tbl[4]tbl[4]

y = x0 + xy = x0 + x11 ++x2x2

X .usect vars,4Y .usect vars,1


.sect code

.dp x

dir: AMOV #x, XDP


indir: AMOV #x, X AR0 AMOV #tbl, X AR6

COPY: MOV *AR6+,*AR0+ MOV *AR6+,*AR0+ MOV *AR6 ,*AR0

ST ORE: MOV AC0,*(#y)

MMR Add i U i ()MMR Add i U i ()


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MMR Addressing Using mmap()MMR Addressing Using mmap()

MMRs are located b etween 0 and 5F.MMRs are located b etween 0 and 5F.Scratch memory is located b etween 60Scratch memory is located b etween 60and 7F.and 7F.mmap() forces b its 22:7 to zero.mmap() forces b its 22:7 to zero.

Useful to access MMR and scratch memoryUseful to access MMR and scratch memorywithout initialization of addressingwithout initialization of addressingregisters.registers.

Useful only for direct addressing.Useful only for direct addressing. ; write #1234h to ST0_55

AMOV #0, XDP MOV #1234h, @( ST 0_55 - 0)

; write #1234h to ST0_55 MOV #1234h, mmap(@ ST 0_55)

A P i h l R iA P i h l R i


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Access Peripheral RegistersAccess Peripheral Registers

The I /O space is internal.The I /O space is internal.The PDP (Peripheral Data Pointer)The PDP (Peripheral Data Pointer)register is used to access ports usingregister is used to access ports usingdirect addressing.direct addressing.

I t is a 9 bit register. I ts value isI t is a 9 bit register. I ts value isconcatenated with the 7 b its in theconcatenated with the 7 b its in theinstruction to o b tain a full 16instruction to o b tain a full 16- -b itb itperipheral address.peripheral address.

The port() modifier selects theThe port() modifier selects theperipheral mapperipheral map

A P i h l R i tA P i h l R i t


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Access Peripheral RegistersAccess Peripheral Registers

0000h0000h

FFFFhFFFFh

I /O I /O -- PeripheralPeripheralMemory MapMemory Map

DMADMA

McBSPMcBSP

EHP IEHP I

EM IFEM IFTimersTimers

Power DwnPower Dwn

Instr CacheInstr Cache

GP IOGP IO

abs: MOV port(#addr), T 1abs: MOV port(#addr), T 1

dir: MOV #addr,PDPdir: MOV #addr,PDP MOV T 1,port(@addr) MOV T 1,port(@addr)

indir: AMOV #addr,AR4indir: AMOV #addr,AR4 MOV port(*AR4), T 1 MOV port(*AR4), T 1

Di ti f Add i M dDi ti f Add i M d


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Directives for Addressing ModesDirectives for Addressing Modes

3 Mode b its affect addressing:3 Mode b its affect addressing:ARMS: Address Register Mode SelectARMS: Address Register Mode SelectC54CM: C54 Compati b ility ModeC54CM: C54 Compati b ility Mode

C54CM=1 on reset, native C55x codingC54CM=1 on reset, native C55x coding

requires C54CM=0.requires C54CM=0.CPL: ComPiLer ModeCPL: ComPiLer Mode

3 directives help the assem b ler to check 3 directives help the assem b ler to check the syntax and responds with ERR O R the syntax and responds with ERR O R in case of inconsistency:in case of inconsistency:

.arms_on.arms_on or .arms_off or .arms_off

.c54cm_on.c54cm_on or .c54cm_off or .c54cm_off

.cpl_on.cpl_on or .cpl_off or .cpl_off

M dif i St t BitM dif i St t Bit


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Modifying Status BitsModifying Status Bits

BCLR BCLR ARM S ARM S ;clear;clear ARM S ARM S

BS ET BS ET CPLCPL ;set;set CPLCPL

BCLR C54CM BCLR C54CM ;clear C54CM ;clear C54CM

BS ET /BCLR bit_nameBS ET /BCLR bit_name

Add i g E iAdd i g E i


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Addressing ExerciseAddressing Exercise02_0105h02_0105h 21h21h

x = 02_0106hx = 02_0106h02_0107h02_0107h02_0108h02_0108h

02_0206h02_0206h

XDPXDP

TheThe initialinitial state of state of eacheach instruction isinstruction isshown here...shown here...

Below, write downBelow, write downthe statethe state afterafter each instreach instr

30h30h

40h40h50h50h60h60h

X AR1X AR1

T 0T 0 22

02_0106h02_0106h

02_0106h02_0106h

.dp x.dp x

AR1 AC0 T 1 02_0106h ST 1 M40

MOV @(x+1),AC0

MOV @(x+80h),AC0 MOV T 0,*AR1+ MOV *(#x),AC0 MOV #4,@(x+128) MOV *(AR1+T 0), T 1

BS ET M40

MOV @(x+2),AC0 MOV *AR1(T 0),AC0 MOV *AR1(#100h), T 1 MOV @(x+129),AR1 MOV *+AR1(#-1),AC0

Add i g E iAdd i g E i S l tiS l ti


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Addressing ExerciseAddressing Exercise SolutionSolution02_0105h02_0105h 21h21h

x = 02_0106hx = 02_0106h02_0107h02_0107h02_0108h02_0108h02_0206h02_0206h

XDPXDP

TheThe initialinitial state of state of eacheach instruction isinstruction isshown here...shown here...

Below, write downBelow, write downthe statethe state afterafter each instreach instr

30h30h40h40h50h50h60h60h

X AR1X AR1

T 0T 0 22

02_0106h02_0106h

02_0106h02_0106h

.dp x.dp x

AR1 AC0 T 1 02_0106h ST 1 M40

MOV @(x+1),AC0

MOV @(x+80h),AC0 MOV T 0,*AR1+ MOV *(#x),AC0 MOV #4,@(x+128) MOV *(AR1+T 0), T 1

BS ET M40

MOV @(x+2),AC0 MOV *AR1(T 0),AC0 MOV *AR1(#100h), T 1 MOV @(x+129),AR1 MOV *+AR1(#-1),AC0

40h

30h107h 230h

4108h 30h

1

50h106h 50h106h 60h

40h105h 21h


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Circular buffer and circular addressingCircular buffer and circular addressing


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Circular buffer and circular addressingCircular buffer and circular addressing

A circular b uffer of length N is a b lock A circular b uffer of length N is a b lock of contiguous memory words addressedof contiguous memory words addressedb y a pointer using a modulo Nb y a pointer using a modulo Naddressing mode.addressing mode.

The 2 extreme words of the memory b lock The 2 extreme words of the memory b lock are considered as contiguous.are considered as contiguous.

Characteristics of a circular b uffer:Characteristics of a circular b uffer:Instead of moving the N data in memory,Instead of moving the N data in memory,

just modify the pointers. just modify the pointers.When a new data x(n) arrives, the pointerWhen a new data x(n) arrives, the pointeris incremented and the new data is writtenis incremented and the new data is writtenin place of the oldest one.in place of the oldest one.

Trace of Memory and Pointer in a CircularTrace of Memory and Pointer in a Circular


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Trace of Memory and Pointer in a CircularTrace of Memory and Pointer in a CircularBuffer of Length 3Buffer of Length 3

Time n Time n+ Time n+2 Time n+3

x(n-1) x(n-1) x(n+2) x(n+2)x(n) x(n) x(n) x(n+3)x(n-2) x(n+1) x(n+1) x(n+1)

Very often used for F IR filters.Very often used for F IR filters.

Documents

Addressing Modes v123