Addressing Challenges in Neuromorphic Computing with Memristive Synapsesornlcda.github.io/neuromorphic2016/presentations/Oak... · 2016-09-13 · ORNL, June 30, 2016 © Vishal Saxena

© 2012 Boise State University 11© Vishal SaxenaORNL, June 30, 2016

Addressing Challenges in Neuromorphic Computing with Memristive Synapses

Vishal Saxena1, Xinyu Wu1 and Maria Mitkova2

1Analog Mixed-Signal and Photonic IC (AMPIC) Lab 2Nanoionic Materials and Devices Lab

ECE Department, Boise State University, ID

http://lumerink.com

2© Vishal SaxenaORNL, June 30, 2016

Agenda

• Introduction

• Synapse Devices and Challenges

• Mixed-Signal Neural Learning Architecture

• Realizing Multibit Synapses

• Conclusion


Reinventing Computing

• Von Neumann computing in the nano-CMOS regime

+ Massive transistor count, but….

– Device variability

– Dark silicon issue

– Not well suited for processing massively parallel data streams and pattern recognition tasks that come easy to a brain.

• US Office of Science and Technology (OSTP) RFI, June 2015:“Create a new type of computer that can proactively interpret and learn from

data, solve unfamiliar problems using what it has learned, and operate with the energy efficiency of the human brain”

DOE, Brain Initiative, AFOSR, DARPA, SRC


Brain-Inspired Neuromorphic System

Our Current Research Focus

Source: DARPA SyNAPSE Program


Revisiting Biological Inspiration

Dendrites

Soma

Axon

Synapse

Synapse

Synapse

Vspk,in

Vmem

Vspk, out

Vmem

Vspk,in

Vthr

tfire

Vspk, out

t1 t2 t3

Vmem

Neuron

Neuron

Neuron

FromPrevious Neurons

A B C

InhibitiveConnection

Δw

0

PrePost

PrePost

Δt<0 Δt>0

Δt = tpost–tpre

Δt Synaptic placiticity

Vspk,in

Vspk, out

• Emerging understanding of neural computation from Computational Neuroscience

– Hierarchical spiking neural networks with localized learning

• Synapses strengthen or weaken by relative firing times of the pre- and post-neurons

– Plasticity rules: Spike-Timing Dependent Plasticity (STDP)


Neuromorphic Computing with RRAMs

Forward spike

Backward spike

Post-synapticneuron

Pre-synapticneuron

ReRAMsynapse

Outp

ut L

aye

r

Input Layer

WTA bus

WTA bus

• To achieve biology-like synapse density, emerging nanoscale devices are under consideration– Resistive RAM (RRAM) or Memristors– Chalcogenide-based Conductive Bridge RAM (CBRAM) devices from Mitkova

Group at Boise State

• Three necessary criterions for the realization of neuromorphic hardware capable of deep learning: (1) non-volatility of the trained weights, (2)massive synaptic density, and (3) ultra-low-power operation.


CBRAM I-V Characteristics

I-V Sweep Resistance


Stochastic CBRAM BehaviorVTH_Set Distributions RON Distributions

• The CBRAM switching behavior is stochastic• The ‘analog’ synapse value depends upon the electroforming process

• Weak bridge-> more intermediate resistance values• The analog resistance value relaxes in few minutes to hours


Spike Timing Dependent Plasticity (STDP)

t

t

t

vp

vn

Vpre

Vpost

tpre tpost

Δt>0

Vnet=Vpost-Vpre

t

t

t

Vpre

Vpost

tpre tpost

Δt<0

Vnet=Vpost-Vpre

Δw or ΔGmr

0

Pre

Post

Pre

Post

Δt<0 Δt>0

Δt = tpost–tpre

Δt

vp

vn

A B

Source: X. Wu, V. Saxena and K. Zhu, “Homogeneous Spiking Neuromorphic

System for Real-World Pattern Recognition”, IEEE Journal on Emerging and

Selected Topics in Circuits and Systems, Accepted.

-4 -2 0 2 4

-0.2

-0.1

0

0.1

0.2

Δt (µs)

ΔG

mr (µ

S)


CBRAM Synapse Challenges

• Variability: Device characteristics such as the switching threshold voltages are variable from device to device

– Switching characteristics depend upon the initial ‘forming’ step and compliance current

• Resistive Load: Thousands of devices in parallel present a difficult (low resistance) load to drive by the neuron circuit

• Resolution: Challenging to realize long-term persistence of weights for more than 1-bit resolution in CBRAM devices


CMOS Integrate and Fire Neuron

WTA Bus

Cmem

Vthr

Vmem

Vrefr

Mleaky

SW1

SW2

Av

SW3

1

Фd=1

Фf=0

1

SpikeGenerator

Vaxon

Vden

Ф1Ф2

Vleaky Vrest

Фi Фf VtchVmode

Фd

Vwtab

Vrst

Vcpr

Фc

Фd=0

Bus Interface

Phase Controller

• Asynchronous integrated and fire operation

• Accommodates RRAM– Provides current summing node– Sustain a fixed voltage for synapses– Dynamic biasing for large current

drive

• STDP compatible– STDP-compatible spike generator– In-situ STDP learning

• Winner-takes-all bus for effective local decision making

• Single contact point to a synapse

Source: X. Wu, V. Saxena and K. Zhu, “Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition”, IEEE Journal on Emerging and Selected Topics in Circuits and

Systems, 5(3), 2015.


Novel Tri-mode Operation

Cmem

Vthr

Vmem

Vrefr

Mleaky

SW1

SW2

Av

SW3

1

Фd=1

Фf=0

1

SpikeGenerator

Vaxon

Vden

Ф1

Ф2

Vleaky Vrest

Фi Фf VtchVmode

Фd

Vwtab

Vrst

Vcpr

Фc

Фd=0

Bus Interface

Phase Controller

Vrefr

A

Av

VrefrVmem

Vrefr

Vthr

Leaky Integrator

Cmem

Vthr

Vmem

Vrefr

Mleaky

SW1

SW2

Av

SW3

Фd=1

Фd=1

0

Фf=1

SpikeGenerator

Vaxon

Vden

Ф1

Ф2

Vleaky Vrest

Фi Фf VtchVmode

Фd

Vwtab

Vrst

Vcpr

Фc

0

Bus Interface

Phase Controller

Vrefr

BVoltage Buffer

Av

Cmem

Vthr

Vmem

Vrefr

Mleaky

SW1

SW2

Av

SW3

Фd=1

Фd=1

Фf=0

1

Vaxon

Vden

Ф1

Ф2

Vleaky Vrest

Фi Фf VtchVmode

Фd

Vwtab

Vrst

Vcpr

Фc

0

Bus Interface

Phase Controller

Vrefr

CDischarging

Av

Vrefr

Vrefr

SpikeGenerator


Systems, 5(3), 2015.

• A first CMOS neuron that is compatible with RRAMs and drives a large load– Several resistive devices in parallel load the neuron


Simulation: Output Spikes

Source: X. Wu, V. Saxena and K. Zhu, “A CMOS Spiking Neuron for Dense Memristor-Synapse Connectivity for Brain-Inspired Computing”, International Joint Conference on Neural Networks

(IJCNN), 2015.

Parameter Symbol Unit Min Max Step

Positive amplitude α+ mV 0 360 24

Negative amplitude α- mV 0 360 24

Positive pulse width τ+ ns 48 396 23

Negative pulse width τ- ns 282 1125 56

Negative pulse slope s mV/ns 0.011 0.52 0.034

Output Spikes

α+

α-

τ+

τ-

slope


Test Chip interfaced with CBRAM Devices

Source: X. Wu, V. Saxena, K. Zhu and S. Balagopal, “A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning”, IEEE

TCAS-II, 62(11), pp.1088-1092.

• Mixed-signal IC with 180-nm CMOS Neurons connected with CBRAM Synapses• A first RRAM compatible STDP learning Neuron• Power consumed in the neuron is 9.3pJ/spike/synapse (in terms of 10,000

synapses each having around 1MΩ resistance).

Pre-spikeVpre

Post-spikeVpost

Net potential across synapse

Vnet = Vpost - Vpre

+Vt,p

-Vt,m

tail-

tail+

Va-

Va+

A B

Δt

Over threshold potential created by STDP spike-pair


Associative Learning Experiment

Source: X. Wu, V. Saxena, K. Zhu and S. Balagopal, “A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning”, IEEE TCAS-II, 62(11),

pp.1088-1092.

Pre-spike

Post-spike

t1

t1+Δt

Post-Neuron

Pre-

Neuron 1

Resistive

Synapses

Outp

ut L

aye

r

Input Layer

Neurons

IFN

#1

IFN

#3

Pre-

Neuron 2

IFN

#2

t2

Pre-Neuron 1(IFN #1)

"Sight of Food"

Pre-Neuron 2 (IFN #2)

"Sound of Bell"

Post-Neuron (IFN #3)

"Salivation"

Time (ms)


Dynamic Resistive Load Driving

0 2 4 6 8 10

0

400

800

1200

1600

Time (us)

Tota

l C

urr

ent (u

A)

10

100

1,000

10,000 1,000 100 10 1

Cu

rre

nt

(µ

A)

Number of Synapses

SynapsesDrivingBaseline

13µA56µA

1,000 Synapses100 Synapses

10,000 Synapses


Systems, 5(3), 2015.

97% Efficiency@ driving 10,000 x

1MΩ synapses


Spike-based Pattern Recognition Circuit

...

Image i×j Input Network

i×j Input Neuron Matrix

i×j×n Synaptic Network

n Output Neurons

WTA


Systems, 5(3), 2015, in press.


Asynchronous WTA Bus Interface

Inhibitory connectionExcitatory connection

Explicit one-one inhibitory connections Implicit inhibition via shared WTA bus

ΦfD

S

Vwtab

Vcpr

Vtch

VmodeΦd

Vrst

Φc

Q

Vdd

DelayTri-state Buffer

Inhibitory connectionExcitatory connection

Explicit one-one inhibitory connections Implicit inhibition via shared WTA bus


Systems, Accepted.

WTA Bus

Cmem

Vthr

Vmem

Vrefr

Mleaky

SW1

SW2

Av

SW3

1

Фd=1

Фf=0

1

SpikeGenerator

Vaxon

Vden

Ф1Ф2

Vleaky Vrest

Фi Фf VtchVmode

Фd

Vwtab

Vrst

Vcpr

Фc

Фd=0

Bus Interface

Phase Controller


Demo: Handwrite Digits Classification

0 100 200 300 400

10

20

30

40

50

60

Input Spike Trains

Neu

ron

#

Time (µs)

0 100 200 300 400

0

1

2

7

Output Spike Trains without Learning

Neu

ron

#

Time (µs)

0 100 200 300 400

0

1

2

7

Output Spikes Train with Learning

Neu

ron

#

Time (µs)

0 1 2 7

Source: X. Wu, V. Saxena and K. Zhu, “Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition”, IEEE Journal on Emerging and Selected Topics

in Circuits and Systems, 5(3), 2015.

Conductance Evolution in Synapses (µS)

10

20

30

40

50

0 1094 2189 3283 4377 5471 6566 7660Time (µs)

0

First 20

Train

(original sequence)

Test

(class-by-class)


Parallel Multibit Synapses

• Emerging spike-based deep learning architectures require at least 4-bits of synaptic resolution.

• The devices fundamentally have bistable nonvolatile states with stochastic switching behavior

• Recent approach: Use several of these device in parallel – Potentially multiple resistance

states due to variation in individual threshold voltages

Output Neuron

Input Layer

Current integration

Compound Multibit

Synapse

Forward

spike

Backward

spikes


Multibit Synapses: Dendritic Processing

• Dendritic processing to include sensitivity to time-overlap between the pre- and post-synaptic spikes

• Shift in time or pulse voltage in the back-propagating spikes

• Simulations exhibit remarkable STDP learning behavior; experiments underway with physical devices

X. Wu and V. Saxena, “Realizing Multibit Synapses with Bistable RRAM Devices”, Unpublished result.


Conclusion

• Nanoscale emerging memory devices present opportunity for realizing non von Neumann computing

• Mixed-Signal architectures for spiking neural networks can realize a versatile neuromorphic computing motif

• Further need to characterize device capabilities and limitations for large scale integration

• Algorithm/architecture development to be driven ground up by emerging device capabilities


References1. X. Wu, V. Saxena and K. Zhu, “Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition”,

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 5(3), 2015, in press.

2. X. Wu, V. Saxena and K. Zhu, “A CMOS Spiking Neuron for Dense Memristor-Synapse Connectivity for Brain-Inspired Computing”, International Joint Conference on Neural Networks (IJCNN), 2015, Accepted.

3. X. Wu, V. Saxena and K. A. Campbell, “Energy-efficient STDP-based learning circuits with memristor synapses”, SPIE Machine Intelligence and Bio-inspired Computation: Theory and Applications VIII, 2014.

4. X. Wu, V. Saxena and K. Zhu, “A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning”, IEEE Transactions on Circuits and Systems II: Express Briefs, In final review.

5. X. Wu and V. Saxena, “Associative Learning on CMOS-Memristor Spiking Neuromorphic Chip”, IEEE Transactions on Nanotechnology, In 2nd round review.


Questions?

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Addressing Challenges in Neuromorphic Computing with Memristive Synapsesornlcda.github.io/neuromorphic2016/presentations/Oak... · 2016-09-13 · ORNL, June 30, 2016 © Vishal Saxena