EE201L - Introduction to Digital Circuits Addendum # 1

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Addendum # 1Digilent Nexys-2 Board and Adept programming tool

1. Synopsis:

Digilent Nexys-2 is a versatile test-bed for prototyping of digital circuits. We can design our cir-cuit and not only simulate it in ModelSim but actually implement it in hardware (on the FPGA ofNexys-2). Adept is a software tool from Digilent used in programming (configuring) the FPGAon the Nexys-2 board. Adept also provides a communication arrangement between the host PCand the FPGA on the Nexys-2 board so that we can make use of Virtual I/O and File I/O. Adeptacts as an interface between the ChipScope software running on the host PC and the ChipScopelogic analyzer hardware planted on the FPGA.

In the coming weeks, we will be using the Digilent Nexys-2 board quite frequently. Additionally,you will be doing your semester-end project on this board. Therefore, you are strongly encour-aged to get to know how to set the jumpers and power up the board and how to download a con-figuration file to the board. Also you need to understand the input/output resources on this boardand how they can be utilized. While the following two manuals provide elaborate information onthe Nexys-2 board and the Adept tool, it is much easier for EE201L students to go through thissimplified addendum.

Digilent Nexys 2 Reference Manual http://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfDigilent Adept Suite User’s Manual (which came with the software)

This addendum is essentially an abridged version of the two manuals, extracting only the essentialinformation needed for EE 201L students. We assume that you have installed Adept on the PC asper procedure Adept_2.1_Installation_steps_USC.pdf conveyed to you.

2. Major items on the board:

Complete set of parts as given in the manual Parts important to EE201L

Most important I/O

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3. Disable unused items:

Though we do not use the Intel/Numonyx StrataFlash or the Micron PSDRAM(pseudo-static RAM), we must disable them so that they do not interfere with therest of the logic. Your TA will talk about this later.

assign {St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_we_bar, Mt_St_oe_bar} = 5'b11111;

NET St_ce_bar LOC = R5; NET St_rp_bar LOC = T5; NET Mt_ce_bar LOC = R6;NET Mt_St_oe_bar LOC = T2; NET Mt_St_we_bar LOC = N7;

4. Power Supply and Jumper configuration:

4.1 No Peripheral Modules initially in EE201L

Since we are not planing to use any Peripheral Modules (Pmod) in the firstfew weeks, the jumpers (JP1, JP2, JP3, and JP5) next to the PeripheralModules connectors (choosing power source for the modules) can be left intheir factory set locations (i.e. 3V3 side and not on the VSWT side).

4.2 No PS2 Keyboard/Mouse interface in EE201L:

Since we are not planning to use the PS2 connector, the jumper JP10 next to the PS2 connector (inthe South-West corner) can be left in its factory set location (i.e. 3V3 side and not on the VSWTside).

4.3 No special JTAG cable needed in EE201L:

Since we do not need to use a special JTAG cable, we need to place a jumper on the JTAG header(J5 in the North-East corner) bridging pins 2 (TDI) and 3 (TDO). Please take the spare jumper from

the jumper storage location JP8 at the South-East corner of the board and place over pins 2

and 3 of JTAG header J5.

4.4 Powering the board:

In EE201L, we will use USB power only. Set the power select jumper to USB as shown and connect the USB cable provided along with the board to your com-puter on one side (regular USB connector side) and the board on the other side (USB mini connector side).

Turn on the power switch at the north-west

corner of the board.

Com

pute

r

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4.5 Run the board built-in self-test: (you can also do this using the tab on Adept.)

To run the board built-in self-test, leave the jumper JP9 (in themiddle of the North-East quarter of the board) on its factory setside (i.e. ROM side and not the JTAG side). With this, whenyou switch on power, and press the reset button at the top rightcorner, after a short while, you will see the 4-character seven-

segment display showing

“run” for a short-while followed by “PASS” and “ 128” alternatively. This means the board haspassed the test. The test program has been pre-stored by the factory in an on-board Platform FlashROM. The test program includes a simple “snake” game. If you now press any one of the 4 but-

tons , the program exits the testing part and enter’s the snake game

part. Press another button and see the snake crawling towards you. Play for sometime by pressingdifferent buttons.

4.6 Configuring the FPGA by downloading your own design from your PC using Adept:

4.6.1 The USB cable previously connected between your PC and the board not only helps pow-ering your board but also helps in downloading a bit file from your PC to the board.

4.6.2 Jumper JP9 setting: Move jumper on JP9 (the JP9 in the middle of the North-East quarterof the board) from ROM side to JTAG side. Leave it there hereafter.

4.6.3 To download your own design, you must first install the Adept tool on your PC, as perinstructions separately provided. You are provided a sample test bit file (test_nexys2_verilog.bit).If you have not done already, download the BIT_files.zip from the link provided on BlackBoard.Extract test_nexys2_verilog_bit_file.zip in C:\ to form C:\BIT_files subdirectory containing thefile test_nexys2_verilog.bit .

4.6.4 When you are using your board with a new computer (such as the lab PC in OHE336) forthe first time, do the following:

A. Make sure that you have set the JP9 jumper as stated above.B. Connect the board and switch-on power.C. If the computer reports “Found New Hardware” go through the wizard to load drivers

Refer to the document Adept_2.1_Installation_steps_USC.pdf if needed.D. Go to Start => Programs => Digilent => Adept

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Adept should automatically recognize your board. For example for EE201L course, it shows the product as Nexys2 - 500.

E. Browse and locate the bit file (test_nexys2_verilog.bit). Configure the FPGA click the Program button. F. Now you should see the walking LEDs pattern on the LEDs. The four seven segment

units display in hex the 8-bit value set on the 8 switches in true and complemented fashion. Play with the push buttons and switches and later understand how the program (test_nexys2_verilog.v) is written to achieve it.

4.7 Clock A 50MHz clock oscillator on the board produces the clock signal. It is usually called CLK_PORT in our designs. It is attached to the pin B8 of the FPGA.

5. I/O Components:

test_nexys2_verilog.bit

You can read about these in the Nexys-2reference manual. Your TA will explaintheir operation.

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6. Connection/Pin Table and UCF file:

The following figures will come handy and useful. Your TA will explain.

Watch this: http://www-classes.usc.edu/engr/ee-s/201/seven_segment_display.swf

Pull-down resistances

Produce “0”when operated

Up = “1”

Down = “0”

Sourcing mode“1” = light up

Current limitingseries resistances

pnp transistorConducts when base = 0

“0” = light up

CommonAnode

4 DP (dot point)cathodesjoined

Rea

d th

e .u

cf fi

le to

ver

ify a

few

pin

num

bers

.

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7. Digilent References:

Digilent main site address: http://www.digilentinc.com/

We have maintained a copy of the Nexys-2 documents our USC EE201L web site so that if theDigilent site is not accessible, you can access our local copy.Nexys 2 2-page brochure <== Not importanthttp://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2&Nav1=Products&Nav2=Programmablehttp://www-classes.usc.edu/engr/ee-s/201/FPGA_Synthesis/Digilent_Nexys2_Documentation/Digilent_Inc_DigitalDesignEngineer_Source.mhtNexys 2 Reference Manual <== Most importanthttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdfhttp://www-classes.usc.edu/engr/ee-s/201/FPGA_Synthesis/Digilent_Nexys2_Documentation/Nexys2_rm.pdfNexys 2 Schematics <== Not importanthttp://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_sch.pdfhttp://www-classes.usc.edu/engr/ee-s/201/FPGA_Synthesis/Digilent_Nexys2_Documentation/Nexys2_sch.pdfAdept Software User’s Manual <== Not important for students but important for teaching teamDigilent Adept Suite User’s Manual (which came with the software)On your PC, Start => Programs => Digilent => Adept => Adept Application User's Manual.pdf

A 2-bit counter and a 2-to-4 decodercan be used to implement the scan control of the anodes. A 4-to-1 8-bitwide mux simultaneously multiplexesthe 8-bit value on to the 8 cathodes.

AN0AN1AN2AN3