Add-In Cores Simply the FPGA Debug Chore

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Add-in Cores Simply the FPGA Debug ChoreVERSION 1

Created on: May 14, 2009 2:12 PM byDustin "Dr Dtroit" Hamilton - Last Modified: May 14, 2009 2:12 PM by Dustin "DrDtroit" Hamilton

by Jon Titus, Senior Technical EditorEcnmag.com - May 04, 2009

Design tools insert debug logic into FPGAs so engineers can focus on design problems and not ondebugging the debugger.

Engineers will find a variety of debugging tools among the design software offered by

FPGA vendors. The tools place debug logic into a design so a host PC can access the

FPGA's internal conditions, memory contents, register data, and so on. Engineers can set

the trigger conditions that initiate data capture and storage of data in internal RAM. The

PC, which communicates with the FPGA through a JTAG connection, also can configure

internal FPGA settings and force signals into known states.

"When engineers are up against a deadline and they must debug an FPGA chip, they don't

want to create their own debug logic to probe the chip," said Brian Caslis, software

marketing engineer at Lattice Semiconductor. "They need something they know will work

and that they can quickly insert into their circuit."

In addition, they must consider how the debug capabilities will affect their design flow. Must they modify their

application code to add debug capabilities, or can they simply invoke debug capabilities and have the design tools

automatically add them? And how much work does on-chip debugging entail? To find out, we talked with experts

at Actel, Altera, Lattice Semiconductor, and Xilinx.

Xilinx provides an integrated logic-analyzer (ILA) core within its ChipScope Pro tools and developers can use a

Core Inserter tool to place an ILA into a synthesized design. (Xilinx also offers other cores for debug and test

operations.) Once developers have an ILA in place, an FPGA editor lets them look at the actual routing of circuits

and low-level components, and connect them to the ILA core for trigger or data-capture use. "You can identify

the debug cores currently in a placed-and-routed design and quickly change the connections to those cores,"

explained Brad Fross, product engineering manager for the Xilinx ChipScope tools. "Assume you have an ILAcore connected to a state machine in your design. You can use the editor to change the signals you need to

observe. Within a few minutes you have changed the signals, re-route them, saved a new bit file, and gone back

to your PC to view new debug information. This operation mimics lifting a scope probe on a board and placing it

on another signal."

The Xilinx ChipScope Pro tool inserts logic-analyzer, bus-analyzer,

and virtual-I/O software cores into a design so developers can view internal signals at any node.

The Platform Cable USB pod performs device-programming and debugging

communications from a host PC to a target board. Courtesy of Xilinx.

The PC-based analysis software can change trigger conditions as needed. "You can set up an ILA core to trigger

on a specific bit pattern or value on the signals it monitors," noted Fross. "Or, you can trigger when a value goes

outside a range, or set up many other types of trigger conditions. You make these changes dynamically from your

PC through a JTAG connection so you don't have to recompile application code when you change trigger

settings. And you can set the trigger position anywhere in your capture window so you could record data after or

before a trigger event, or capture x data points before and y points after a trigger event."
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Developers add SignalTap ELA blocks to their design as needed, using either the Quartus II software, which

automatically adds the ELA to the design, or by manually adding SignalTAP to their RTL, just as they would add

any other IP or circuit "component." If they change trigger conditions or data lines, they only have to recompile

the SignalTap block. "When someone says, 'Wait a second, I want to trigger on ABC not XYZ,' they can do an

incremental compile with the new trigger information," said Simpson.

When engineers debug or test a design in an Actel flash-based FPGA they use Identify Actel Edition (AE)

Instrumentor to insert debug-logic into their RTL before synthesis. This "instrumentation" step creates a

debuggable hardware description language (HDL) version of the design. Then engineers can set the sample

signals, trigger points for conditional sampling, and trigger breakpoints for event-driven sampling of the signals

within the design. After they program an FPGA, the engineers use the Identify AE Debugger to communicate

with the debuggable design and capture data.

As needs change, the engineers can modify the RTL code to accommodate new trigger conditions and data-

capture signals. "Each time you change the particular points you probe, you change the RTL code, recompile the

code, and layout and route the new design," said Wendy Lockhart, senior manager for design solutions marketing

and training at Actel. "So the physical implementation changes because the debug circuits become part of theoverall architecture. You don't intend to change things, but you might observe some slight changes in timing, for

example, even though the tools confirm the proper functionality of your design."

Of course, the IP for any debug core take some "space" in the FPGA. "If your design already takes 98 percent of

an FPGA's logic elements, you can't add a debug core at the last minute," stressed Lockhart. "We encourage

engineers to think about debug requirements when they start a project. If they plan to use, say, a ProASIC3

A3P250 250k-gate FPGA, they might start with a larger device such as the A3P600 with 600K gates. That device

gives them plenty of space for the debug circuits. Then they can validate their design, remove the debug cores,

and transfer the circuit into a smaller FPGA." According to Hughes, many customers include the Identify AE

core or cores in a design right from the start because it comes as part of the Libero Gold software package.

Simulation of a circuit can only take you so far before you have to jump into debug mode. "Suppose you run asimulator and have to wait for 1000 cycles of event A and then wait for 1500 cycles of event B before you

examine the relationship of three other signals, X, Y, and Z," said Lockhart. "You want to know if X comes on

for five clock ticks and then if Y goes off for six clock ticks before Z comes on for another seven ticks. That's a

complex relationship to look for and it can take a long time to obtain and analyze the simulation results."

"But you can use conditional triggers in Identify AE to wait until events occurs in sequence," said Lockhart.

"Then you can acquire just the information you need so you minimized the amount of data you must examine to

ensure your circuit operates as it should. Think of the debug core as a logic-analyzer with a wide range of

conditional statements engineers can put into their RTL code to analyze on-chip events."

The debug data from an Identify AE core goes into a PC that will display the data in several ways. "The PC-based

software can highlight pieces of your RTL codes to indicate where a problem might occur," said Hughes. "Then auser can back annotate the RTL code to fix the problem or try something different. Also users can display values

for signal groups, such as data and address buses, so they can better interpret what happens over a given time.

And they can look at computer-generated waveforms that present the debug information in graphical form."


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This display from the Actel Identify Debugger shows instrumentation code added

(bottom window) to a design. The floating window shows the acquired signals and their waveforms. Courtesy of Actel.

Leave It In or Take It Out?

After you debug a design should you remove the debug cores or leave them in the circuit? It depends. "If

designers don't have a strict power and layout budget, often they leave a debug core in the FPGA," noted Altera's

Simpson. "They might choose to upgrade the design later on, so it's helpful to still have the debug core available.

Also they can use remote debug capabilities to extract information in the field via the JTAG port and the System

Console software. We put in a SPI interface to System Console as well, because weve seen FPGAs connected to

coprocessors that use SPI as a communication channel."

Brad Fross at Xilinx said when customers remove debug cores they have to go back and re-implement the design.

"When you probe something inside an FPGA with one of our debug cores, you inherently change the design, add

loads to signals, and perhaps change how the place-and-route algorithms handle the design. In other words, you

perturb the design."

"Suppose you have a basic functional problem where your logic was just incorrect," continued Fross. "In that

case, taking the cores out will not hurt your design. But lets say you have a timing problem. Often adding the

debug core causes the problem to disappear because the FPGA tools moved things around and all of sudden the

circuit behaves properly. In that case it behooves you to go back and understand how the timing changed so you

can properly constrain your design. Then you can safely remove the debug cores."

If you decide to remove Lattice debug cores it doesn't take much work. After you use the Reveal Inserter to add a

debug core, a Reveal .rvl source file appears in the ispLEVER Project Navigator. If you decide to remove debug

from your design, you just delete that .rvl file from your source list. "Conversely, if you change the functionality

of your source code, the Project Navigator will automatically reinsert the debug cores as long as the .rvl Reveal

file exists," said Caslis of Lattice Semiconductor.

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Add-In Cores Simply the FPGA Debug Chore