ADC Training

ADC Training

Peter QianNSSH FAE

2

Agenda

• Review of Definitions• Sources of Distortion and Noise• Common Design Mistakes• ADCs from National Semiconductor

3

Offset Error

111

110

101

100

011

010

001

000

1/8 1/4 3/8 1/2 5/8 3/4 7/8 FS

ANALOG INPUT (V)

OUTP

UT C

ODE

IDEAL

ACTUAL

OffsetError

NCG 9/99

4

Full-Scale (Offset) Error

111

110

101

100

011

010

001

000

1/8 1/4 3/8 1/2 5/8 3/4 7/8 FS

ANALOG INPUT (V)

OUTP

UT C

ODE

ACTUALFull-Scale

Error

IDEAL

NCG 9/99

5

Gain Error (Full-Scale Gain Error)

111

110

101

100

011

010

001

000

1/8 1/4 3/8 1/2 5/8 3/4 7/8 FS

ANALOG INPUT (V)

OUTP

UT C

ODE SHIFTED ACTUAL

Gain Error

ACTUAL

NCG 9/99

8

Signal-to-Noise and Distortion (SINAD)

SINAD = -20 * Log 10-SNR

10 + 10THD

10

SINAD = 10 * Log10

-SNR

10 + 10THD10

1

1

9

ENOB - Effective Number Of Bits

• ENOB says that the ADC is equivalent to this (ENOB) number of bits as far as SINAD is concerned. That is, a converter with an ENOB of 7.0 has the same SINAD as a theoretically perfect 7-bit converter.

ENOB = SINAD - 1.766.02

1

10

Input Dynamic Range

Dynamic Range is the ratio of the largest to the smallest possible signals that can be resolved. DO NOT confuse with Spurious Free Dynamic Range (SFDR).

Resolution (Bits) Dynamic Range (dB) 6 36.0 8 48.1 10 60.2 12 72.2 14 84.3 16 96.3 18 108.4 20 120.4

Dynamic Range = 20 * Log(2n - 1)

NCG 9/99

11

SFDR - Spurious Free Dynamic Range

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

65dB SFDR

Signal

Highest “Spur”

12

Ideal Case

• THD and SNR curves are linear• SINAD (and ENOB) maximum at –THD = SNR

40.0

45.0

50.0

55.0

60.0

65.0

70.0

75.0

-40 -30 -20 -10 0

SNR (dB)

-THD (dB)

SINAD (dB)

13

Actual Case

• THD and SNR curves nonlinear near 0 dBFS input• SINAD (and ENOB) maximum a little below –THD = SNR

40.0

45.0

50.0

55.0

60.0

65.0

70.0

75.0

-40 -30 -20 -10 0

SNR (dB)

-THD (dB)

SINAD (dB)

Sources of Noise and Distortion

15

Common Sources of Noise and Distortion

• Inadequate Supply Bypassing• Inadequate VA - VDR* Supply Decoupling• Noisy Components/Conditioning Circuitry• Quantization• Clock• Output to Input Coupling

* VDR (or DR VD) is the supply for the output drivers

18

Excessive Clock Jitter (cont’d)

Jitter

NoiseAmplitude

Max Jitter = VIN / (2(n+1) VFS fIN)

19

Jitter Question


How much jitter can be allowed in the following- 8 bit ADC- VREF = 2 Volts- ADC Gain = 1- Maximum input of 1VP-P at 40 MHz

Max Jitter = 2V / (2(8+1) 1V 40,000,000)Max Jitter = 2V / (512 40,000,000)Max Jitter = 31.1 ps

3

?

20

Jitter Question (2)



2

?Max Jitter = VIN / (2(n+1) VFS fIN)

21

Jitter Question (3)



3

?Max Jitter = VIN / (2(n+1) VFS fIN)

22

Jitter Question (3)

How much jitter can be allowed in the following-12 bit ADC- VREF = 2 Volts- ADC Gain = 1- Maximum input of 1VP-P at 248 MHz

Max Jitter = 2V / (2(12+1) 1V 248,000,000)Max Jitter = 2V / (8192 248,000,000)Max Jitter = 0.31 ps !

2

?

Allowable Jitter with 0.1VP-P input? 3.1 ps


23

Signal Integrity Problem

• Signals propagate down a line• Improper termination causes reflections• Reflections

– Cause signal distortion– Cause signal radiation

• Distortion– Leads to a change in timing– Can lead to timing uncertainty (jitter)– Jitter causes ADC output noise

24

Reflection Problem

• Signals propagate down a line• Improper termination causes reflections

and signal distortion.

25

When is Termination Needed?

• Simple traces need not be terminated• Transmission Lines should be terminated• Trace becomes a transmission line at:

Length >-tr

6 x tPR

Where tr is the digital signal rise timetPR is the signal propagation rate

Typical tPR is about 150ps/inch on board of FR-4 material

4

26

Terminating Analog Lines

• Analog signals are complex waveforms• For single frequencies, traces carrying

analog signals become transmission lines at

Where A is the zero-to-peak signal amplitudef is the signal frequency in MHz

Length >-440

A x x f140A x f=

27

Question: Is Termination Needed?

An ADC clock Signal has a 2ns rise time. The PCB is a typical one of FR-4 material. Beyond what line length should the line be properly terminated??Length >- tr

6 x tPR

2 x 10-9

6 x 150 x 10-12 /in=

103

450Maximum Length = = 2.2 inches (5.6 cm)

2

28

Termination Techniques

• Two Types of Termination– Series – Matches Driver Output to Line

• Rsource + Rseries = ZO

– A.C. – Matches Receiving end to Line • Series RC to Ground

29

Series Termination

• Series Termination: A Series Resistor– Source Impedance + Resistor = ZO

– Resistor placed close to the source• Series Terminate When Source to Resistor

Distance :

Length >-tr

6 x tPR

3

NOTE: See National Semiconductor’s Application Note AN-1113 (http://www.national.com/an/AN/AN-1113.pdf) for controlling line impedance.

tPR is approximately 150 ps/inch or about 59 ps/cm

http://www.national.com/an/AN/AN-1113.pdf

http://www.national.com/an/AN/AN-1113.pdf

30

Series Termination Question 1

Develop a Rule of Thumb for the relationship between maximum line length and digital rise time before a trace must be treated as a transmission line

7

L = Max Length >-tr

6 x tPR

L = tR / (6 x tPR )L = tPR / (6 x 150ps/in) = tPR / 900 x 10-12 = tPR / 9 x 10-10

If tPR = 1 ns, then L = 1 x 10-9 / 9 x 10-10 = 10/9 inch per nsL = 1.1 inch per ns of rise time Or, for centimetersL = tPR / (6 x 59ps/cm) = tPR / 354 x 10-12 = tPR / 3.54 x 10-10

If tPR = 1 ns, then L = 10-9 / 3.54 x 10-10 =10/3.54 cm per nsL = 2.8 cm per ns of rise time

?

31

Series Termination QuestionAn ADC sometimes has bad data at the output. It is noted that the clock line is 6 inches long and the clock signal rise time is 2 ns. It is also noted that the ADC data output lines are 3 inches long and have 3.5 ns rise time. The data outputs go directly to an ASIC. What is the first thing you would do to try to solve this problem?

7

? L = Max Length >-tr

6 x tPR

Check to see if clock or data lines are long enoughto be considered transmission lines:L = 1.1 inch per ns of rise timetPR = 2ns, so max line length is 1.1 * 2 = 2.2 inchesAt 6 inches, the clock line should be treated as a transmission line.At 3.5 ns rise time, max length is 1.1 * 3.5 = 3.85 inches,So the 3 inch output data line length is o.k.

32

A.C. Termination

• A.C. Termination: Series RC to Ground at Destination. Needed for “Rat’s Nest”

–R = ZO

–C: C 4 x tPR x LZO

>-

2

Where L is the line lengthZO is the characteristic impedance of the linetPR is the signal propagation rate down a board trace (about 150ps/inch with FR-4 board material)

33

Question (A.C. Termination)

A 7 inch long clock line with a 50-Ohm characteristic impedance needs a.c. termination on an FR-4 board. What is the value of the series resistor and the smallest capacitor that should be used?

2

R = ZO = 50

C 4 x tPR x LZO

>-4 x 150 x 10-12 x 7

50>- 84 pF>-

?

ADC DesignConsiderations

35

Agenda: ADC Design Considerations

• The Analog Input• The Voltage Reference• The ADC Clock• The Digital Outputs

The Analog Input

37

Inadequate Conditioning Circuitry

ADC Input

4.7k

2K

-

+

+5V

-5V

220 220

Input

51

430 pFWhat is wrong with this circuit?

1) Gain of ~2 (could be unstable)2) Possible problem driving sampling input

3

38

Better Conditioning Circuitry

Input220 22pF

ADC Input

47430

2K

-

+

+5V

-5V

22 220

47

62

3.9 nF

What is overall gain of this circuit?

(47/(220+47)) *0.176 * 11.51 =

(220 / (22 * 430)/(22 + 430))2.026

From Input Divider Amplifier Gain Circuit

7

39

Single-Ended Input to Differential Input ADCNOT Preferred Way Best Way

ADC12DL066

IN+

IN-

2V

0V+VCM

+VCM

VCM can be any voltage from 1V to VA / 2. It is acceptable to use VRM.

NOTE: Performance with a single-ended input signal is not as good as with a differential input signal !

ADC12DL066

IN+

IN-

+0.5V

-0.5V

VCM

40

Single-Ended Input to Differential Input Without a Transformer

Best Solution for d.c. and low frequency applications

ADC121S625

IN+

IN-

VCM

LMH6550

41

Single-Ended Customer Issue

What are expected output codes? – peak = 0.0V + peak = 1.0V & output clipped > 1VIs the output as predicted? YES !How should the input circuit look for correct conversion results?

(IN+) – (IN-) = –1V(IN+) – (IN-) = 0 gives code of 800h or 1000 0000 0000 decimal(IN+) – (IN-) = +1V gives code of FFFh or 1111 1111 1111 decimal

Min code: 800hMax code: FFFhWhat is the problem with this circuit?

VREF = 1.0V. What value of (IN+) – (IN-) gives code of 000h?

+1V

–1VDifferential Input

12

Actual output

Desired output

ADC12DL066

IN+

IN-

VREF

2V

0V

1.0 V

42

Recommended Single-Ended Circuit

Here is a better way to bias the input circuit, ensuring that the input common mode voltage is at the mid-scale voltage of the input signal.

NOTE: Performance with a single-ended input signal is not as good as with a differential input signal !

ADC12DL066

IN+

IN-

2VP-P

VCM

VCM

1

43

Recommended Single-Ended Input Circuit for D.C. Applications

NOTE: Performance with a single-ended input signal is NOT as good as with a differential input signal !

1

ADC

2V

0V +1V

IN+

IN-

VREF1.0 V

The Voltage Reference

45

Ramp with Quiet Reference

46

Ramp with Noisy Reference

47

Why Noisy Reference is Worse at High Input Voltages

From ABCs of ADCs :Output = 2n x G x AIN / VREF

So, as the input increases so does the output code and an error in AIN is a larger error when AIN is larger.

1

48

Clean Reference and a Sine Wave

49

Noisy Reference Effect Upon a Sine Wave

50

Clean Reference and a Sine Wave – FFT

Note SNR & Noise Floor

51

Noisy Reference Effect Upon a Sine Wave – FFT

Note SNR & Noise Floor

52

How NOT to Build a Reference

+3V

+3V

+

-

+

-

+

--

+

CM

+3V

+3V

+3V

+3V

REFB

REFT5.49K

1.5K

10K

5K 15K

0.1

0.1

0.1

0.1

10K 11K

1K

1K

316

316

0.1

0.1

0.1 10/10V

2N3906

2N390410/10V

10K

178

178

What is wrong with this circuit?Too Many ComponentsCollector in Feedback PathToo Many AmplifiersToo many different resistor values

5

53

A Better Reference Circuit

+5V

+

-

+5V

+5V

EXTT

82

4.7K

0.1

0.1

10K

0.1

2N3906

2N3904

2K

470

750

2K

750 100

+5V

0.1

10K

100

100-V

LM4040-4.1

10uF, 6V

-

+

10 uF, 6V

1.5K

1.5K

EXTB-V

What is the nominal range of voltages for EXTT and EXTB?EXTT min = 4.1 * 0.75/(0.75+2+0.75) = 0.88VEXTT max = 4.1 * (0.75+2)/(0.75+2+0.75) = 3.22VEXTB min = 4.1 * (0.47)/(4.7+2+0.47) = 0.27VEXTB max = 4.1 * (0.47+2)/(4.7+2+0.47) = 1.41V

13

54

Keep Reference Quiet!

• Use a Tight Layout• “Star” Ground for all Components and

Reference Grounds of ADC• Ground Via Enters Ground at Quiet Point

The ADC Clock

56

Clock Noise

• Clock Can Add Noise• Clock Can Be Noisy, Exhibiting Jitter

– For Ideal SNR, Max Jitter = (VIN/VFS) / (2(n+1) fIN)

• Transmission Line– Clock Line Longer Than tr / (6 * Delay)

Should Be Properly Terminated

2

What effect does sample rate have on max allowable jitter?

None

57

Effect of Jitter

Sampled with “clean” Clock Sampled with Jittery Clock

The Digital Outputs

59

High Capacitance on ADC Outputs

ADC

VDR

RSUB

Driven Device

CIN

Discharge

Charge

CBUS

At what point is at “ground” potential on the die ?

4

So, what does the input see when the output current is dumped into “ground?

Noise

60

Output to Input Coupling

• Output “Talks” to Input– Because of Output Capacitance– Through Substrate

• Limiting Output Current (with Resistors) Can Help

Latch

8 x 47

ADC

VA DR VD

10uFV+

0.1uF

10uF

0.1uF

How is it that these resistors help reduce noise?

By limiting the current that is dumped into the substrate.

2

61

Watch the Time Constant!

• Reduced Amplitude With Increasing Data Rate

• Difficulty Capturing Data– Shortened Capture Window– May Not Cross Logic Threshold

62

Common Design Mistakes

• Inadequate Attention to Noise Minimization– Ignoring PSRR– No Power Decoupling/Bybassing– Noisy Support Components– Excessive Clock Jitter– Treating Clock Line as a Trace– Inadequate Conditioning Circuitry– Inadequate Reference Driver– Inadequate Supply Bypassing– High Capacitance on ADC Outputs

• Overdriving Any Input

ADC LayoutConsiderations

64

The Skin Effect

• Current Seeks The Path of Least Impedance– Entire Conductor at d.c.– Very Thin Skin Above a Few MHz

• Inductance Causes Current to Flow on Skin

• Reduces Conductor Cross Sectional Area• Increases Resistance

65

The Skin Effect: Skin Current

Current flow area

Skin Depth = inches 2.6 * Kf

K = 1r

CU

2

66

Skin Depth vs FrequencySkin Depth vs Frequency for 22 Guage Wire

0.00%20.00%40.00%60.00%80.00%

100.00%120.00%

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

Frequency, MHz

Skin

Dep

th, %

Skin Depth vs Frequency for 22 Guage Wire

0.00%

10.00%

20.00%

30.00%

40.00%

0 200 400 600 800 1000 1200

Frequency, MHz

Skin

Dep

th, %

Freq (MHz)

Skin Depth, %

0.0003 100.00%0.001 100.00%0.003 100.00%0.01 100.00%0.03 100.00%0.1 64.74%0.3 37.38%1 20.47%3 11.82%10 6.47%30 3.74%

100 2.05%300 1.18%1000 0.65%

2

67

The Skin Effect: A.C. Resistance

The a.c. resistance of a conductor is much higher than its d.c.resistance.

Rac = 2.61 x 10-7 f x r

2 x (w + h)

where Rac = AC resistance, Ohms/inchf = frequency, Hzr = conductor relative resistivity, compared to copper = 1.00w = flat trace width in inchesh = flat trace height or thickness in inches

68

A.C. Resistance vs Frequency (Typical PCB Trace)

0

0.1

0.2

0.3

0.4

0.5

0.6

0 200 400 600 800 1000 1200

Frequency, MHz

Res

ista

nce,

Ohm

s / I

nch

A.C. Resistance vs Frequency

Freq, MHz Rac0.3 0.00953041 0.01743 0.030137710 0.055023630 0.0953037

100 0.174300 0.30137681000 0.5502363

PCB Trace 0.006" wide by 0.0015" high

69

Question (A.C. Resistance)

What is the a.c. resistance in Ohms per inch at 80 MHz of a typical copper PCB trace that is 0.006 inch wide and 0.0015 inch thick?

Rac = 2.61 x 10-7 f x r

2 x (w + h)2.61 x 10-7 80 x 106 x 1

2 x (0.006 + 0.0015)=

0.002330.015

= = 0.1556 Ohms/inch2.61 x 10-7 80 x 106 0.015

Rac =

?

5

70

Proximity Effect

The Proximity Effect on two conductors carrying opposite high frequency currents causes the a.c. current flow in those nearby conductors to be primarily on the side of the conductors nearest each other.

1

Current flow areas

71

Proximity Effect on a PCB3

IRP = i

H x x (1 +(D/H)2 ) Amps/In

where IRP is the reference plane current density at horizontal distance “D” from the outgoing signal trace i is the signal current H is the height of the signal trace above the reference plane D is the horizontal distance from the edge of the trace.

PC Board

Ground Plane

Signal Trace

Current Densityin Ground Plane

DH

72

Ground Resistance

ADC Resolution (Bits)

ADC LSB Size(uV)

ADC Noise (LSB/Inch)

ADC Noise for 3 Inch Trace Length

(LSB)8 7813 0.07 0.210 1953 0.28 0.812 488 1.13 3.414 122 4.51 13.516 31 17.74 53.2

Ground plane resistance of 0.055 Ohms per inch (at 40 MHz) with an ADC reference voltage of 2.0 Volts can result in significant ground noise that can affect apparent ADC performance with only 10mAP-P of 40 MHz ground current.

73

Skin Effect + Proximity Effect

Current flows in a small area of the trace and reference plane.

1

74

Radiation

• Any Conductor Can– Radiate– Pick Up Signals

• Therefore, Any Conductor Can Be An Antenna

• Greater Loop Area Leads to a Better Antenna

• A Plane Can Radiate• Copper With One Point Grounded can

Radiate

75

Built in Antenna

Antenna

3

76

Previous Suggestion

ANALOGGROUNDPLANE

DIGITALGROUNDPLANE

ADC10321CIVT(TQFP)

32 31 30 29 28 27 26 251

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17 9 10 11 12 13 14 15 16

SwitchingPowerSupply

ADC & Analog Ground Current Flow

HighPowerDigital

Components

Hi-Power Digital Ground Current Flow

1

77

ADC10D040CIVS(TQFP)

48 47 46 45 44 43 42 41 40 39 38 371

2

3

4

5

6

7

8

9

1011

12

3635

3433

3231

3029

2827

2625

13 14 15 16 17 18 19 20 21 22 23 24

SINGLE, UNIFIEDGROUND PLANE

USE POWER TRACES, NOT A PLANE

Another Previous Suggestion

ADC Power Supply path (yellow)

ADC Return current path (brown)

Digital Power Supply path (blue)

Digital Return current path (red)

DigitalComponents

DigitalComponents

PowerSupply

2

78

DIGITAL POWER PLANE

Recommended ADC Layout Example

Use a Single, Solid Ground Plane

NOTE: ADCs DO NOT like Switching Supplies !

Green dots are vias to appropriate PWR or GND plane

ANALOG POWER PLANE

ADC DIGITAL OUTPUT POWER

PLANE

32 31 30 29 28 27 26 25

ADC12020

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

9 10 11 12 13 14 15 16

VREF

VIN+

VIN-

AGND

VA

VA

AGND

PD

D8

D7

D6

VDR

DR GND

D5

D4

D3

VR

M

VR

P

VR

N

VA

AG

ND

D11

D10 D9

DG

ND

CLK

___

OE

DG

ND

VD

D0

D1

D2

11

HIGH PWR DIGITALCOMPONENTSANALOG

CIRCUITRY

DIGITALPWR SUPANALOGPWR SUP

79

Signal Traces vs. Transmission Line

• “Long” Lines Are Not Traces• Transmission Lines Can Distort Signals• Distorted Digital Signals Produce:

– Timing Uncertainty– Clock Jitter

• Through Hole Problem• Layout Can Be Critical

80

Maximum Trace Length

Remember: All traces are transmission lines, but a trace length longer than this absolutely must be treated as a transmission Line:

tR 6 x tPD LMAX =

where LMAX is the maximum line length beyond which that line must be considered a transmission line tR is the signal rise time tPD is the signal propagation rate down the board

81

Summary of Rules

• Use A Single, Unified Ground Plane• Use Separate Power Planes• Keep All Power Planes in

Same Board Layer• Tie Down Grounded Copper Areas

at Many Points• Remember: Traces Are Transmission

Lines

82

Recommended Reading

• High-Speed Digital Design, A Handbook of Black Magic by Howard W. Johnson and Martin Graham, Prentice-Hall, 1993 ISBN 0-13-395724-1

• Analog-Digital Conversion Handbook, the Engineering Staff of Analog Devices,Inc, Prentice-Hall, edited by Daniel H. Sheingold, 1986, ISBN 0-13-032848-0

Evaluating ADCs, WaveVision Explanation

and Demonstration

84

Evaluating ADCs

• Garbage in – Garbage Out– Need spectrally Pure Sine Wave

• Minimize Jitter• Minimize Output Capacitance• Follow Manufacturer Suggestions

– Voltages– Layout

85

WaveVision History• Need for Easy Data Capture & Evaluation• Original WaveVision

– 80 MHz Oscillator on Capture Board– ADC Sample Rates: 80 MHZ Divided by 2, 4, 8, or 16 (40, 20, 10, 5 Msps)

ONLY • WaveVision2

– Added 100 & 120 MHz Osc Possibilities– ADC Sample Rates: 5, 6.25, 7.5, 10, 12.5, 20, 25, 30, 40, 50, 60 Msps– Could use 125 MHz Osc for additional sample rates of 7.8125, 15.625, 31.25,

62.5 Msps, but frequencies incorrectly reported.• WaveVision3

• Added Possibility of Inverting Sample Clock and Delaying Sample Clock by One Master Clock Cycle for Better Timing

• Problem: All Manual Adjustments• WavewVision4

– No Manual Adjustments– Automatically Recognizes Device Board– Virtually Any Sample Rate to 800 Msps Available– Automatically Measures Sample Rate– Better Display Software

WaveVision Demonstration

National’s ADCs

88

High Speed ADCs From National – 8-Bits

* Expected specifications: product in development

Speed(Msps)

Res(Bits)

Pwr. Cons(mW)

INL(LSB)

DNL(LSB)

SNR(dB)

SINAD(dB)

SFDR(dB)

@ fIN

(MHz)ADC

8 15 36 ±0.5 ±0.4 48 46 51 7.5ADC1173

8 20 60 ±0.5 ±0.35 47 46 58 4.4ADC1175

8 50 125 ±0.8 ±0.7 44 44 56 19.9ADC1175-50

8 42 40 ±0.7 ±0.6 45 45 54 4.4ADC08351

8 60 1.3/Msps ±0.5 ±0.4 47 47 60 25ADC08060

8 100 1.3/Msps ±0.5 ±0.4 46.5 46 63 41ADC08100

8 200 1.05/Msps ±0.4 46 46 60 50ADC08200 +1.0 -0.3

8 60 0.65/Msps ±0.5 ±0.25 47.4 46.1 54.5 29ADC08L060

8 1000 1.43 W ±0.35 ±0.25 48 47 58.5 100ADC081000

2 x 8 1000 1.8 W * ±0.5 * ±0.4 * 47 * 46 * 57 * 100ADC08D1000*

89

High Speed ADCs From National – 10-bits

Res(Bits)ADC Speed

(Msps)Pwr. Cons

(mW)INL

(LSB)DNL

(LSB)SNR(dB)

SINAD(dB)

SFDR(dB)

@ fIN

(MHz)10ADC10321 20 98 ±0.45 ±0.35 60 59 72 4.4

2x20ADC10D020 Dual 20 150 ±0.65 ±0.35 59 59 75 4.7

10ADC10030 30 125 ±0.45 ±0.4 59 58 68 13.5

10ADC10040 40 55.6 ±0.3 ±0.3 59.6 59.4 80 19

10 65 68.6 ±0.3 ±0.3 59.3 59 80 32ADC10065

10 80 78.6 ±0.5 ±0.25 59.2 59 78.8 39ADC10080

2x40ADC10D040 Dual 40 267 ±0.65 ±0.35 60 59 72 10.4

90

High Speed ADCs From National 12-bits & Higher

Speed(Msps)

Res(Bits)

Pwr. Cons(mW)

INL(LSB)

DNL(LSB)

SNR(dB)

SINAD(dB)

SFDR(dB)

@ fIN

(MHz)ADC

12 1.5 200 ±0.4 ±0.4 70 69.7 - 0.1ADC12662

ADC12040 12 40 340 ±0.7 ±0.4 69.5 69 84 10

12 62 354 ±1.0 ±0.5 66 65 78 10ADC12L063

12 66 357 ±1.2 ±0.4 65 64 73 25ADC12L0664 x 12 65 840 * ±0.5 * ±0.3 * 66 * 66 * 79 * 32.5ADC12QS065

12 70 640 ±1.5 ±0.65 66 - 74 25CLC5957

ADC12D040 2 x 12 40 600 ±0.7 ±0.4 68 68 80 10

ADC12010 12 10 160 ±0.5 ±0.3 70 69 83 10ADC12020 12 20 185 ±0.55 ±0.4 70 69 85 10

Coming: ADC12DL040, ADC12L065 ADC14L020, ADC14L040

2 x 12 66 686 ±1.2 ±0.5 64 63 72 33ADC12DL066

12 80 357 * ±1.2 * ±0.4 * 65 * 64 * 73 * 25ADC12L080

* Expected specifications: product in development

ADC16061 16 2.5 390 ±3.0 ±1.0 80 79 91 0.514 52 1,400 ±1.5 ±0.3 69 69 80 10CLC5958

91

General Purpose ADCs From National

Coming: ADC082S051, ADC084S06, ADC102S051, ADC124S051

Speed(ksps)

Res(Bits)

Pwr. Cons(mW)

INL(LSB)

DNL(LSB)

SNR(dB)

SINAD(dB)

SFDR(dB)

@ fIN

(KHz)ADC MuxInputs

ADCS7476 12 1,000 10 ±0.4 ±0.5 72.5 72 82 1001

ADCS7477 10 1,000 10 ±0.2 ±0.3 62 61.7 78 1001

ADCS7476 8 1,000 10 ±0.05 ±0.07 49.7 49.7 69 1001

12 500 0.5 ±1 ±1 72.8 72.6 88 100ADC78H89 712 500 0.5 ±1 ±1 72.8 72.6 88 100ADC78H90 8

ADC121S101 12 1,000 10 ±0.4 ±0.5 72.5 72 82 1001

ADC101S101 10 1,000 10 ±0.2 ±0.3 62 61.7 78 1001

ADC081S101 8 1,000 10 ±0.05 ±0.07 49.7 49.7 69 1001

10 500 0.5 ±1 ±1 62 61.7 78 40ADC104S051 4

12 500 0.5 ±1 ±1 73 73 88 40ADC122S051 2

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Summary - ABCs of ADCs

• The ADC• Review of Definitions• Sources of Distortion and Noise• Common Design Mistakes• ADCs from National Semiconductor

93

National SemiconductorData Converter Web Site

• National Semiconductor’s Data Conversion web site: www.national.com/adc– Application Notes– Data Conversion Calculator– Definitions of Terms (ADC / DAC)– Evaluation Boards, Manuals, Software– Press Releases– Selection Guides– Technical Articles– Technical Presentations– Technical Support Link

http://www.national.com/adc

http://www.national.com/adc

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Documents

ADC Training