adc EXP

ANALOG AND DIGITAL CIRCUITS

EXPERIMENT NO. 1Name:Roll No. Batch: Date performed:Sign of Instructor:

INVERTING AND NON-INVERTING AMPLIFIERAim:

1. To verify voltage gain and phase relationship.2. To observe condition for virtual short concept to be true.

Theory Inverting AmplifierThe inverting amplifier is an amplifier that inverts the input signal. If the input signal is positive voltage output will be voltage with negative polarity. Similarly, if we provide the negative input voltage we will get positive output voltage if the input signal is sine wave voltage of 1 KHz, then output will be sine wave with 180 phase shift. The inverting amplifier is useful in analog signal processing and serves as a building block to implement larger circuits. The circuit of an inverting amplifier is shown in figure 1.1 the gain of the circuit can be computed by the formula

Ainv=−Rf

R1 (1)

Where Ainvis the gain of the inverting amplifier and R f ,R1the feedback and the input resistor respectively.Inthe next section we are going to derive this formula but before that let’s understand a powerful concept called virtual short

We know that operation amplifier is the differential amplifier with extremely high differential gain( A¿¿ d)¿ .For the ideal opamp,( A¿¿ d)¿ is infinite. For the purpose of analysis, we assume that ideal opampis used to build the inverting amplifier. Due to infinite differential gain, the idea opamp requires zero differential input voltage to produce any finite output. This makes the inverting terminal to go to the same potential as non-inverting terminal. These terminals are two different terminals, yet have the same potential. Therefore the inverting and non-inverting terminals are said to have virtually short. This powerful concept that simplifies the analysis of the opamp circuits. There is certain circuit conditions under which the virtual short exists. Practically, virtual short exits if,

1. There is negative feedback used in the circuit.2. The output of the opamp is not in saturation, (i.e.) V o≤ ± V sat

3. The operating frequency is such the open loop gain of the opamp is very high.Using the virtual concept, we can analyze the inverting amplifier .In the circuit shown in figure 1.1, the non-inverting terminal is grounded .Therefore, we can write V noninv = 0

1 | Walchand College of Engineering Sangli


As there is negative feedback, assuming the not in saturation, we can apply virtual short concept (i.e.), the inverting terminals is at ground potential without being physically grounded, it is referred as Virtual ground.

V inv = 0

I R1=

V R1

R1

Since V inv = 0, the voltage across R1 is the same as the input voltage.

I R1=

V ¿

R1

Since the input resistance of an ideal opamp is infinite the current through R f will be same as R1.Therefore,

I Rf =I R1

The inverting terminal of the opamp is at the ground potential. Hence the output voltage is same as the voltage across R f

V o=- I Rf .R f

=-(V R 1

R1). Rf

=-(V R 1

R1). V inv

The voltage gain of the inverting amplifier Avis given by,

Av =V o

V ¿ =

−Rf

R1 (2)

Thus it is seen that if the virtual short exists, the gain of the amplifier is independent of the components (opamps) and depends only on the passive components (resistors). This feature is extremely important because the active component are sensitive to sensitive to temperature .Thus the circuit gain remains unchanged even if the temperature changes.

Non-Inverting Amplifier

The Non-inverting amplifier is an amplifier that amplifies the signal without inverting the input signal (i.e.) the phase difference between input and output signal is 0 . If input is positive voltage then output also will be with positive polarity. If the input is sine wave voltage of 1 KHz, then output will be sine wave voltage of same frequency with 0 phase shift.

The inverting amplifier suffers a disadvantage that the input resistance is low and is decided by resistor R1 . In the non-inverting amplifier, you will find that the input resistance R¿ is very height this because, the input is directly connected to non-inverting terminal of the opamp. The input resistance of the opamp being very high, the overall resistance of the circuit is also very high .The actual value of the input resistance is decided by input resistance of opamp used. For LM741, the input resistance R¿ is 1MΩ.The non-inverting amplifier is useful in processing analogue signal from the sensor which has high output impedance. It is usually used as front and of the signal conditioning in



circuits in instrumentation system .The circuit is shown in figure. The gain of the circuit is given by formula

Anoninv = 1+Rf

R1

Where Anoninv is gain of the non-inverting amplifier and R f , R1are the feedback resistors respectively.Applying virtual short concept .we can write,

V noninv=¿V ¿ ¿

V inv=¿ V noninv ¿

I R1=

V ¿

R1

Since V inv=¿ V ¿ ¿ ,the voltage across R1is same as the input voltage.

V R1=V ¿

I R1=

V R1

R1

Since the input resistance of the ideal opamp is infinite, the current through R fwill be same as that through R1.

I R1=I Rf

The inverting terminal of is at potentialV ¿. Hence the output voltage is the sum of the voltage across R f and voltage at inverting terminal

V o= V ¿+ I Rf . R f

=V ¿+(V ¿

R1 ) . Rf

¿V ¿(1+R f

R1)

V o

V ¿ =(1+

Rf

R1)

Thus voltage gain of a non- inverting amplifier Avis given by

Av =V o

V ¿ =(1+

Rf

R1)

Apparatus: The required apparatus is as follows:

1. Signal Generator (0-1 MHz)2. Dual power supply 3. Variable DC Power supply (0-30V, 100mA)4. Dual trace oscilloscope (20 MHz) with probes5. Digital Multimeter with probes6. Experimental Chassis or Bread –board7. Connecting wires (Single stand as well as multi stand)



8. Two resistors (1K,10K or values near these)9. Operational Amplifier IC :LM741

Procedure:1. Connections are given as per the circuit diagram.2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.3. By adjusting the amplitude and frequency knobs of the function generator,

appropriate input voltage is applied to the inverting input terminal of the Op-Amp.

4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

Observations: Inverting Amplifier

R1= Ω Rf= Ω

%error=V ocalculated−¿V O

Observed

V ocalculated

× 100¿ Gain=−Rf

R1

Sr.No Vin Vinv V OmeasuredV ocalculated

%error

12345678910

Calculations: Inverting Amplifier



Observations: Noninverting Amplifier

R1= Ω Rf= Ω

%error=V ocalculated−¿V O

Observed

V ocalculated

× 100¿ Gain=1+Rf

R1

Sr.No Vin Vinv V OmeasuredV ocalculated

%error

12345678910

Readings forNon- inverting amplifier



Calculations: Noninverting Amplifier

Conclusion:




INVERTING ADDER

Aim:1. To verify voltage gain relation with DC input2. To observe performance for AC input

Theory:

Inverting Adder

The inverting adder is a circuit that adds more than one signal and inverts the sum. For example, with reference to figure 1, if input v¿1=1V , v¿2=2V and v¿3=2.5 V , then the output voltage v0 is the algebraic sum of all the input voltages in inverted form. The value of the output voltage is given by – (1+2+2.5) V = -5.5 V.In general, when we apply Dc input

vo=−(v¿ 1+v¿2+v¿ 3)

Similarly, if we provide ac voltage waveforms at the input terminals, then the output waveform will be inverted sum all the input waveforms.

vo=−(v¿ 1+v¿2+v¿ 3)

Referring to the figure 1, the non-inverting terminal of the opamp is grounded. Due to virtual short, the inverting terminal is also at the same potential. Hence, the currents through R1 , R2 , R3

Are given by,

I R1=

V ¿ 1

R1 ; I R2

=V ¿ 2

R2 ; I R3

=V ¿ 3

R3

All these currents get summed up and pass throughR f . This is because; the input current of ideal opamp is zero. Hence the current through R f is given by,

I R f=I R1

+ I R2+ I R3

¿V ¿1

R1

+V ¿2

R2

+V ¿3

R3

The output voltage is the same as the voltage developed acrossR f . Hence vo=−R f I Rf

=−R f (I R1+ I R 2

+ I R3)



¿−Rf ¿Hence vo=−(v¿ 1+v¿2+v¿ 3) …………if R1=R2=R3=R f

In general, for n inputs, when R1=R2=R3=…=Rn

Then .vo=−(v¿ 1+v¿2+v¿ 3+…+v inn)

Thus the circuit works as adder circuit. Because of the minus sign appearing in the expression ofvo, it is referred as Inverting Adder. This circuit is quite useful in adding multiple ac/dc electrical signals.

Inverting Summing AmplifierIf

Rf

R1

=R f

R2

=Rf

R3

=...=Rf

Rn

=A ≠ 1

Then the circuit is known as Inverting Summing Amplifier. The Inverting adder is a special case of inverting summing amplifier where A=1.

Inverting Averager If

Rf

R1

=R f

R2

=Rf

R3

=...=Rf

Rn

=1n

Then output voltage is given by,

vo=−(v¿1+v¿ 2+v¿3+…+v inn)

n

Hence, the circuit is known as Inverting Averager. The circuit output is inverted instantaneous average of all input signals.

Inverting Scaler If

Rf

R1

≠R f

R2

≠Rf

R3

≠ ...≠Rf

Rn

Then output voltage is given by,

vo=−(R f

R1

v¿1+Rf

R2

v¿ 2+R f

R3

v¿3+.. ..+R f

Rn

v inn)

vo=−(A1 v¿1+ A2 v¿ 2+ A3 v¿3+…+ An v inn)Where A1 , A2 ,……. An are the scaling factors for the respective inputs. Since the inputs are scaled by different scaling factors, the circuit is known as Inverting Scaler.

Apparatus

The required apparatus is as follows:1. Signal Generator (0-1 MHz)



2. Dual Power Supply ±12V, 200mA3. Variable Power Supply (0-30,100mA- three)4. Dual trace Oscilloscope (20 MHz) with probes 5. Digital Multimeter6. Experimental Chassis or Bread- board7. Connecting wires8. Resistors9. Operational Amplifier LM741

Circuit Diagram

Procedure1. Set the opamp power supply to ±15 V2. Assemble the circuit in breadboard. Connect the power supply and all three DC

inputs.3. Note down the output voltage. 4. Vary al the inputs and again note down the output voltage5. Also check for the AC inputs and observe the output on CRO

Observations

R1=R2=R3=R f=10 KΩ

Sr. no v¿1 v¿2 v¿3 vo(Observed) vo(Calculated)

Calculations:



Conclusion:



SUBTRACTORAim:

1. To verify voltage gain relation with DC input

2. To find CMRR of Subtractor

Theory:

The subtractor is a circuit that allows subtracting one electrical signal from the other. Fig.

shows the circuit of a subtractor. If the two inputs are connected with input voltages V in1

and Vin2, the output of the subtractor is given by the formula-

V O=V ¿1−V ¿ 2

Since the output voltage is equal to the difference between two input voltages, it is also

known as a difference amplifier.

This type of circuit is widely used in control systems where it is required to find the

difference between the process variable and the set-point. This difference is the error

signal which is then used to control the process variable.

Let’s now derive the formula for the output voltage. We apply superposition theorem to

find the output voltage Vo. We assume that the only one input signal is present at a time

and find the output voltages. Then we add the results under the different conditions to get

the effective output voltage.

Case 1:

Assuming only Vin2 is present and Vin1 is grounded, we get out voltage Vo1. Thus we have,

V non−inv=( R2

R1+R2)V ¿2

V O1=V non−inv(1+R4

R3)



¿( R2

R1+R2)( R3+R4

R3)V ¿2

Case 2:

Assuming only Vin1 is present and Vin2 is grounded, we get the output voltage Vo2. Here,

the circuit becomes an inverting amplifier with input Vin1. Thus we have,

V non−inv=0

V O2=−R4

R3

V ¿1

Therefore, the effective output voltage Vo when both inputs are simultaneously present is

equal to Vo1 + Vo2, and is given by

V O=( R2

R1+R2)( R3+R4

R3)V ¿2−

R4

R3

V ¿1

If R3 =R1 and R4 = R2, We get,

V O=( R2

R1+R2)( R1+R2

R1)V ¿2−

R2

R1

V ¿ 1

¿( R2

R1)(V ¿2−V ¿ 1)

If R1=R2=R3=R4, i.e. all resistors are equal, we get

V O=V ¿2−V ¿ 1

Thus, the circuit works as subtractor.

Theoretically, if the same voltage (Common mode voltage) is applied as V in2 and Vin1,

then the output voltage should be zero. However, practically the output will not be zero,

due to mismatch between the resistors and imperfections in the practical opamp. This is

expressed in terms of Common Mode Rejection Ratio (CMRR). It is defined as,



CMRR=ADM

ACM

Where, ACM is the common mode gain and ADM is the differential mode gain. Ideally,

CMRR is∞.

Circuit Diagram:

Fig: OPAMP as a Subtractor (Difference Amplifier)

Apparatus:

Dual power supply, two variable power supplies, Digital Multimeter, Breadboard,

Connecting wires, Matched resistors, OPAMP IC LM 741.

Procedure:

1. Measure the printed values of given resistors.

2. Check all the table equipment for proper functioning.

3. Set the opamp power supply voltage to ±12V or ±15V. Set the variable power

supply voltages to +1V DC. Switch off the supplies.

4. Set the multimeter on correct range (typically 20V range).



5. Assemble the circuit on the breadboard. Use R1 = R3 = 2.2 K and R2 =R4 = 10K.

Connect the dual power supply to opamp. Verify the connections. Show the

connections to the instructor.

6. Short both the inputs and apply same voltage (common mode voltage) to both the

inputs. Observe the output voltage. The output voltage should be very close to

zero. If not, check the circuit for proper connections again and consult the

instructor. Take four readings of output voltage for various common mode input

voltages. Write the readings in a table.

7. Connect separate variable power supplies to the two inputs. Adjust the input

voltages such that the input is not saturated. Set different values for the two inputs

and measure voltage at all points in the circuit. Check if the virtual short is

present. Repeat this step to take four readings. Write the readings in the table. For

each reading, calculate the expected output voltage. Compare it with the observed

one.

8. Then apply inputs such that the output goes in saturation. Verify that, virtual short

doesn’t exist. Take two readings.

9. From readings 1-4, find the common mode gain (ACM). From readings 5-8 find

differential mode gain (ADM). Then find the CMRR using the formula-

CMRR=ADM

ACM

.

Observation:

Sr. No Vin1 Vin2 Vnon-inv Vinv Vo-measured Vo-calculated



Conclusion:




WEIN BRIDGE OSCILLATOR

Aim: To construct a wein bridge oscillator

Apparatus Required:

OP-AMP IC-741, Resistors, Capacitors, CRO.

Theory:wein bridge oscillator is an audio frequency sine wave oscillator of high stability

and simplicity. An oscillator is acircuit that produces periodic electric signals such as sine

wave or squarethe application of oscillator includes sine wave generator, local oscillator

for synchronous receiver etc.Wein bridge oscillator using IC 741 is a low frequency

oscillator. The Op-amp used in this circuit is non-inverting amplifier mode. Here

feedback network need not provide any phase shift .The circuit can be viewed as wein

bridge with series RC network in one arm and parallel RC in the adjoining arm.Resistors

R1 and Rf are connected in the remaining two arms.

In wein bridge oscillator, wein bridge circuit is connected between the

amplifierinput terminals and output terminals. The bridge has a series RC network in one

arm andparallel network in the adjoining arm. In the remaining 2 arms of the bridge

resistorsR1and Rf are connected. To maintain oscillations total phase shift around the

circuitmust be zero and loop gain unity. First condition occurs only when the bridge is

balanced. Assuming that the resistors and capacitors are equal in value, the

resonantfrequency ofbalanced bridge is given byFo = 0.159 / RC

Design:At the frequency the gain required for sustained oscillations is given by 1+Rf /R1

= 3 or Rf = 2R1Fo = 0.65/RC and Rf = 2R1



Circuit Diagram:

Calculation:Theoretical: F = 1/ (2*3.14*R*C)

Practical: F = 1/T



Procedure:

Connections are made as per the diagram. R,C, R1, Rf are calculated for the

givenvalue ofFo using the design. Output waveform is traced in the CRO

Conclusion:




SQUARE WAVE GENERATOR USINGIC 741

Aim: study of square wave generator using IC 741

Apparatus: IC 741, Resistor, Capacitor, Dual Power Supply, CRO

Theory:

The non-sinusoidal waveform generators are also called relaxation oscillators. The op-amp relaxation oscillator shown in figure is a square wave generator. In general, square waves are relatively easy to produce. Like the UJT relaxation oscillator, the circuit’s frequency of oscillation is dependent on the charge and discharge of a capacitor C through feedback resistor R. The “heart” of the oscillator is an inverting op-amp comparator. The comparator uses positive feedback that increases the gain of the amplifier. In a comparator circuit these offer two advantages. First, the high gain causes the op-amp’s output to switch very quickly from one state to another and vice-versa. Second, the use of positive feedback gives the circuit hysteresis. Let V0=Vsat, Capacitor C charges to + Vsat, as Vc>β Vsat, then V0 becomes - Vsat,& capacitor now starts discharging from+ β Vsat to -β Vsat .When V=Vsat then this process is repeated. The frequency, f = 1/T, of the square-wave is independent of output voltage Vout. This circuit is also known as free-running or Astablemultivibrator because it has two quasi-stable states. The output remains in one state for time T1 and then makes an abrupt transition to the second state and remains in that state for time T2. The cycle repeats itself after time T = (T1 + T2) where T is the time period of the square-wave.


http://www.circuitstoday.com/op-amp-comparator

http://www.circuitstoday.com/op-amp-comparator

http://www.circuitstoday.com/ujt-relaxation-oscillator


Circuit Diagram:

Observations:

Observed frequency:

Calculated frequency:



Conclusion:




TRIANGULAR WAVE GENERATOR USINGIC 741

Aim: study of Triangular wave generator using IC 741

Apparatus: IC 741, Resistor,Capacitor,CRO

Theory:

A triangular wave generator can be formed by simply connecting an integrator to the square wave generator. This circuit requires a dual op-amp two capacitors and at least five resistors. The frequencies of square wave and triangular wave are the same. For fixed R1,R2and C values, the frequency of square wave as well as triangular wave depends on the resistor R. As R increased or decreased, the frequency of triangular wave will decrease or increase, respectively. Although the amplitude of the square wave is constant, the amplitude of the triangular wave decreases with an increase in its frequency, and vice versa. The input of integrator A2 is a square wave, while its output is a triangular wave .However for the output of A2 to be a triangular wave requires that 5R3C2>T/2,Where T is the period of the square wave input. As a general rule, R3C2 should be equal to T. To a stable triangular wave ,it may also be necessary to shunt the capacitor C2 with the resistance R4=10R3 and connect an offset voltage –compensating network at the non-inverting terminal of A2 .As with any other oscillator, The frequency of the triangular wave generator is limited by the slew-rate of op-amp. Therefore, a high-slew-rate op-amp such as LM 301 is used for the generation of relatively higher frequencies.



Circuit diagram

Observations:

Observed frequency:

Calculated frequency

Conclusion:




ASTABLE MULLTIVIBRATOR USING IC 555

Aim: Study of IC555

Objectives: After performing this experiment, you will be able to,Understand operation of IC555 as Astable Multivibrator.

Introduction:The 555 timer IC is an integrated circuit (chip) used in a variety of timer, pulse

generation, and oscillator applications. The 555 can be used to provide time delays, as an oscillator, and as a flip-flop element.

An astable multivibrator, often called a free-running multivibrator, is a rectangular-wave generating circuit. Unlike the monostable multivibrator, this circuit does not require any external trigger to change the state of the output, hence the name free-running.

Pin 1 is grounded; pins 4 and 8 are shorted and then tied to supply +Vcc, output (VOUT is taken form pin 3; pin 2 and 6 are shorted and the connected to ground through capacitor C, pin 7 is connected to supply + VCC through a resistor RA; and between pin 6 and 7 a resistor RB is connected. At pin 5 either a bypass capacitor of 0.01 F is connected or modulation input is applied.

The circuit diagram for the astable multivibrator using IC 555 is shown here. The astable multivibrator generates a square wave, the period of which is determined by the circuit external to IC 555. The astable multivibrator does not require any external trigger to change the state of the output. Hence the name free running oscillator. The time during which the output is either high or low is determined by the two resistors and a capacitor which are externally connected to the 555 timer.



Circuit Diagram:

The above figure shows the 555 timer connected as an astable multivibrator. Initially when the output is high capacitor C starts charging towards Vcc through RA and RB.

The capacitor is periodically charged and discharged between 2/3 Vcc and 1/3 Vcc respectively. The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output remains high and is given by

where RA and RB are in ohms and C is in Farads. Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vccis equal to the time the output is low and is given by

Thus the total time period of the output waveform is

Therefore the frequency of oscillation

The output frequency, f is independent of the supply voltage Vcc.



Specifications of Equipment’s:1. Dual power supply (± 15V , 100 mA)2. CRO (20 MHz ,Dual Trace)3. Experimental Chassis / Breadboard and components, Wires.

Procedure:1. Make connections of power supply and CRO to Experimental Chassis.2. Observe the waveforms output (at pin-3) and capacitor (at pin-2) on CRO with

and without diode connection across RB.

Observations:

With DiodeTON = TOFF = TTOTAL =

Without DiodeTON = TOFF = TTOTAL =

Calculations:

Conclusion:




HALF ADDER AND FULL ADDER

Aim:

To design and verify the truth table of the Half Adder & Full Adder circuits.

Apparatus required:

Sr.No

Name of the Apparatus Range

1. AND gate IC 74082. OR gate IC 74323. NOT gate IC 74044. EX-OR gate IC 74865. Connecting wires As required

Theory:

The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely,

0 + 0 = 00 + 1 = 11 + 0 = 1

1 + 1 = 102

The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum.

Half adder:

The half adder is a dual input, dual output logic circuit that adds two binary bits and gives the sum of these bits and a carry.



Full adder:

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and one OR gate.

In the above example the least significant bits of the two binary numbers are added. In this case, "1+1 = 0" with carry. A zero comes out to the adder as the least significant bit of the sum and the "1" carry-out produced by this addition is stored. When the next addition is performed, the carry-out resulting from the first addition is fed into the adder along with two (0) bits. The addition of these two bits and the carry-in (carry-out from the first addition) is interpreted as "0+0+1 = 1". This equals (1) with no-carry. Therefore, the second addition produces a sum bit of (1) and no carry-out for the next addition. The third addition, in this case "1+1+0 = 0", equals (0) with carry. The carry is again stored, becoming a carry-in for the final addition. When the final addition is performed, then, "0+0+1 = 1" produced (1) with no carry.

HALF ADDER

Truth table:

Sr.No

INPUT OUTPUTA B S C

1. 0 0 0 02. 0 1 1 03. 1 0 1 04. 1 1 0 1



Design:

From the truth table the expression for sum and carry bits of the output can be obtained as,Sum, S = A XOR BCarry, C = A AND B

Circuit diagram:

Observation Table

Sr.No

INPUT Theoretical OUTPUT Practical OutputA B S C LED 1 LED2

1. 0 0 0 02. 0 1 1 03. 1 0 1 04. 1 1 0 1

Result:

Conclusion:


http://4.bp.blogspot.com/-qU391HkdS1Q/TZpd0TFGV0I/AAAAAAAAAQk/45NsSHfUHlo/s1600/1.JPG


FULL ADDER

Truth table:

Sr.No

INPUT OUTPUTA B C SUM CARRY

1. 0 0 0 0 02. 0 0 1 1 03. 0 1 0 1 04. 0 1 1 0 15. 1 0 0 1 06. 1 0 1 0 17. 1 1 0 0 18. 1 1 1 1 1

Design:

From the truth table the expression for sum and carry bits of the output can be obtained as,

SUM = A B C + A B C + A B C + A B CCARRY = ABC + ABC +ABC+ABC

Using Karnaugh maps the reduced expression for the output bits can be obtained as

SUM

SUM = A B C + A B C + A B C + A B C = A B C


http://4.bp.blogspot.com/-Mz6YK_5azR0/TZpd5U29CRI/AAAAAAAAAQo/1_D6dW9SZJ8/s1600/2.JPG


CARRY

CARRY =ABC + ABC +ABC+ABC= AB + AC + BC

Circuit diagram:

Fig. Full Adder using Half Adder

Fig.Circuit Diagram


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http://2.bp.blogspot.com/-vAG4iDlMaIs/TZpeDv2QSTI/AAAAAAAAAQw/QocnJ3qy4Dg/s1600/4.JPG


Observation Table

Sr.No

INPUT Theoretical OUTPUTPractical Output

A B C SUM CARRY LED1 LED 21. 0 0 0 0 02. 0 0 1 1 03. 0 1 0 1 04. 0 1 1 0 15. 1 0 0 1 06. 1 0 1 0 17. 1 1 0 0 18. 1 1 1 1 1

Procedure:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half adder and full adder

circuits.

RESULT:

Conclusion:




Mux and DemuxTheory: Study of Multiplexer using IC & 74151

Multiplexer is logic circuit with many input & single output. Multiplexer accepts many inputs & gives only one output depending upon the status of control or select lines. Types of multiplexer are 2:1, 4:1, 8:1 and 16:1...

Proposition:-

The commonly used multiplexer ICs are 74150, 74151A, 74152, 74153, 74157.

74150 74151A 74152 74153 74157(16:1 Mux)

(8:1 Mux) (8:1 Mux) (Dual 4:1 Mux) (Quad 2:1 Mux)

Block Diagram:-



Pin out Diagram of IC 74151:-

Circuit Diagram:-

Observation table:-

Input Output

Strobe GSelect Input

YS2 S1 S0


S2S1S0

I0I1

I2

I3

I4

I5

I6

I7

G (Strobe)

VCC = +5V

4 3 2 1 15 14 13 12

7 8 9 10 11

74151

5

16

R=330Ω


Result:

Conclusion:



3:8 DEMULTIPLEXER USING IC 74138

Objective – the main objective of this experiment is to study of working principle of 3:8 Demultiplexers.

APP – Trainer kit.

Theory -Demultiplexer as the name indicates, it has only one data input D with 8 outputs, namely Y0, Y1…Y7. It has four data selector inputs namely A, B and C at which the control bits are applied.

The data bits are transmitted to the data bit Y0, Y1…Y7 of the output line. Which particular output line will be chosen will depend on the value of A, B and C the control input. Consider the case when CBA= 000. Now the upper AND gate is enabled while all other AND gates are disabled. Hence, it is another case CBA=001, we find that Y1 is activated because seconds AND gate enabled. This is possible only when G2, G3 pins are low and G1 pin is high.

The multiplexer is disabled when above condition fulfill otherwise all outputs are high and not dependent on input condition.

Procedure –

1. Give supply 5V to pin 16 and ground to pin 8.2. Connect LED and the input as well as to the output.3. Make the enable pins high/low as per the requirement.4. Make the input high/low.5. Observe the output.

Diagram-

Logic diagram-



Truth table-

Conclusion:


Inputs

OutputsEnable Select

G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7


EXPERIMENT NO. 9

Name:Roll No. Batch: Date performed:Sign of Instructor:

STUDY OF FLIP FLOP

Aim:To study SR, D, and JKFlip flop

Concepts:

Truth table, symbol NAND & NOR gate. Combinational circuit, sequential, memory, multivibrator, latch. A flip-flop is also called a bistable mulivibrator which gives two stable

states. Flip-flop is sequential circuit whose output depends on present state of

input as well as on the previous history of inputs.

Preposition:-

Broadly FF are classified as

FF

SR JK M/S JK D T

Layout.

Equipment’s: BreadBoard, connecting wires, power supply, LEDs, IC 7400



SR-FF (using NOR gates)

Case I- S=0, R=0, since 0 at the input of NOR gate has no effect on its output, theflip-flop remains in present state i.e. Q remains unchanged. Thefore Q=last value (no change).

Case II-S=1, R=0, this output of NOR B is low & output of NOR Ais high.

Therefore 1 at S input sets the flip flop Therefore Q=1.

Case III- S=0, R=1, this forces NOR A output to low &NOR B output to high,

Therefore Q=0

CaseIV-S=1, R=1, it is forbidden condition, because for this condition Q=Q =0.This Violates the basic definition at the flip flop.

Figure (A): RS flip flop using NOR gate

SR-FF (using NAND gates)

Case I- S=0, R=0, since 0 at the input both the NAND gates give output Q=Q =1

Therefore this is forbidden condition.

Case II-S=1, R=0, this forces output of NAND B to 1, input of NAND A to 1,

Therefore Q=0 &Q =1

Case III- S=0, R=1 this gives NAND An output as 1& input B is 1,

Therefore Q=1 &Q =0

Case IV-S=1, R=1, since 1at the input of NAND gate has no effects on its output, the FF



Remains in its present state. Therefore Q equals the last value (no change).

Figure (B): RS flip flop using NAND gate

Observation table

For Figure (A)

INPUT OUTPUT(Theoretical)

OUTPUT(Practical)

S R Q Q LED1(Q) LED2(Q )

0 0 Last value

0 1 1 0

1 0 0 1

1 1 Forbidden

For Figure (B)



INPUT OUTPUT

(Theoretical)

OUTPUT

(Practical)

S R Q Q LED1(Q) LED2(Q )

0 0 Forbidden

0 1 0 1

1 0 1 0

1 1 Last value

Result:

Conclusion:



D Flip-Flop

Observation table

Result:

Conclusion:


D Clock Q Q

0 1

1 1


JK Flip-Flop

Case-I

When both J and K are 0, the clock pulse has no effect on the output and the output of flip-flop is same as its previous value.

Case-II J=0, K=1

When J=0 and K=1 the flip-flop reset at positive going edge of clock pulse.

Case-III J=1, K=0

When J=1 and K=0 theflip-flop set at positive going edge of clock pulse.

Case-IV J=K=1

When J=K=1, the flip-flop toggles, i.e. goes to the opposite state at the positive- going edgeof the clock pulse. In this mode, the flip-flop toggles or changes state for each occurrence of the positive going edge of the clock pulse.



Observations:CLK INPUT OUTPUT

(Theoretical)OUTPUT(Practical)

J K Q Q LED1(Q) LED2(Q )

1 0 0 Last Value

1 0 1 0 1

1 1 0 1 0

1 1 1 Toggle

Result:

Conclusion:




STUDY OF UP-DOWN COUNTER

Aim:To Study Of Up-Down Counter

Apparatus: IC 74LS193,LED,Connecting wires, Bread board.

Theory:

The 74LS192 and 74LS193 are Asynchronously Presettable Decade and 4-Bit Binary Synchronous UP/DOWN (Reversible) Counters. The operating modes of the 74LS192 decade counter and the 74LS193 binary counter are identical, with the only difference being the count sequences as noted in the State Diagrams. Each circuit contains four master/slave flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operations. Each flip-flop contains JK feedback from slave to master such that a LOW-to-HIGH transition on its T input causes the slave, and thus the Q output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH. Otherwise, the circuit will either count by twos or not at all, depending on the state of the first flip-flop ,which cannot toggle as long as either Clock input is LOW. The Terminal Count Up ¿ and Terminal Count Down ¿outputs are normally HIGH. When a circuit has reached the maximum count state (9 for the LS192, 15 for the LS193),the next HIGH-to-LOW transition of the Count Up Clock will cause¿ to go LOW. ¿will stay LOW until CPU goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the¿ output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter. Each circuit has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load¿and the Master Reset (MR) inputs are LOW, information present on the Parallel Data inputs (P0, P3) is loaded into the counter and



appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both Clock inputs, and latch each Q output in the LOW state. If one of the Clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that Clock will be interpreted as a legitimate signal and will be counted.

Pin Diagram

Pin Names

CPU : Count Up Clock Pulse Input

CPD : Count Down Clock Pulse Input

MR : Asynchronous Master Reset (Clear) Input

PL : Asynchronous Parallel Load (Active LOW) Input

Pn : Parallel Data Inputs

Qn : Flip-Flop Outputs (Note b)

TCD : Terminal Count Down (Borrow) Output (Note b)

TCU : Terminal Count Up (Carry) Output (Note b)



NOTES:

a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.

b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)b. Temperature Ranges.

MODE SELECT TABLE

L = LOW Voltage LevelH = HIGH Voltage LevelX = Don’t Care

= LOW-to-HIGH Clock Transition

Observation Table

1. Up Counter

CPU CPD Q0 Q1 Q2 Q3


MR PL CPU CPD MODE

H X X X Reset (Asyn.)

L L X X Preset (Asyn.)

L H H H No Change

L H H Count Up

L H H Count Down


2. Down Counter

INPUT OUTPUTCPU CPD Q0 Q1 Q2 Q3

Conclusion:


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