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ADC ANALYZERUSER MANUAL
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
FEATURES Used with high speed ADC evaluation boards to simplify
evaluation Virtual model evaluation board using ADIsimADC™ Measures performance with HSC-ADC-EVALA/HSC-ADC-EVALB
Real-time FFT and time domain analysis Analyze SNR, SINAD, SFDR, and harmonics Import raw text data for analysis Logic analyze for quick debugging
Standard USB version 2.0 port interface (version 1.1 supported)
Compatible with Windows® 98 (2nd edition), Windows 2000, Windows ME, or Windows XP
EQUIPMENT NEEDED High speed ADC evaluation board and ADC data sheet PC running Windows 98 (2nd edition), Windows 2000,
Windows ME, or Windows XP USB 2.0 port recommended (USB 1.1 compatible) Available ADIsimADC product model files
FUNCTIONAL BLOCK DIAGRAM
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1CLOCK INPUT
FILTEREDANALOG
INPUT
SINGLE OR DUALHIGH SPEED ADC
EVALUATION BOARD
120-PIN CONNECTOR
HSC-ADC-EVALA/B-SCOR
HSC-ADC-EVALA/B-DC
CLOCKCIRCUIT
LOG
IC
SPI
ADC
n
n
SPI
+3.0VREG
PSCHB FIFO,32K,
133MHz
TIMINGCIRCUIT
CHA FIFO,32K,
133MHz
USBCTLR
PS REG
STANDARDUSB 2.0
Figure 1.
PRODUCT DESCRIPTION
The ADC Analyzer program allows users to evaluate Analog Devices’ high speed analog-to-digital converters (ADCs) when combined with the high speed ADC FIFO evaluation kit. The program also integrates Analog Devices’ ADC behavioral modeling tool, ADIsimADC, enabling users to evaluate a virtual evaluation board. With this solution, no hardware is necessary other than a PC. To evaluate the performance of high speed ADCs quickly, users can view an FFT for their specific analog input and encode rate and analyze SNR, SINAD, SFDR, and harmonic information.
The software is easy to use, intuitive, and supports many analysis tools. Through ADIsimADC, or when coupled with the ADC FIFO evaluation kit, users can start evaluating products within Analog Devices’ high speed ADC portfolio.
PRODUCT HIGHLIGHTS
1. Easy to Use. Interfaces easily with ADI’s high speed ADC evaluation boards and the ADI FIFO evaluation kit.
2. ADIsimADC. The software supports virtual ADC evaluation using ADI proprietary behavioral modeling technology. This allows rapid comparison between multiple ADCs, without requiring hardware evaluation boards.
3. USB Port Connection to PC. The PC interface is a USB 2.0 connection (1.1 compatible). A USB cable is provided in the ADC FIFO evaluation kit.
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TABLE OF CONTENTS Features .............................................................................................. 1
Equipment Needed........................................................................... 1
Functional Block Diagram .............................................................. 1
Product Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Virtual Evaluation Board Easy Start with ADIsimADC ............. 3
Requirements ................................................................................ 3
Easy Start Steps ............................................................................. 3
FIFO Evaluation Board Easy Start.................................................. 4
Requirements ................................................................................ 4
Easy Start Steps ............................................................................. 4
Installing ADC Analyzer Software................................................. 5
Installation..................................................................................... 5
Configuration File ........................................................................ 5
Configuring an Evaluation Board .............................................. 5
Additional Configuration Options ............................................ 8
Additional Analyze Options ....................................................... 9
Installing ADC Analyzer with ADIsimADC .............................. 10
Installation................................................................................... 10
Configuration File ...................................................................... 10
Configuring a Model.................................................................. 10
ADC Analyzer Functions .............................................................. 12
Time Data .................................................................................... 12
Continuous Time Data .............................................................. 12
FFT ............................................................................................... 12
Continuous FFT ......................................................................... 12
Average FFT ................................................................................ 12
Continuous Average FFT .......................................................... 13
Two Tone ..................................................................................... 13
Continuous Two Tone ............................................................... 13
Average Two Tone ...................................................................... 13
SPI................................................................................................. 13
Stop............................................................................................... 13
Zooming and Exporting Data .................................................. 13
Configuration Files .................................................................... 14
Importing Data ........................................................................... 14
Saving Files.................................................................................. 16
Printing ........................................................................................ 16
Additional Functions ..................................................................... 17
Amplitude Sweep (Virtual ADC Only) ................................... 17
Analog Frequency Sweep (Virtual ADC Only) ....................... 18
Troubleshooting.............................................................................. 19
Flat Line Signal Displayed......................................................... 19
Displayed Signal Unlike Analog Input .................................... 19
FFT Noise Floor Higher Than Expected................................. 19
Large Spur in FFT (Image Problem)........................................ 20
MSBs Missing from Time Domain .......................................... 20
Appendix: Sampling and FFT Fundamentals ............................. 21
Coherent Sampling..................................................................... 21
Windowing Functions ............................................................... 21
FFT Calculations ........................................................................ 21
REVISION HISTORY
4/06—Revision 0: Initial Version
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VIRTUAL EVALUATION BOARD EASY START WITH ADIsimADC No hardware is required to perform an easy start with ADIsimADC. However, if you wish to compare results of a real evaluation board and the model, you can switch easily between the two, as described in the following sections.
REQUIREMENTS Requirements include • Completed installation of ADC Analyzer version 4.5.0 or
later.
• ADIsimADC product model files for the desired converter. Models are not installed with the software, but can be downloaded from the website at no charge. Go to www.analog.com/ADIsimADC or look under Design Tools for the product of interest.
For more information on how ADIsimADC works, see AN-737, How ADIsimADC Models Data Converters.
EASY START STEPS 1. Obtain the ADC model files from www.analog.com/
ADIsimADC or click Design Tools for the product of interest. Download the files to a local drive. The default location is c:\program files\adc_analyzer\models.
2. Start ADC Analyzer (see the Installing ADC Analyzer section to install the software).
3. From the Open Configuration dialog box , select Modeling (see Figure 2).
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Figure 2. Open Configuration Dialog Box
4. In the ADC Modeling window, select the Device tab and click the ellipses (…) button adjacent to the dialog box. A list appears with all of the models found in the default directory, c:\program files\adc_analyzer\models.
If no model files are found, follow the on-screen directions or see Step 1 to install available models. If you have saved the models somewhere other than the default location, use the browser to navigate to that location and select a model.
5. In the ADC Modeling window, select the Input tab, then do the following:
• Select either Sine Wave or Two Tone from the list to configure the input to the model.
• Modify the Amplitude and Analog In fields to the desired values.
• Set the Encode Frequency for the desired sample rate of the simulated device under test. If set too low or too high, the model does not run.
6. Click Time Data, as shown in Figure 3. A reconstruction of the analog input displays. The standard feature set supported for evaluation boards extends as a subset of ADIsimADC features.
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Figure 3. Time Data
The model supports additional features not found when testing a standard evaluation board. When using the modeling capabilities, it is possible to sweep either the analog amplitude or the analog frequency. See the Installing ADC Analyzer with ADIsimADC section for additional features.
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FIFO EVALUATION BOARD EASY START REQUIREMENTS • FIFO evaluation board, ADC Analyzer, and USB cable. • High speed ADC evaluation board and ADC data sheet. • Power supply for ADC evaluation board. • Analog signal source and appropriate filtering. • Low jitter clock source applicable for specific ADC
evaluation, typically <1 ps rms. • PC running Windows 98 (2nd edition), Windows 2000,
Windows ME, or Windows XP. • PC with a USB 2.0 port recommended
(USB 1.1-compatible). • For products with SPI functionality, refer to individual
product data sheets and the Interfacing to High Speed ADCs via SPI® User Manual.
• For further information on best practices in testing and evaluating ADCs, see AN-835, Understanding High Speed ADC Testing and Evaluation.
EASY START STEPS You need administrative rights for the Windows operating system during the entire easy start procedure. It is recommended to complete every step before changing to user mode.
1. Install ADC Analyzer from the CD provided in the FIFO evaluation kit or download the latest version on the web. For the latest updates of the software, check the Analog Devices website at www.analog.com/hsc-FIFO.
2. Connect the FIFO evaluation board to the ADC evaluation board. If an adapter is required, insert the adapter between the ADC evaluation board and the FIFO board.
• If you are using the HSC-ADC-EVALB-SC model, connect the evaluation board to the bottom two rows of the 120-pin connector, closest to the installed IDT FIFO chip.
• If you are using an ADC with a SPI interface, remove the two 4-pin corner keys so that the third row can be connected.
3. Connect the provided USB cable to the FIFO evaluation board and to an available USB port on the computer.
4. Refer to the HSC-ADC-EVALA/HSC-ADC-EVALB data sheets for any jumper changes. Most evaluation boards can be used with the default settings.
5. Connect the appropriate power supplies to the ADC evaluation boards. The FIFO evaluation board is supplied with a wall-mount switching power supply that provides a 6 V, 2 A maximum output. Connect the supply end to the rated 100 ac-to-240 ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at J301. Refer to the instructions included in the ADC data sheet for more information about the ADC evaluation board power supply and other requirements.
Once the cable is connected to both the computer and FIFO board and power is supplied, the USB drivers start to install.
6. To complete the installation of the FIFO drivers, you must complete the new hardware sequence twice. When the first Found New Hardware Wizard opens, click the recommended install, and go to the next screen. A hardware installation warning window appears.
7. Click Continue Anyway.
8. Click Finish. The second Found New Hardware Wizard begins.
9. Repeat Step 6 to Step 8. This completes the installation.
10. (Optional) In the device manager, verify that Analog Devices, FIFO4.1 is listed under the USB hardware.
11. Apply power to the evaluation board and check the voltage levels at the board level.
12. Connect the appropriate analog input (which should be filtered with a band-pass filter) and low jitter clock signal. Make sure the evaluation boards are powered on before connecting the analog input and clock.
13. Start ADC Analyzer.
14. Choose an existing configuration file for the ADC evaluation board or create one.
15. Click Time Data in the ADC Analyzer window. A recon-struction of the analog input appears. If the expected signal does not appear, or if there is only a flat red line, see the HSC-ADC-EVAL data sheet at www.analog.com/hsc-FIFO or the data sheet for the current ADC device.
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INSTALLING ADC ANALYZER SOFTWARE ADC Analyzer is designed to evaluate the performance of an Analog Devices analog-to-digital converter quickly and easily.
INSTALLATION A copy of ADC Analyzer is included on the CD that comes with the FIFO evaluation kit. Check the Analog Devices website for updates to the software at www.analog.com/hsc-FIFO.
1. Copy the AnalyzerSetup.exe file to the PC.
2. Run the setup file and follow the instructions given in the installation wizard. Note that administrator privileges are required to install the software on Windows 2000, Windows ME, and Windows XP computers.
3. Run the executable file (the default location is in c:\program files\ADC_Analyzer\ADC_Analyzer.exe).
CONFIGURATION FILE A configuration file can be created for each high speed ADC evaluation board used with ADC Analyzer. A configuration file provides the software with important information about the data sent from the ADC evaluation board to the FIFO evaluation board, such as the number of bits, speed of the clock, and format of the data bits (binary or twos complement). Configuration files for some of the evaluation boards are included with the ADC Analyzer files. Each time ADC Analyzer is launched, a dialog box opens for you to specify a configuration file. Click Yes to specify a configuration file and then choose the file corresponding to the ADC being used.
The default configuration files can be modified or a new configuration file can be created using the instructions in the section Configuring an Evaluation Board.
CONFIGURING AN EVALUATION BOARD Follow this procedure to configure the software with the ADC evaluation board:
1. From the ADC Analyzer main menu, select Config > Channel Select. The Channel Select dialog box opens, as shown in Figure 4.
2. Complete the following, and then click OK. • On a single-channel ADC, the default configuration is
correct. • On a dual-channel ADC, it is necessary to check both
ChannelA and ChannelB. • On a demultiplexed ADC, it is necessary to check
both ChannelA, ChannelB, and Interleaved Data.
Note that Channel A in the software corresponds to Channel B on the HSC-ADC-EVALA/HSC-ADC-EVALB schematics and the bottom FIFO (U201) on the evaluation board. Channel B corresponds to Channel A on the HSC-ADC-EVALA/B schematics and the top FIFO (U101) on
the evaluation board (closest to the Analog Devices logo). For more information about the channel selection process, see the Troubleshooting section.
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Figure 4. Channel Select Dialog Box
3. From the ADC Analyzer main menu, select Config > DUT. The DUT Configuration dialog box opens (see Figure 5).
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Figure 5. DUT Configuration Dialog Box
4. Complete the following and then click OK.
• Type the name of the ADC being evaluated in the Device field.
• Type the number of bits (resolution of the ADC) in the Number of Bits field. (Note: This information is used for display purposes only.)
• To specify a different directory for the configuration file, type a new location in the Default Data Directory.
5. From the ADC Analyzer main menu, select Config > FFT. The FFT Configuration dialog box appears (see Figure 6).
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Figure 6. FFT Configuration Dialog Box
6. Complete the fields in the FFT Configuration dialog box as specified in Table 1, and then click OK. This configures the Fast Fourier Transform plot.
7. From the ADC Analyzer main menu, select Config > Buffer. The Buffer Memory dialog box appears, as shown in Figure 7.
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Figure 7. Buffer Memory Dialog Box
8. Select HSC-ADC-EVAL(A) and click OK. The Buffer Configuration dialog box opens, as shown in Figure 8.
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Ezusb-0
Figure 8. Buffer Configuration Dialog Box
9. From the ADC Analyzer main menu, select Config > Bits > Data Bits. The Bit Mask dialog box appears (see Figure 10).
Make sure that the number of bits matches the resolution of the converter. Most of the supported evaluation boards are MSB justified, so check the number of bits for the converter starting with Bit 15 (MSB). However, for the AD9280, AD9281, AD9200, and AD9201, check the number of bits starting with Bit 13.
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Figure 9.
ADC Analyzer User Manual
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Table 1. FFT Configuration Fields Field Description Select Channel If needed, modify the options under Channel A to select the appropriate channel.
Note that Channel A in the software corresponds to Channel 1 on the FIFO schematics and the bottom FIFO on the evaluation board. Channel B corresponds to Channel 2 on the FIFO schematics and the top FIFO on the evaluation board (closest to the Analog Devices logo).
Samples Choose the number of samples taken to calculate an FFT. The default is 16 kB samples. Users can choose more or fewer samples, depending on the application. The maximum number of samples that can be selected in the software is 64 kB. However, the FIFO evaluation boards are configured with 32 kB FIFOs. For single ADCs evaluated with the HSC-ADC-EVALA/B-SC model, the maximum number of samples selected should match the FIFO memory on the evaluation board. For dual ADCs evaluated with the HSC-ADC-EVALA/B-DC, the maximum number of samples should match the FIFO memory of each channel (a different number of samples can be selected for each channel). ADCs with demultiplexed outputs (such as the AD9430) can be used with a sample value of twice the FIFO memory.
Averages Specify the number of averages taken for the average FFT functions. See the ADC Analyzer Functions section for more information.
Encode Frequency (MHz) Enter the speed of the sampling clock to the ADC. If evaluating a dual ADC, two different clock rates can be entered. Note: If the value is wrong, the analog fundamental frequency displayed is wrong.
FullScale Input Power (dBm) This feature lets the user enter the amount of power (in dBm) needed on the input to determine the output full scale. It applies only in noise figure and IIP2/IIP3 calculations.
Enable Fundamental Override ADC Analyzer automatically defaults the highest spur as the fundamental frequency of interest. However, in some applications, the user may have a very small analog input signal that could be equal to or below another spurious harmonic. This option lets the user specify the small analog input signal needed for evaluation. If Enable Fundamental Override is selected, the Fundamental Frequency (MHz) box is enabled for the user to specify.
Fundamental Leakage (Bins) The number of bins that are neglected on either side of the fundamental signal when calculating the SNR and SINAD results. For example, if an encode rate is defined at 80 MSPS with 16384 samples, then 80M/16384 = 4883 Hz/Bin is specified. The type of windowing selected determines the default value of the fundamental leakage. See the Windowing section for more information. The default values are 25, 10, and 1 for Hanning, Blackman Harris, and no windowing, respectively.
Harmonic Leakage (Bins) The number of bins that are neglected on either side of each harmonic of the fundamental signal defined in the Max # of Harmonics field. Typically, this can be left at the default value of 3.
DC Leakage (Bins) The number of bins (at dc) that are not used in calculating SNR and SINAD. Typically, this can be left at the default value of 6.
Maximum # of Harmonics The number of harmonics displayed by ADC Analyzer. The default value is 6 and the maximum number of harmonics that can be displayed is 12.
Twos Complement Select this box if the data from the ADC evaluation board is in twos complement format. Refer to the ADC data sheet to determine if the ADC outputs are configured for twos complement or offset binary. If the Twos Complement option is not selected, ADC Analyzer expects the data outputs from the ADC to be in offset binary format.
User Defined SNR Bandwidth Left (MHz)
This is the amount of spectral information to the left of the fundamental by the user to analyze SNR. The resulting value is called UDSNR and appears after an FFT plot is captured.
User Defined SNR Bandwidth Right (MHz)
This is the amount of spectral information to the right of the fundamental by the user to analyze SNR. The resulting value is called UDSNR and shows up after an FFT plot is captured.
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10. To save the configuration, select File > Configuration File > Save Configuration from the ADC Analyzer main menu. Choose a file name and a location to save the file.
To turn windowing on, select either Hanning or Blackman Harris 4-Term (default) and click OK. (See the Windowing Functions section for a description of Hanning and Blackman Harris windowing).
11. From the ADC Analyzer main menu, select Config > Bits > Data Bits. The Bit Mask dialog box appears (see
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Figure 10).
Make sure that the number of bits matches the resolution of the converter. Most of the supported evaluation boards are MSB justified, so check the number of bits for the converter starting with Bit 15 (MSB). However, for the AD9280, AD9281, AD9200, and AD9201, check the number of bits starting with Bit 13.
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Figure 11. Select Windowing Function
To turn windowing off select None and click OK. The Coherent Sampling Calculator window opens (see Figure 12).
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Figure 10. Bit Mask Dialog Box
12. To save the configuration, select File > Configuration File > Save Configuration from the ADC Analyzer main menu. Choose a file name and a location to save the file.
ADDITIONAL CONFIGURATION OPTIONS Figure 12. Coherent Sampling Calculator Other options under the Configuration menu include
Windowing, Power Supply, and Y Axis. For the calculator to work properly, the correct sampling frequency must be entered under Config > FFT. Select either the desired approximate Analog Input Frequency (MHz) or the # of Sine Wave Cycles. Enter the value in the field (not labeled) and click Calculate to view the coherent frequency. The coherent frequency and number of integer cycles display in the gray boxes. Click OK to exit the Coherent Sampling Calculator.
Windowing Option
From the ADC Analyzer main menu, select Config > Windowing. The Select Windowing Function dialog box appears, as shown in Figure 10.
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ADDITIONAL ANALYZE OPTIONS Power Supply Option From the ADC Analyzer main menu, select Config > Power Supply. The Power Supply Configuration dialog box appears (see
Another option under the Analyze menu is the Bus Check.
Bus Check Figure 13). With this option, users can enter the value of the ADC analog and digital voltage supplies (see From the ADC Analyzer main menu, select Analyze > Bus Check.
The Bus Check dialog box appears, as shown in Figure 13).
Note that this dialog box is for user documentation only and does not actually set an external power supply. ADC Analyzer displays this information when data is captured. See the
Figure 15.
ADC Analyzer Functions section for more information.
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Figure 13. Power Supply Configuration
Y Axis Option
From the ADC Analyzer main menu, select Config > Y Axis. The Y Axis Configuration dialog box appears (see Figure 13).
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Figure 15. Bus Check
The bus check is a feature that reports activity on the ADC FIFO evaluation bus. This is very helpful when troubleshooting unexpected behavior.
The first pair of results report absolute bus activity. Each character in the result string reports the value nature (over time) of each respective bit on the ADC FIFO bus. If a bit in the middle of the bus is shorted to ground, it becomes clear with this result string.
The second pair of results report the relative bus activity. Each character in the result string reports the relative value nature (over time) of each bit with respect to its neighboring bits. This is very useful with it comes to determining whether two bits are shorted together on the DUT.
Logic Analyze
From the ADC Analyzer main menu, select Analyze > Logic Analyze. Once selected, ADC Analyzer captures data from the buffer source and displays a new window in which the data is displayed as individual bits in a logic analyzer style represent-tation. This is helpful when troubleshooting. Figure 14. Y Axis Configuration
Use this option to configure the display of the FFT Y Axis. From the Y Axis Configuration dialog box, you can change the default value of –130, a typical setting for the noise floor of a 14-bit ADC with 16,384 samples in the FFT calculation.
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INSTALLING ADC ANALYZER WITH ADIsimADC 2. Select a model from the list and click OK. A Model button
appears next to the Stop button (see ADC Analyzer is also useful as an evaluation tool for simulated ADCs using ADIsimADC. Figure 17).
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INSTALLATION The simulation tools are installed as part of the regular software installation of ADC Analyzer (for instructions, see the section Installing ADC Analyzer ). Before using these features, the appropriate model files must be installed. Locate the models on www.analog.com/ADIsimADC or go to the converter product page and select Design Tools for that product. Check the web-site periodically to ensure that you have the latest model files.
Figure 17. Model Button
3. Click Model. The ADC Modeling dialog box appears. Here you select the device to model and configure the analog input to the model (see
1. Download the desired model file to the models directory. The default is c:\program files\adc_analyzer\models. Figure 18).
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2. Run the executable file (the default location is in c:\program files\adc_analyzer\adc_analyzer.exe.
CONFIGURATION FILE As with the standard ADC evaluation board, a configuration file for ADIsimADC must be loaded before simulations can occur. This file provides the software with important information about the format in which the data is generated, the number of bits, the clock speed, and format of the data bits (binary or twos complement). Configuration files for some of the evaluation boards are included with the ADC Analyzer files. Each time ADC Analyzer is launched, a window opens for you to specify a configuration file. Click Yes to specify a configuration file and then choose the file corresponding to the ADC evaluation board being used. For more details, see the Configuring an Evaluation Board section.
CONFIGURING A MODEL
Follow this procedure to configure the software for use with ADIsimADC virtual evaluation board.
Figure 18. ADC Modeling Dialog Box
4. Click the Device tab, then click the ellipses (…) button to the right of the Please select your model field. A file browser opens with a list of all the models found in the default directory. If you have not loaded models on your PC, see Step 1 in the
1. Select Config > Buffer from the ADC Analyzer main menu. The Buffer Memory dialog box appears, as shown in Figure 16.
Installation section.
5. Select a model. Information about that device is filled in on the ADC Modeling dialog box, as shown in Figure 19.
Figure 16. Buffer Memory Dialog Box
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6. Click the Input tab. From this tab, you can select the input stimulus of either a single sine wave or dual sine wave, the input signal level relative to the converter range, the input frequency, the signal offset, the signal range, the external clock jitter, and the external analog dither. If two tone is selected, you can also specify the second tone. For the most accurate results, both signals should be in the same Nyquist zone (see Figure 20).
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Figure 19.ADC Modeling Device Tab
Note that the amount of jitter, assumed at the time of characterization, automatically inserts in the External Jitter box on the Input tab. The model also returns a default Output Mode which is defined either as Offset Binary or Twos Complement. This automatically sets through the Config > FFT menu. If you are using a real part along with a model, note the correct Output Mode setting.
Figure 20. ADC Modeling Input Tab
The model is now fully configured and evaluations can begin. Any of the documented features of ADC Analyzer can be used for testing the virtual evaluation board as if a real evaluation board were connected. In addition, the virtual evaluation board supports sweeping of the analog input level and frequency.
If the windowing function under the Config > Windowing menu is set to None, a Coherent Sampling window opens. If you are in modeling mode and use this function, the calculated frequency is inserted in the Analog In field on the Input tab.
To switch back to evaluate a real product, it is only necessary to specify the buffer memory. From the ADC Analyzer main menu, select Config > Buffer. Then select HSC_ADC_EVAL from the list.
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ADC ANALYZER FUNCTIONS A number of functions can be performed on the data collected by the FIFO evaluation board. These functions are represented by the row of buttons under the pull-down menus. The same functions also can be accessed under the Analyze pull-down menu. This section describes each button. For a detailed explanation of how to calculate the results, see AN-835, Understanding High Speed ADC Testing and Evaluation.
DVCC: Digital voltage level, set under Config > Power Supply (for display purposes only).
Encode: ADC clock rate (MSPS), set under Config > FFT.
Analog: Calculated analog input frequency (MHz). In IF sampling applications, the analog input is calculated back to the first Nyquist zone. Note that the encode rate must be set properly in the Config > FFT menu. TIME DATA
SNR: Signal-to-noise ratio (dB). This function displays a reconstruction of the captured
data in the time domain. The following values are listed to the left of the signal:
SNRFS: Signal-to-noise ratio full scale (dBFS).
UDSNR: User defined signal-to-noise ratio (dB). AVCC: Analog voltage level, set under Config > Power Supply (for display purposes only). NF: Noise figure (dB).
SINAD: Signal-to-noise and distortion (dB). DVCC: Digital voltage level, set under Config > Power Supply (for display purposes only). Fund: Level of the fundamental (highest) tone (dBFS). Encode: ADC clock rate (MSPS), set under Config > FFT. Image: Level of image (nonharmonic) spur (dBc). Note that
image is valid only when using demultiplexed ADCs. Analog: Calculated analog input frequency (MHz).
Second: Level of the second harmonic (dBc) of the fundamental.
Min: Minimum output code produced by the analog input.
Max: Maximum output code produced by the analog input. Third: Level of the third harmonic (dBc) of the fundamental.
Range: The range of the codes produced by the analog input. Fourth: Level of the fourth harmonic (dBc) of the fundamental.
Average: Average value of the codes; may be interpreted as the common mode. Fifth: Level of the fifth harmonic (dBc) of the fundamental.
Sixth: Level of the sixth harmonic (dBc) of the fundamental. Offset: The difference between the average and the ideal median code value. WoSpur: Level of the worst spur not including the first six
harmonics (dBc). F/S: Full-scale code range, equal to 2n, where n is the number of bits. THD: Total harmonic distortion (dBc). Samples: Number of samples taken, determined by FFT Configuration (Config > FFT).
SFDR: Spurious-free dynamic range (dBc).
Noise Floor: Level of the noise floor (dBFS). CONTINUOUS TIME DATA
Samples: Number of samples taken, determined by FFT configuration, set under Config > FFT. This function displays a continuous reconstruction of
the captured data and is also useful for trouble shooting. Click STOP to end the continuous display. CONTINUOUS FFT
FFT This function displays a continuous FFT.
AVERAGE FFT This function displays a reconstruction of the captured data in the frequency domain to analyze single-tone analog inputs. The following values are listed to the left of the signal: This function displays an average of a user-specified
number of FFTs. Configure the number of FFTs under Config > FFT. The default value is 5. AVCC: Analog voltage level, set under Config > Power Supply
(for display purposes only).
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CONTINUOUS AVERAGE FFT AVERAGE TWO TONE
This function displays a continuous average of a user-specified number of FFTs. Configure the number of FFTs under Config > FFT. The default value is 5.
This function displays an average of a user-specified number of dual-tone FFTs. Configure the number of FFTs under Config > FFT. The default value is 5.
TWO TONE SPI
This function displays a reconstruction of the captured data in the frequency domain to analyze dual-tone analog inputs. The following values are listed to the left of the signal:
This button batch executes the ADI SPI Controller program. The button is only visible when the current buffer selected in the Buffer Memory is set to HSC-ADC-EVALA/B (see Figure 16).
AVCC: Analog voltage level, set under Config > Power Supply (for display purposes only). STOP
DVCC: Digital voltage level, set under Config > Power Supply (for display purposes only).
Click this button to end any of the continuous display functions.
Encode: ADC clock rate (MSPS), set under Config > FFT. ZOOMING AND EXPORTING DATA To zoom in on any portion of a displayed analog signal or FFT, drag the left mouse button across the area of interest.
Analog 1: First analog input frequency (MHz).
Analog 2: Second analog input frequency (MHz). To display a hidden menu, click the right mouse button in the active window. Fundamental 1: First fundamental tone (dBFS).
Fundamental 2: Second fundamental tone (dBFS). Time-domain plots and FFT plots have slightly different hidden menus. These hidden menus have several options, including zooming and the capability to export time-domain data. Select items from the menus using the left mouse button (see
F1 + F2: Sum of the fundamental tones (dBFS).
Figure 21 and
F2 – F1: Difference of the fundamental tones (dBFS). Figure 22).
2F1 – F2: 2 × Fundamental 1 – Fundamental 2 (dBFS).
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2F1 + F2: 2 × Fundamental 1 + Fundamental 2 (dBFS).
2F2 – F1: 2 × Fundamental 2 – Fundamental 1 (dBFS).
2F2 + F1: 2 × Fundamental 2 + Fundamental 1 (dBFS).
WoIMD: Worst intermodulation distortion (dBc).
IIP2: Measure of the input intercept point in relation to the second order intermodulation distortion powers (dBm).
IIP3: Measure of the input intercept point in relation to the third-order intermodulation distortion powers (dBm).
SFDR: Spurious-free dynamic range (dBc).
Noise Floor: Level of the noise floor (dBFS). Figure 21. Time-Domain Plot Hidden Menu
Figure 22. FFT Plot Hidden Menu
Samples: Number of samples taken, determined by FFT configuration, set under Config > FFT. H-Zoom: Scales the selected section horizontally.
CONTINUOUS TWO TONE V-Zoom: Scales the selected section vertically.
X-Y Zoom: Scales horizontally and vertically (two dimensions). This function displays a continuous dual-tone FFT.
Exact Zoom: Enter specific coordinates to view.
Restore: Restores the graph to its original view.
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Spawn: Produces an exact working copy of the active window that can be analyzed separately.
IMPORTING DATA Data can be imported to ADC Analyzer to perform an FFT calculation. Two types of data can be imported: raw time domain text data in decimal format (from a logic analyzer, for example) and data exported from ADC Analyzer.
Export Data: Writes all of the data points as well as the calculated information to a file. The information is saved as a .CSV file that can be viewed in Microsoft Excel.
When importing data, be sure the number of bits, sample size, and digital format (twos complement vs. offset binary) are selected appropriately in the FFT Configuration dialog box.
Comments: Lets the user enter comments about the graph. If the FFT is printed, the comments are included in the printout.
Lock Data (Time-Domain Plot Only): Once a time-domain sample of the data is taken, the user can lock this data and then perform an FFT. The FFT is calculated based on this data instead of a new sample of data.
To import data previously exported from ADC Analyzer:
1. Select File > Import Data. The Import Data dialog box appears (see Figure 24).
EC1 Transition: Not applicable.
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FFT Data Write (FFT Plot Only): Writes the calculated FFT data to a file.
Bin Boundaries (FFT Plot Only): Highlights the bins used to calculate the fundamental and harmonic energy. Configure the Fundamental Leakage and Harmonic Leakage under Config > FFT. See the Configuring an Evaluation Board section for more information.
FFT Bins: Changes the x-axis of the graph from frequency to bins.
Figure 24. Import Data Dialog Box
2. Type the file path in the dialog box or click Browse to search for the file. Then click OK. The time-domain data is graphed in a new window.
CONFIGURATION FILES Use these procedures to maintain configuration files in ADC Analyzer: 3. Right click the graph to open the hidden menu and select
Lock Data from the menu (see Figure 21 and Figure 22). • To add a useful comment to your configuration file, select File > Configuration File > Comments. The Config File Comment dialog box appears (see
4. To perform an FFT on this data, click FFT. Figure 23).
To import raw time domain text data in decimal format: • To load a configuration file, select File > Configuration
File > Load Configuration File. 1. Select File > Import Data. The Import Data dialog box appears, as shown in Figure 24.
• To save a configuration file, select File > Configuration File > Save Configuration. 2. Click the ASCII File button. The Import ASCII Text File
dialog box shown in Figure 25 opens. This window is used to give ADC Analyzer information about how to interpret the text data file. If any of these input parameters are not correct, both the time and FFT data are not correct.
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3. Check the following: • Data Bits: Select the resolution of the ADC. • Samples: Select the number of samples in the file. • Data Format: Select the format of the ADC output data. • Justification: Normally, the data exported from ADC
Analyzer is MSB_Justified. When importing data, be sure to select the proper justification.
• Encode Frequency (MHz): Enter the sampling clock rate used.
Figure 23. Config File Comment Dialog Box
• ASCII Text File to Import: Click Browse to search for the file.
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To construct a .csv file to import to ADC_Analyzer, the format of the sample .CSV file must be followed. Use these steps to create a sample file.
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1. Generate a template file with ADC_Analyzer that mirrors in content the type of data you have (time data for samples, FFT data for frequency content, and so on.). See the section on Zooming and Exporting Data.
2. Open the new template file with MS Excel.
3. Paste the desired data over the template file you previously generated. Also, modify any parameters necessary to describe the data. For example, if you have 16384 samples (16 kB samples), paste the amount of samples (16384) into the cell directly below the Samples cell. Then paste the desired 16384 raw data samples under the RawTimeData cell. Other parameters can be changed in the same manner, but are not necessary for the import to work properly.
Figure 25. Import ASCII Text File Dialog Box This procedure works most easily with Microsoft Excel. A .CSV
file can be constructed with a text editor such as Notepad, but, as shown in
4. Click OK. The time-domain data is graphed in a new window. Right-click the graph to open the hidden menu. Select Lock Data from the menu (see
Figure 27, Notepad does not provide the column alignment that Excel provides. Figure 21 and
Figure 22).
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5. To perform an FFT on this data, click the FFT button.
Importing .CSV Files
Figure 26 shows a comma separated value or comma delimited file (.CSV) formatted in Microsoft Excel. The .CSV file not only includes raw time domain data, but extra parameters such as Device, Device Number, Analog Frequency, Encode Frequency, Average (value), (number of) Bits, Max (value), Min (value), Range (of values), (amount of) Samples, AVCC, DVCC, XMaxTime, XMinTime, YMaxTime, YMinTime, Date, Time, Device Temperature, and Comments.
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Figure 27. Import ASCII Text File Using Notepad
Figure 26. Import .CSV File Using MS Excel
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Importing ASCII Files SAVING FILES Only raw time domain data is used in an ASCII file format that is imported to ADC Analyzer. No specifications, words, extraneous characters, spaces, commas, or tabs can be placed in the ASCII file.
There are three ways to save an image in ADC Analyzer:
• To save the active window in bitmap or JPEG format, select File > Save As > Save Active.
• To save each open window as a separate bitmap file, select File > Save As > Save List.
Figure 28 shows a sample portion of an ASCII file. Note that the entire ASCII file consists of time domain samples such as that shown here.
• To save the entire screen as a bitmap file, select File > Save As > Save Screen.
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4PRINTING There are several printing options available in ADC Analyzer:
• To print the active window, select File > Print > Print Active.
• To print the entire screen, select File > Print > Print Screen.
• To print more than one open window, select File > Print > Print List. A dialog box appears so you can choose which windows to print (see Figure 29). To print all open windows, click Print All.
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Figure 28. ASCII File Sample
Figure 29. Printing Options
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ADDITIONAL FUNCTIONS
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Two additional functions are available with the virtual evaluation board feature. As shown in Figure 30, you can perform an analog frequency sweep or an analog amplitude sweep. (These functions are only enabled while using ADIsimADC.)
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Figure 30. Sweep Mode Options
AMPLITUDE SWEEP (VIRTUAL ADC ONLY) 1. Before you can select an amplitude sweep, the frequency
for the amplitude sweep must be set on the ADC Modeling form under the Input tab.
2. From the ADC Analyzer main menu, select Sweep > Analog Amplitude Sweep. As shown in Figure 31, the Amplitude Sweep Configuration dialog box appears.
Figure 31. Amplitude Sweep Mode Options
3. Complete the fields in this dialog box as described in Table 2.
Table 2. Analog Sweep Configuration Options Option Description Start Amplitude (dB) Sets the starting level of the amplitude sweep. This is relative to the dc full scale of the converter. This number
should always be lower than the stop amplitude. Stop Amplitude (dB) Sets the stopping level of the amplitude sweep. This is relative to the dc full scale of the converter. This number
should always be larger than the start amplitude. Step Size (dBm) Indicates step size used for each amplitude step. This number should always be positive. There is no limit to the
size of the step. However, the smaller the step, the longer the sweep requires to complete. Likewise, the larger the step, the lower the resolution of the sweep.
Reference Line Draws a reference line used for comparison to the SFDR of the unit. SNR Reference Line Draws a reference line used for comparison to the SNR of the unit. FFT Determines if single or average FFTs are used during the sweep. SFDR vs. Amplitude Enables SFDR vs. amplitude results. SNR vs. Amplitude Enables SNR vs. amplitude results. 2nd Harmonic Enables 2nd harmonics vs. amplitude results. 3rd Harmonic Enables 3rd harmonics vs. amplitude results. 4th Harmonic Enables 4th harmonics vs. amplitude results. 5th Harmonic Enables 5th harmonics vs. amplitude results. 6th Harmonic Enables 6th harmonics vs. amplitude results. Worst Other Spur Enables worst other spur vs. amplitude results. Results FullScale Refers all measurements to full scale (dBFS). When not selected, measurements are relative to the signal (dBc). Datalog to Disk Writes all data to a file in the default data directory. The data format is an ASCII readable .CSV file. Datalog to Screen Displays graphs of each of the selected plots to be displayed on the screen after completion of the sweep. Datalog Plots to File Writes each bitmap plot to the default data directory. Datalog Plots to Printer Sends each bitmap plot to the printer.
ADC Analyzer User Manual
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ANALOG FREQUENCY SWEEP (VIRTUAL ADC ONLY)
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1. Before you can select an frequency sweep, the amplitude for the sweep must be set on the ADC Modeling form under the Input tab.
2. From the ADC Analyzer main menu, select Sweep > Analog Frequency Sweep. As shown in Figure 32, the Frequency Sweep Configuration dialog box appears.
3. Complete the fields in this dialog box as described in Table 3.
Figure 32. Frequency Sweep Mode Options
Table 3. Frequency Sweep Configuration Options Option Description Start Frequency Sweep (MHz)
Sets the starting frequency of the frequency sweep. This number should always be lower than the stop amplitude.
Stop Frequency Sweep (MHz)
Sets the stopping frequency of the frequency sweep. This number should always be larger than the start amplitude.
Step Size (MHz) Indicates the step size used for each frequency step. This number should always be positive. There is no limit to the size of the step. However, the smaller the step, the longer the sweep requires to complete. Likewise, the larger the step, the lower the resolution of the sweep.
Reference Line Draws a reference line used for comparison to the SFDR of the unit. SNR Reference Line Draws a reference line used for comparison to the SNR of the unit. FFT Determines if single or average FFTs are used during the sweep. SFDR vs. Frequency Enables SFDR vs. frequency results. SNR vs. Frequency Enables SNR vs. frequency results. 2nd Harmonic Enables 2nd harmonics vs. frequency results. 3rd Harmonic Enables 3rd harmonics vs. frequency results. 4th Harmonic Enables 4th harmonics vs. frequency results. 5th Harmonic Enables 5th harmonics. vs. frequency results. 6th Harmonic Enables 6th harmonics vs. frequency results. Worst Other Spur Enables worst other spur vs. frequency results. Results FullScale Refers all measurements to full scale (dBFS). When not selected, the measurement is relative to the signal (dBc). Datalog to Disk Writes all data to a file in the default data directory. The data format is an ASCII readable .CSV file. Datalog to Screen Displays graphs of each of the selected plots on the screen after completion of the sweep. Datalog Plots to File Writes each bitmap plot to the default data directory. Datalog Plots to Printer Sends each bitmap plot to the printer.
ADC Analyzer User Manual
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TROUBLESHOOTING 3. Use the Analyze > Bus Check option to ensure all of the
data bits are switching. FLAT LINE SIGNAL DISPLAYED Scenario: When you click Time Data, the signal displayed in the window is a flat line. 4. Ensure that Twos Complement is set correctly in the FFT
Configuration dialog box. If Twos Complement is selected and the ADC outputs are not in twos complement format, a time-domain plot may look like that shown in
1. Check the power connections.
2. Verify that the USB cable does not exceed 5 feet in length. Figure 34.
3. Check the cable connection between the PC and the FIFO board. If applicable, ensure the correct parallel port is selected (LPT1 or LPT2) in the Buffer Configuration dialog box.
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4. If you are using a parallel port, make sure the printer port in the computer BIOS is set to Standard Bidirectional.
5. Make sure Channel A, Channel B, or both channels are selected in the Channel Select dialog box.
6. Check the signal connections and make sure that the clock is present at the output of the ADC evaluation board.
7. Verify that data bits are switching at the connection point between the FIFO and the ADC evaluation board.
Figure 34. Incorrect Setting for Twos Complement
5. Adjust the timing to ensure that the data is captured correctly. Refer to 8. Use the Analyze > Bus Check or the Analyze > Logic
Analyze option to ensure all data bits are switching. See www.analog.com/hsc-FIFO for more
information. Figure 15 for an example of the AD6645 14-bit single-channel ADC. (Note: The left-most bit is the MSB.)
6. Try using a very low frequency analog input (such as 0.1 MHz to 1 MHz) to debug timing issues. For an exact number of cycles, such as 10, try (10 × fs)/M, where fs = encode frequency and M = sample size (2
9. Use the ADC data sheet to ensure all jumper connections are set appropriately on the ADC evaluation board. Ensure the ADC power-down option is not active.
N).
7. Check for problems with the common-mode level at the analog input by looking at the time data with no analog input signal.
DISPLAYED SIGNAL UNLIKE ANALOG INPUT
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FFT NOISE FLOOR HIGHER THAN EXPECTED Scenario: The noise floor of the FFT is higher than expected, which is often traced back to timing issues in the clock path.
1. Put a very slow sine wave signal into the ADC (such as 0.1 MHz to 1 MHz) and initiate a time-domain plot. If the plot looks similar to that shown in Figure 35, there are timing issues.
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Figure 33. Typical Time Domain Plot
Scenario: When you click Time Domain, the signal displayed does not look like the analog input signal.
1. A fast sinusoidal signal may look like a solid red block in the time-domain window (due to the number of sine waves shown). Right-click the window for options to zoom in for a closer view of the signal.
2. Check the cable connection between the PC and the FIFO
board. If applicable, ensure the correct parallel port is selected (LPT1 or LPT2) in the Buffer Configuration dialog box. Check the signal connections.
Figure 35. Example of How Timing Issues Affect the Noise Floor
ADC Analyzer User Manual
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2. Switch Jumpers J304 and/or J305 to their alternate positions to invert the clock.
2. Be sure the channel selected in the Interleaved Priority dialog box is correct.
3. The four XOR gates of U302 can be used to insert delay into the high speed clock path or to invert the clock to optimize timing. Try moving Jumper J314 and Jumper J315 to their alternate position. This should allow enough flexibility for you to adjust timing under any conditions.
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4. To gain even finer adjustments, use the installed trim potentiometer, R312 and R315. To undo the default bypass, the solder Jumper J310 to Jumper J313 must be removed first.
Figure 38. Interleaved Priority
LARGE SPUR IN FFT (IMAGE PROBLEM) 3. Perform another FFT. The spur should disappear. Scenario: There is a large spur in the FFT (image of the fundamental) when evaluating the demultiplexed outputs (see
MSBs MISSING FROM TIME DOMAIN Figure 36).
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Figure 39. Incorrect Bit Mask Setting Figure 36. Demultiplexed Image Problem
Scenario: Two MSBs are missing from the time domain plot. 1. Select Config > Channel Select to open the Channel Selection dialog box shown in Figure 37. 1. If you are evaluating the AD9200, AD9201, AD9280, or
AD9281, default configuration files for these ADCs are installed with ADC Analyzer. Make sure the appropriate bits are selected in the Bit Mask dialog box, as follows:
Be sure the Interleaved Data box is selected and click OK. Note that Channel A in the software corresponds to Channel 1 on the FIFO schematics and the bottom FIFO on the evaluation board. Channel B corresponds to Channel 2 on the FIFO schematics and the top FIFO on the evaluation board (closest to the Analog Devices logo).
• Bit 13 to Bit 4 should be selected for the AD9200 and AD9201.
• Bit 13 to Bit 6 should be selected for the AD9280 and AD9281.
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2. Make sure the bits are switching at the FIFO connector.
Figure 37. Channel Selection
ADC Analyzer User Manual
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APPENDIX: SAMPLING AND FFT FUNDAMENTALS COHERENT SAMPLING The weighting function for a Hanning window is:
In a coherent system, the analog and clock sources must be synchronized, and the analog and clock input frequencies must be selected such that given 2
⎟⎟⎠
⎞⎜⎝⎛ ×
×−=M
nWn
2πcos0.50.5
N (N is an integer number) samples, there is an integer number of whole sine wave cycles. The number of cycles should ideally be a prime number. Selecting a prime number ensures that the same converter codes are not repeated over and over, therefore exercising as many converter codes as possible. Although a crystal oscillator can be used as a clock source in this technique, two synchronized signal synthesizers are generally preferred because special hardware is sometimes required to ensure the crystal oscillator is synchronized with the analog source. The following equation can be used to mathematically calculate the correct analog and clock frequencies for a coherent system:
where:
M = Sample size(2 ) N
n = Indexed sample number
FFT CALCULATIONS Whether a system is coherent or a windowing function has been applied, the resulting data is processed via a discrete Fourier analysis that translates the discrete time-domain samples into the frequency domain. A Fast Fourier Transform (FFT) is used, which is simply an algorithm that reduces the required mathematical calculations. There are many FFT algorithms available but the most popular is the radix 2 algorithm. Regardless of the algorithm, for each time-domain sample a complex conjugate pair (r ± jx) is generated from the FFT. For example, if the time-domain sample size is 16,384, the resulting FFT array contains 16,384 complex samples. To generate a frequency domain plot from this data, the magnitude of each complex sample must be calculated. The magnitude can be computed using the following equation:
CS
IN
MM
ff
=
where:
fIN = Analog input frequency
fS = Sampling clock (encode) frequency
M = Sample size (2 ) N
MC = Number of sine wave cycles 22 ImReMagnitude +=
If the requirements of the coherent system defined here are not met, the discrete time samples appear discontinuous at the end of the captured samples and the results are invalid.
If the input data to the FFT is complex, the FFT contains 16,384 magnitudes representing frequencies between plus and minus fs/2. Although complex ADCs are not available, it is very common to use two ADCs to synchronously sample the I and Q data streams from a quadrature demodulator. If the data input to the FFT is real, representing the data from a single ADC, the last 8192 samples represent a mirror image of the first 8192 samples. Because this is an exact mirror image, the last 8192 samples can be ignored.
WINDOWING FUNCTIONS It is sometimes desirable to use a windowing function instead of coherent sampling to reduce the restrictions on the analog and encode sources. Two popular windowing functions are the Blackman Harris 4-Term and the Hanning window. With windowing, the time-domain samples are multiplied by the appropriate function that weights the time-domain data such that the discontinuities at the end of the captured samples have less significance. The weighting function (W
With the data set processed, there are two ways to evaluate the ADC performance, graphically and computationally. To plot the data in a meaningful way, the magnitude data must be converted to decibels (dB). This can be done with the formula:
n) for a Blackman Harris 4-Term window is:
⎜⎜⎝
⎛⎟⎠
⎞×π×−⎟⎟
⎠
⎞⎜⎝
⎛ ×π×+⎜⎜
⎝
⎛⎟⎠
⎞×π×−=
Mn
a3M
na2
Mn
a1a0Wn32
cos22
cos2
cos ⎜⎜⎝
⎛⎟⎠⎞×=
FullScaleMagnitude
10log10dB
where: where Magnitude is the individual array elements computed above, and FullScale is the full-scale magnitude. The computa-tion for dB assumes the square root was not actually taken in this equation, leaving the magnitude expressed as the sum of two squares. Therefore 10 × log is used instead of 20 × log, eliminating the time required to compute the square root.
a0 = 0.35875
a1 = 0.48829
a2 = 0.14128
a3 = 0.01168
M = Sample size (2 ) N
n = Indexed sample number
ADC Analyzer User Manual
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Noise_Energy represents the summation of all the noise energy in the spectrum, and Fundamental_Energy represents the summation of the fundamental energy. The fundamental energy resides in a single bin if a coherent system is used; however, in the case of a windowing function, it may be spread over 10 bins to 25 bins, depending on the windowing technique.
Based on Nyquist theory, the encode rate must be at least twice the signal bandwidth to faithfully represent the signal when sampled. Therefore, if the encode rate is 80 MHz, an ADC can only represent 40 MHz of continuous bandwidth. Knowing the encode rate and the number of time-domain samples, the frequency representation per bin can be established. In this example, the encode rate is 80 MHz and there are 16,384 time-domain samples; therefore, 4880 Hz/bin is represented. If the encode rate is doubled or the number of time-domain samples is doubled, a 3 dB improvement in the noise floor is observed. This does not represent an improvement in ADC performance, but simply represents an increased resolution per bin.
Harmonics can be defined as the ratio of the rms signal amplitude to the rms value of the harmonic component, reported in dBc. Harmonics represent the nonlinearities within the ADC and are integer multiples of the fundamental. If the harmonic exceeds fs/2, it is aliased back into the first Nyquist zone. A concept closely related to harmonics is SFDR. For an ADC, SFDR is defined as the ratio between the rms amplitude of a single tone and the rms amplitude of the worst spur as the tone is swept through the entire ADC input range. It is very common for the worst spur to be harmonically related.
From the computations above, it is now possible to define and calculate SNR, SINAD, harmonics, SFDR, ENOB, and noise figure. The signal-to-noise ratio can be expressed as the ratio of the rms signal amplitude to the rms value of the sum of all other spectral components, excluding the first six harmonics and dc, or by the equation:
Whereas SNR excludes the first five harmonics, SINAD includes these harmonics as part of the Noise_Energy summation, otherwise known as total harmonic distortion, or THD. If the harmonic performance of the ADC is excellent, there is very little difference between the SNR value and the SINAD value.
dBlog20 10⎜⎜⎝
⎛⎟⎟⎠
⎞×=
gyNoise_Enerl_EnergyFundamentaSNR
ADC Analyzer User Manual
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NOTES
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NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. G05741-0-4/06(0)
