Adaptive runtime system with intelligent allocation of ... · Development and application of HW / SW partitioned systems. Increased usage of software. Increased complexity of the

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DirectorsProf. Dr.-Ing. K.D. Müller-Glaser

Prof. Dr.-Ing. J. BeckerProf. Dr. rer. nat. W. Stork

Institute for Information Processing Technology

Karlsruhe Institute of Technology (KIT)DFG Abschlusskolloquium Karlsruhe

Adaptive runtime system with intelligent allocation of dynamically reconfigurable functions and optimized

interface topologies - ALadyn

Jürgen Becker, Klaus Müller-Glaser, Tobias Schwalb, Lars Braun, Michael Hübner, Philipp Graf

© Institute for Information Processing Technology 20092 | KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH)

Agenda

Overview of the ALadynapproach

Hardware-SystemEvolution of the run-time reconfigurable hardware 2D – Online routing of functional unitsAdaptive 2D NoC approachBitfile analysis tool

System modelingIntegrated toolchainModel based debuggingModel based development process and tests

Cooperation

List of publications

Conclusions and outlook


Pervasiveness of embedded systems

Infotainment

Signal processing / Communications

Office

Data processing

Aerospace

Feedback control

Automotive

Feedback control

Microelectronics as embedded system is essential for a variety

of applications


Development and application of HW / SW partitioned systems

Increased usage of software

Increased complexity of the functions

⇒ New design techniques required

Increased demand of performance, power

consumption, safetyness

Embedded HW-Systems with processor centric

solutions. ⇒ ASICS expensive!

Customer anticipates new function

Reduced product lifecycle (< 2 year!)

Increased costs for hardware and


Development and application of HW / SW partitioned systems

Increased usage of software

Increased complexity of the functions

⇒ New design techniques required

Increased demand of performance, power

consumption, safetyness

Embedded HW-Systems with processor centric

solutions. ⇒ ASICS expensive!

Customer anticipates new function

Reduced product lifecycle (< 2 year!)

Increased costs for hardware andPure processor based

solutions come to the limit

Performance and data throughput

Desigspace and risk of high costs

Power dissipation, reliability

Long term support / maintainability

Deployment of flexiblereconfigurable

hardware as onepossible solution


Aladyn: System Overview

Application1(MP3-Player)

Application2(Video)

Application3(Carcontrol)

Application4(Collision protection)

Opcode/Bitstream-Repository (FLASH)

Local runtime-control (FPGA)

Modul/Funktion

Modul/Funktion

Local runtime-control (e.g. Amurha)

Modul/Funktion

Modul/Funktion

Bus-Macro

Arbiter

Module 1

Bus Com 1

ID 1

Module 1

Bus Com 1

ID 1

Module 2

Bus Com 2

ID 2

Module 2

Bus Com 2

ID 2

Module 0

Bus Com 0

ID 0

Module 0

Bus Com 0

ID 0

Module 3

Bus Com 3

ID 3

Module 3

Bus Com 3

ID 3

Run-timeModule

Controller

µController(MicroBlaze)

ICAP

DecompressorUnit (LZSS)

Buffer

CAN-Interface

Buffer

Buf

fer

HW-Layer API (Data, Functional negotiation , Reconfiguration)

Function distribution management

Local runtime-control (GP-Proc.)

APPLICATION-API (QoS, Function, Communication)

CPU

CBR-based Function-/ HW-Resources selection


Run-time System: QoS-based function realization

Application services / start of sub-functionsDifferent HW/SW realizations possible (FPGA, DSP, GP-Proc., ASIC etc.)Introduction of quantifieableQoS-MetricsDescription through a set of comparable attributes

Evaluation of suitable function realizationsFunction description in database with QoS-related data setsComparison of the QoS-descpription of the requirements with the data base entriesSelection by application of a simlarity metric (distance)

Approach from knowledge based systemsAdaptation of the case based reasoning


Case-Based-Reasoning-CycleAI research early 80’sKnowledge stored in cases.Case as pair of

Problem / SolutionNo rule-sets

Find case(s) matching best to new problem

Adapt found solution(s)Test solution(s)Keep solution/ problem as new case if proved to be useful.

NewCaseRetrieved

Case

ConfirmedSolution

Tested/Repaired

Case

SolvedCase

SuggestedSolution

Knowledge

CaseBase

LearnedCase

NewCase

Problem

Source: Aamodt & Plaza, AI Communications 1994

Current focus


HW - Reconf.Control

Interface to application-layer

Local FPGAx-Run-timeControl

Module-Reconf.

Request / Attributes

HW-CBR-

Retrieval

Allocation-Management

HW-sub-devices(FPGA, DSP etc.)Allocation-

Management

HW-CBR-Retrieval – System Context

Low-level functional description

Implementation DatabaseCB-MEM

GlobalMetrics

extract

Request usingLow-level-Metrics

CBR-Retrieval

Suitablerealization

GrantRequest/ QoS

Check for feasibility of found solution

Reconfigure


FPGA – CBR Retrieval UnitXilinx Virtex II 3000

• CLB-Slices:441 of 14336 ≈3 %

• MULT18X18s:2 of 96 ≈2 %

• BRAMS(18Kbit):2 of 96 ≈2 %

• Max. Clock: ≈ 77 MHz

• Bottleneck: size of CB

• Software Version: • MicroBlaze @ 66 MHz• 1984 bytes opcode• 1208 bytes variables• approx. 8.5 times slower

Type Ai_CBw i

CB-MEM

ABS(X)

A i

Ai_CBType A i

Diff(Ai,A_i_CB)

Si

0Exist Ai_CB

TEMP

Smax

?

Req_Mem_Addr.

CB_Data

S=Σ Si*wi

Req-MEM

Req_Data

Realis_ID ID

Smax

Realis_ID_max IDmax

?

New_Req Req_Ptr

CB_Mem_Addr.

(1+Dmax_i)-1

CTRL(incl.Mem_ptr)

Req


Evolution ofAladyn

1 Dimensional PDR SystemFix module sizeFixed communication topology

Not adaptable to the needs of the System

Introduction of LUT-based Bus-Macros Context Load & SaveBitstream compressing

BM

RuntimeSystem

Module0

BusCom0

Module1

Module2

Module3

BusCom1

BusCom2

BusCom3

Arbiter


Evolution ofAladyn

1 Dimensional PDR SystemFix module sizeFixed communication topology

Not adaptable to the needs of the System

Introduction of LUT-based Bus-Macros Context Load & SaveBitstream compressing

BM

RuntimeSystem

Module0

BusCom0

Module1

Module2

Module3

BusCom1

BusCom2

BusCom3

Arbiter


DaimlerChrysler AG:

FPGA System: I-Cell

Reconfiguration in Automotive ECUsAnalysis:Design Alternatives- μC vs. FPGA vs. ASIC

Demo Application:Cabin Functions

Goals:•-> Reduction of Architecture Variants• -> Easy Life-Cycle Updates• -> Complexity Reduction (Verification!)

FPGAs Xilinx Virtex XC2V3000

# Framesper Slot


FPGA based Reconfigurable System: On-Demand Functions

Bus-Macro

Arbiter

Module B

Bus Com 1

ID 1

Module C

Bus Com 2

ID 2

Module A

Bus Com 0

ID 0

Module E

Bus Com 3

ID 3

Run-timeModuleController


Flash-MemoryBootstream

Slotstream

s

Boot-CPLD

I/O (e.g. CAN)

ICAP


Buffer

CAN-Interface

Buffer

Buf

fer

MA MB

MC MD

Search Slot Backup state Start Reconfiguration Restore state

Module D

Bus Com 2

ID 2

Save State!

State - Data

MD

Start addressEnd address

Last Bus-WordState - Data


FPGA based Reconfigurable System: On-Demand Functions

Bus-Macro

Arbiter

Module B

Bus Com 1

ID 1

Module C

Bus Com 2

ID 2

Module A

Bus Com 0

ID 0

Module E

Bus Com 3

ID 3

Run-timeModuleController


Flash-MemoryBootstream

Slotstream

s

Boot-CPLD

I/O (e.g. CAN)

ICAP


Buffer

CAN-Interface

Buffer

Buf

fer

MA MB

MC MD

Search Slot Backup state Start Reconfiguration Restore state

Module D

Bus Com 2

ID 2

Save State!

State - Data

MD

Start addressEnd address

Last Bus-WordState - Data

Real Car feasibility study:First prototype presentet at DATE 2005 Conference

Central control unit


First Prototype: Real Car FeasibilityDemonstration


DATE 2006 and DATE 2008 Demonstrator

LIN

LIN

LIN

LIN

ROOFCAN

BODY CAN

Message RoutingModule

CTRLModule MicroBlaze

GNoCMaster

NMAdminFct.

CANCore

CANCore

CAN Interface

USBModule

GNoC-Network

LINModule

LINModule

LINModule

LINModule

Highlights:• Standardized Peripherals as Drivers

(Intelligent Actuators and Sensors)• New Topology• New System Architecture


Evolution ofAladyn

System is adaptable to the communication needs of the modules

Module size still fix

Additional Arbiter needed

B0B1B3B2

PMM3

Bus

M2M0 M14 44 44

Module0

Module1

Module2

Module3

RuntimeSystem

Arbiter


Evolution ofAladyn




B0B1B3B2

Module0

Module1

Module2

Module3

RuntimeSystem

Arbiter M1

Star

B1

B2

B0

PM

M0

M2

B3 M3


Evolution ofAladyn




B0B1B3B2

Module0

Module1

Module2

Module3

RuntimeSystem

Arbiter

PM

M0

M1

B0

B2B1M2

B3

Ring


Evolution ofAladyn

SwitchBoxes and communication are controlled by ICAP

No Arbiter needed

Configuration of the Switchboxes by Read-Modify-Writeback

Different topologies feasible

Module0

Module1

Module2

Module3

BMSB BM BM BM

RuntimeSystem

SB SBSB


2 Dimensional Configuration possible

Read-Modify-WritebackVirtex 4 Archirecture and follower

Free placement of ModulesChanging of Network topologies

Evolution ofAladyn

BM BM

BM

BM

BM

Run-TimeSystem

FunctionalUnit

FunctionalUnit

FunctionalUnit

SB SB

SB

FunctionalUnit

SB


2 Dimensional Configuration possible

Read-Modify-WritebackVirtex 4 Archirecture and follower

Free placement of ModulesChanging of Network topologies

Evolution ofAladyn

BM BM

BM

BM

BM

Run-TimeSystem

FunctionalUnit

FunctionalUnit

FunctionalUnit

SB SB

SB

FunctionalUnit

SB

• Positioning at run-time• Variable bit width• No additional control signals• Resource requirements as low as possible• Modification and adaptation of the topology

• Positioning at run-time• Variable bit width• Length and course adaptable to

the placement of the FEs

• Positioning at run-time• Generating at run-time• Adjusting of the bit width and the

functionality during run-time

• Positioning of the FE• Positioning of the Switch Boxes• Routing of the Bus-Macros• Generating of the functional units• Caching of pre-routed functional

units


Online Routing of functional units

BM

BM

Run-TimeSystem

&Bitstream-

packer

+ -

x

/ + -

x

/



BM

BM

Run-TimeSystem

&Bitstream-

packer

+ -

x

/ + -

x

/

StaticSystem

Submodule

Routingtemplate



BM

BM

Run-TimeSystem

&Bitstream-

packer

+ -

x

/ + -

x

/

StaticSystem

Submodule

Routingtemplate

Innovation:• Increased flexibility due to adaptation of the functional blocks, to the physical chip

size and requirements at runtime• Additional degrees of freedom for the dynamic allocation by an architecture-

independent description of the function blocks• Changeable granularity of macro-blocks• Simple adjustment of the functional units to changing challenges


Adaptive 2D NoC Architektur

MU

XM

UX

MU

XMUX

GlueLogic

µC

XX

XX

ICAP

X



MU

XM

UX

MU

XMUX

GlueLogic

µC

XX

XX

ICAP

X



MU

XM

UX

MU

XMUX

GlueLogic

µC

XX

XX

ICAP

X



MU

XM

UX

MU

XMUX

GlueLogic

µC

XX

XX

ICAP

XInnovation: • Manipulation of the LUT based multiplexer via ICAP• Information of the LUTs is stored in two frames fast switching• No direct connection needed between controller and switch Reduced overhead

on the chip surface• Modularize structure adjustment on bit width is possible at runtime• Uses available resources to control the switches (ICAP)• C library to control the switches by the embedded processor• Switch-box generator for generating parameterized switchboxes

• Switching time @ Virtex 2 Pro 30 (1648 byte): approx. 330 µs• Switching time @ Virtex 4 (320 byte): approx. 65 µs• Size of fife Way 10 Bit Switch: 9 CLBs


Online 2D Routing

Run-TimeSystem

FunctionalUnit

SB


Online 2D Routing

Run-TimeSystem

FunctionalUnit

SB

Innovation:• Better utilization of reconfigurable area• Integration of Network-on-Chip (NoC) approach to allow inter-module

communication• Generic approach for a variety of applications• Various topologies are feasible by Switch approach• Good and fast path finding heuristic (A *)• Implementing of path finding algorithm on PowerPC

• Time requirement for A*routing to find a way from position (1/2) to position (17/15): approx. 2 ms

• Bus macros to be placed: 8 • Time requirement for reconfiguration approx. 18 ms (Xilinx HW-ICAP)

approx. 1 ms (PLB ICAP)

© Institute for Information Processing Technology 200933 | KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH)33 |

BitFileParser - ToolUniversal tool for working with bitstreams

Parsing of bitstreams (FPGA independent)Visualization of the resource consumption of FPGAs (V2 / V2Pro / Virtex4)Visualization of routing resources(SwitchMatrix) (V2 / V2Pro / Virtex 4)Display the contents of a logic block (CLB + SM) (V2 / V2Pro / Virtex 4)Readback via JTAG (V2 / V2Pro / Virtex4)Generation of partial bitstreams for RMW (V2 / V2Pro)Editing of LUT / BRAM content (V2 / V2Pro)Generation of partial and complete bitstreams similar to PartialMask(V2 / V2Pro)Import of partial bitstreams(V2 / V2Pro)


2-dimensional runtime reconfigurable system and model based design support

BM BM

BM

BM

BM

Runtimesystem

Functional‐Unit

Functional‐Unit

Functional‐Unit

SB SB

SB

Functional‐Unit

SB

Model driven development

and tool chain

Debug on model level

Model basedtests


System modeling

Modeling:Top-level architecture (UML)Template for allocation manager (UML)Interface for function types (UML)Attributes of functionrequirements (UML)Attributes of realization alternatives (UML)Realization alternatives for sub functions(UML / Simulink / Stateflow)

Integrated model based design flowTop-Level modeling based on the Unified Modeling LanguageModeling using adapted notations for architecture, function, resources, …Integration of additional notations (Simulink, …) using model transformation


Integrated tool chain

Integrated, highly coupled aggregate modelProcess modeling

Aligns the individual design steps: model processing, code generation, compile, synthesis, deployment, debugger configuration, reconfiguration, …Practicability of the model

Platform modelingIncludes the numbers, parameters of the execution units and data flowsAbility to refer to dynamic network on chip and 2D-Reconfiguration

Function modelingServices of the execution units

Functionmodeling

Processmodeling

Platformmodeling

processes

uses configuresModel


Model based debugging

In model-driven development, a representation and manipulation of the system state is needed on the design notation levelDebugging of executable models across the boundaries of heterogeneous notations as well as across different execution unitsAvoids additional complexity and semantic equivalence problems by additional modeling of the associated environment and interfacesGenerated adapted independent interfaces

Non real time / real timeNo influence / influence on systemBlack-Box / White-Box debugging


Model based development process

Model

AutomaticCode Generation

ImplementationMap, Place & Route

SignalRecording

Binary

Debugging

Interpretation& Mapping

Target

Execution

Develops Informs

Refers to

User

ARCHITECTURE fsm_SFHDL OF Car_dominated ISSIGNAL is_Car_dom : type_is_Car_dom;SIGNAL PedFinished : std_logic;SIGNAL is_Car_dom_next : type_is_Car_dom;

BEGINinitialize_Car_dom : PROCESS (clk, reset)BEGIN

IF reset = '1' THENis_Lights <= IN_NO_ACTIVE_CHILD;y1_reg <= to_unsigned(0, 3);

ELSIF clk'EVENT AND clk = '1' THENy1_reg <= ‘1’;

VHDL-Code010101010111001001010100001001111110110000011001101100010100110111001000101100011100011100011100010010101100010011010110100111011010000011001010101110111101001101010011100110101010101110010010101000010011111101100000110011011000101001101110010001011000111000111000111000100101011000100110101101001110111010101011100100101010000100111111011000001100110110001010011011100100010110001110001110001110001001010110001001101011010011101101000001100101010111011110100110101001110011110011001101001100100110110010011001001100011101011101110111000111

Signal-DataReal time

InformationSource


On-chip model debugging for FPGAs

Different on-chip debuggersReal time tracingAdvanced trigger methodsMinimal influence on systemIndividual setup during runtimeBacktracking to model

Standard System:3,2 Gbit/s to On-Chip Ram, Simple Triggers, No compression

Uses only 1% of Xilinx XC2VP30Advanced System:

12,8 GBit/s to On-Chip Ram, Advanced Triggers, Lz77 Compression

Uses 14% of Xilinx XC2VP30


Debugging dynamic systems

Bitstream readback using JTAG-interface or internal ICAPNo impact on design under testMinimal or no additional on-chip system neededReal time Snapshot and only non real time recording possibleInterpretation of bitstream up to model level based on xdl-Files, synthesis report and model information

Possible integration of debugger in partial dynamic platformIntegration as functional unitDebugging other functionalunits using the NoCDebugging NoCDebugging static runtimesystem


Debugger softwareRepresentation of recorded inputs, outputs and internal signalsHighlight of active StatesFree movement forward and backward in recorded traceIndependent graphical representation

Control of the debugger during runtime without reimplementation

Control Design under Test using Reset-signal and Clock-EnableSet recording start & -end to conditions or point in time(Pre-trigger recording possible)Set up trigger conditions (comparator and switch matrix)


Model based tests

Generative approachEasily customizableRepeatableComprehensive

Same syntax for testing on different platforms

Automatic generation of tests according to the models

Test results represented by models to allows easy comprehension and documentation

Model

Tests

System

Describes

Results

Generates

Runs

Analysis of behaviour

Visualization

User


Model based tests

Specifying test using UML Use-Case and Sequence diagramsStructured tests, independent syntax, stimuli, expected response

Automatic execution on test platform


Model based tests

Specifying test using UML Use-Case and Sequence diagramsStructured tests, independent syntax, stimuli, expected response

Automatic execution on test platformXML based test report generation (Converting to HTML)


Test platform

HiL-SystemHardware Monitoring

FPGATest-Treiber

System under Test

SoftwareMonitoring

Messageto HiL

TesterGUI: Selection of test cases, startData- (Monitor-) conversion

Socket

ReportHTML, MS WordReport-

Generator

PCI PR-BoxRTAI, FPGA

ComClientSocket Message Adapter

Messagefrom HiL

Socket

Runcontrol

FPGA CPU


Socket

In-CircuitEmulator



Test platform

HiL-SystemHardware Monitoring

FPGATest-Treiber

System under Test

SoftwareMonitoring

Messageto HiL

TesterGUI: Selection of test cases, startData- (Monitor-) conversion

Socket

ReportHTML, MS WordReport-

Generator

PCI PR-BoxRTAI, FPGA


Messagefrom HiL

Socket

Runcontrol

FPGA CPU


Socket

In-CircuitEmulator


Real time Trace In-Circuit EmulatorMethod calls

Trace protocol allows reconstruction of the call stack at any time Senders and receivers of messages in sequence diagrams

Parameters Minimal instrumentation at runtimeAbility to reconstruct the parameters and return values

TestRealization of individual functions Functionality distribution manager

Ability to test dynamic function units


Conclusions

2-Dimensional physical placement of functional blocks at runtime Increased flexibility and architecture independence

Runtime adaptive NoC architecture with 2D-online routingConfigurable Topology-on-chip on-demand Enables application specific wiring during runtime

High-level fault diagnosis / monitoring and debugging by evaluating the information obtained

Restoration of the hardware functionality by taking advantage of the new degrees of freedom on-line placement and wiring (2 dimensional) Interface to high-level tools for debugging

Continuous modeling processesExpansion and integration modeling: platform, function, processesModeling and feasibility using integrated tool chains

Debugging at model levelIntegrated configurable real time hardware debuggerDebugging dynamic systems (readback and direct Integration)

Test Methodology Syntactically powerful definition of tests by UML diagramsProcessor and reconfigurable execution units as sources


Aladyn and next?

High-performance ComputingPlacing of variable accelerators and Microprocessors (Speed / Size / Area / low Power)

System partitioningIntelligent Task allocation and migrationHW / SW Co-design

Tool integrationValidation and Verification on heterogeneous platformsModel based Debugging and Test for distributed applicationsModel based control of systems

Migration of Aladyn techniques into different Platforms e.g. Morpheus


Cooperations

Prof. Dr.-Ing. Renate Merker, TU DresdenEntwicklung von Partitionierungsstrategien im Bereich dynamisch rekonfigurierbarer SystemeAnknüpfungspunkt: Reduzierte Rekonfigurationskosten und Verlustleistung durch Map-Werkzeug

Prof. Dr. Sandor Fekete, Technische Universität Braunschweig,Prof. Dr.-Ing. Jürgen Teich, Universität Erlangen-NürnbergReCoNodes - Optimierungsmethodik zur Steuerung hardwarekonfigurierbarer KnotenAnknüpfungspunkt: ESM als Integrationsplattform

Prof. Dr.-Ing. Andreas Herkersdorf und Dr.-Ing. Walter Stechele, Dipl.-Ing. Christopher Claus, TU MünchenReconfigurable Hardware Acceleration for Video-based Driver AssistanceAnknüpfungspunkt: On-Line Visualisierung der physikalischen Konfiguration für Debug Zwecke


List of publicationsBecker, J.; Hübner, M.; Hettich, G;Constapel, R.;Eisenmann, J.;Luka,J.:Dynamic and Partial FPGA ExploitationProceedings of the IEEE on Special Automotive Hardware, Spring 2007 Braun, L.; Perschke, T.; Schatz, V.; Bach, S.; Hübner, M.;Becker, J.:Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing ApplicationsFPL 2007, Amsterdam, The NetherlandsBraun, L.; Sander, O.; Becker, J.:An Exploitation of Data Reallocation by Performing Internal FPGA Self-Reconfiguration MechanismsARC 2008, London, GBGraf, P.; Reichmann, C.; Müller-Glaser, K.D.:A Model-Based Design Approach for a Dynamically Configurable Hardware-/Software-Architecture“, 3rd Workshop on Object-oriented Modeling ofEmbedded Real-Time Systems (OMER 3), Paderborn, Oktober 2005Graf, P.; Müller-Glaser, K.D.: Eine Architektur für die modellbasierte Fehlersuche in der Software eingebetteter Systeme“, Modellierung 2006, Workshop: Modellbasierte Entwicklung von eingebetteten Fahrzeugfunktionen, Innsbruck, März 2006Graf, P.; Müller-Glaser, K.D.: Dynamic Mapping of Runtime Information Models for Debugging Embedded Software“, 17th IEEE International Workshop on Rapid System Prototyping, Chania, Juni 2006 Graf, P.; Müller-Glaser, K.D.:Gaining Insight into Executable Models during Runtime: Architecture andMappingsIEEE Distributed Systems Online, vol. 8, no. 3, 2007Graf, P.; Reichmann, C.; Müller-Glaser, K.D.:Nonintrusive Black- and White-Box Testing of Embedded Systems Software against UML Models18th IEEE International Workshop on Rapid System Prototyping, Porto Alegre, Mai 2007Graf, P.; Hübner, M.; Müller-Glaser, K.D., Becker, J:A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures17th International Conference of Field Programmable Logic and Applications (FPL), Amsterdam, August 2007 Graf, P.; Müller-Glaser, K.D.:ModelScope: Inspecting Executable Models during Run-time30th international conference on Software engineering, Leipzig, Mai 2008

Hübner, M.; Schuck, C.; Becker, J.: Elementary Block Based 2-Dimensional Dynamic and Partial Reconfiguration for Virtex-II FPGAsRAW2006, Rhodos, GreeceHübner, M.; Becker,J.:Dynamic and Partial Reconfigurable Hardwaresystemarchitecture with Real-Time On-Demand FunctionalityDesign and Test in Europe Conference, PhD Forum DATE 2007, Nice, France 2007Hübner M.; Braun, L.; Becker, J.; Claus, C.; Stechele, W.:On-Line Visualization of the Physical Configuration of a Xilinx Virtex-II FPGAISVLSI 2007, Porto Alegre, BrazilHübner, M.; Braun, L.; Göhringer, D.; Becker, J.:Run-time Reconfigurable Apaptive Multilayer Network-on-Chip for FPGA-based SystemsRAW 2008, Miami, Florida, USAHübner, M.; Ullmann, M.; Becker, J.:Real-time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration - extended version, International Journal on Embedded Systems (IJES), vol. 1, no. 3/4, 2006, pp. 263-273.Paulsson, K.; Hübner, M.; Becker, J.:Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration, AHS2006, Istanbul, TurkeyPaulsson, K.; Hübner, M.; Becker, J.:On-Line Optimization of FPGA Power-Dissipation by Exploiting Run-time Adaption of Communication Primitives„ SBCCI 2006, BrazilPaulson, K., Auer, G.,Dreschmann, M., Chen, L.; Hübner, M.; Becker, J.:Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self- Reconfiguration on Xilinx Spartan III FPGAsFPL 2007, Amsterdam, The NetherlandsPiontek, T.; Albrecht, C.; Koch, R.; Maehle, E.; Hübner, M.; Becker, J.:Communication Architectures for Dynamically Reconfigurable FPGA DesignsRAW 2007, Long Beach, California USASchwalb, T.; Graf, P.; Müller-Glaser, K.D.: Architektur für das echtzeitfähige Debugging ausführbarer Modelle auf rekonfigurierbarer Hardware12th GI/ITG/GMM-Workshop Modellierung und Verifikation, Berlin, Germany, 2009


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Adaptive runtime system with intelligent allocation of ... · Development and application of HW / SW partitioned systems. Increased usage of software. Increased complexity of the