AD9670EBZ User Guide (Rev. 0) - analog.com · 12. The AD9670 is now running and fully configured for data capture mode. The VisualAnalog software offers two data capture modes: onetime

AD9670EBZ User Guide UG-1459

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the AD9670 Octal Ultrasound AFE with Digital Demodulator

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 15

FEATURES Fully featured evaluation board for the AD9670 PC software for controlling the AD9670 via a USB interface

EVALUATION KIT CONTENTS AD9670EBZ evaluation board 1 switching power supply (6.0 V, 2.5 A), CUI EPS060250UH-

PHP-SZ (provided)

EQUIPMENT NEEDED Analog signal source and antialiasing filter Linear benchtop dc voltage source (0 V to 1.6 V), not

required for CW Doppler mode PC running Microsoft Windows® 7 and Windows 10 operating

system USB 2.0 port, recommended (USB 1.1 compatible) HSC-ADC-EVALCZ FPGA-based data capture kit

1 switching power supply (6.0 V, 2.5 A), CUI EPS060250UH-PHP-SZ (provided with data capture kit)

Spectrum analyzer for CW Doppler mode

DOCUMENTS NEEDED AD9670 data sheet

SOFTWARE NEEDED VisualAnalog SPIController

GENERAL DESCRIPTION The AD9670EBZ evaluation board assists in evaluating all features of the AD9670 octal ultrasound analog front end (AFE) device. The AD9670 is low cost, low power, compact, and easy to use with medical ultrasound applications. The device provides eight voltage gain amplifier (VGA) channels, each with a low noise amplifier (LNA), a continuous wave (CW) harmonic rejection I/Q demodulator with programmable phase rotation, an antialiasing filter, an analog-to-digital converter (ADC), and a digital demodulator and decimator for both data processing and bandwidth reduction.

The evaluation board provides eight Subminiature Version A (SMA) connector inputs for all eight AD9670 channels. The evaluation board mates with a field-programmable gate array (FPGA) data capture board (HSC-ADC-EVALCZ) that enables data capture through a USB connection to a computer.

The SPIController software provides flexible configuration of the AD9670 and the VisualAnalog® software offers powerful data capture and signal analysis tools.

EVALUATION BOARD PHOTOGRAPH 17

260-

001

Figure 1.

http://www.analog.com/ad9670?doc=AD9670EBZ-UG-1459.pdf



http://www.analog.com/EVAL-HSC-ADC-EVALCZ?doc=AD9670EBZ-UG-1459.pdf


http://www.analog.com/en/design-center/interactive-design-tools/visualanalog.html?doc=AD9670EBZ-UG-1459.pdf

http://www.analog.com/en/design-center/interactive-design-tools/spicontroller.html?doc=AD9670EBZ-UG-1459.pdf








http://www.analog.com?doc=AD9670EBZ-UG-1459.pdf

https://www.analog.com/EVAL-AD9670?doc=AD9670EBZ-UG-1459.pdf

UG-1459 AD9670EBZ User Guide

Rev. 0 | Page 2 of 15

TABLE OF CONTENTS Features .............................................................................................. 1 Evaluation Kit Contents ................................................................... 1 Equipment Needed ........................................................................... 1 Documents Needed .......................................................................... 1 Software Needed ............................................................................... 1 General Description ......................................................................... 1 Evaluation Board Photograph ......................................................... 1 Revision History ............................................................................... 2

Evaluation Board Hardware .............................................................3 Power Supplies ...............................................................................3 Input Signals...................................................................................3 Output Signals ...............................................................................3

Evaluation Board Software ...............................................................4 Software Installation Procedures.................................................4

Evaluation Board Schematics and Artwork ...................................9

REVISION HISTORY 1/2019—Revision 0: Initial Version




EVALUATION BOARD HARDWARE POWER SUPPLIES A switching power supply (6.0 V, 2.5 A) powers up the AD9670EBZ board.

INPUT SIGNALS The AD9670EBZ board provides eight SMA connector inputs for the eight AFE channels. The SMA channel inputs directly connect to the AD9670 LNA input. An optional, external clock SMA input bypasses the default on-board 40 MHz crystal by changing the J301 jumper. Figure 1 shows an image of all inputs.

Other SMA inputs include the VGA VGAIN control, the CW Doppler MLO±, RESET±, and an optional TX_TRIG± input. The VGAIN single-ended signal is the default but a differential input configuration is also possible. The FPGA provides the TX_TRIG± signal on the HSC-ADC-EVALCZ data capture board.

OUTPUT SIGNALS The data capture board receives low voltage differential signaling (LVDS) digital output signals from the AD9670EBZ board through the on-board connectors (P401 and P402) (see Figure 1). The J501 jumper and J502 jumper SMA outputs are the CW Doppler summed in-phase quadrature (I/Q) outputs.






EVALUATION BOARD SOFTWARE SOFTWARE INSTALLATION PROCEDURES To install the VisualAnalog and SPIController software packages, and configure and test the AD9670, take the following steps:

1. Install the VisualAnalog software. 2. Install the SPIController software. 3. Plug the 6 V adapters into the AD9670EBZ evaluation

board and the data capture board to power them up. Connect the data capture board to the PC with the USB cable that is provided with the data capture board.

4. Launch the SPIController software to open the window shown in Figure 2 and select the AD9670.cfg file from the dropdown list (under File > Cfg Open Menu). After the Open File dialog appears, browse for and select the AD9670_14bit_ 125MSspiR03.cfg file. The chip ID reads AD9670 (see Figure 2) after loading the AD9670.cfg file.

CHIP READS AD9670

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Figure 2. SPIController Main Window

5. From the Config menu, click Launch Memory Map Dialog to open the Memory Map window, as shown in Figure 3. Click the Load File button to open the AD9670_14bit_125MSspiR03.mmp file, which loads the coefficient and profile memory data into the AD9670.

READS THE MEMORYON THE DEVICE

AND SAVES IT TO A FILE

UPDATINGPROFILE NUMBER

SELECTS A NEWDECIMATION RATEAND COEFFICIENT

POINTER

DEMODULATION FREQUENCYCAN BE CHANGED BY

UPDATING DEMODAND SAMPLE FREQUENCY

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Figure 3. Memory Map Window

6. In the main SPIController window, open the File menu and click Open Macrogroup. Select the AD9670_ Initialization.mgp macro file to open the MacroEditor window shown in Figure 4. The macro file is an .XML file that lists the serial peripheral interface (SPI) command macros in the D6970_Initializaion_v2.mg dropdown box (see Figure 4). Each command macro includes SPI writes that configure the AD9670 for specific operating modes. The MacroEditor conducts a batch write of SPI registers to set up the AD9670. The macro file contains the following two macros: Real Mode, 40Msps and IQ Mode, 40Msps. It is possible to add unique configuration macros to the .XML macro file and load the macros into the MacroEditor window.















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Figure 4. MacroEditor Window and D6970_Initializaion_v2.mg Dropdown

Box

Table 1. Procedural List of SPI Commands Configuring the AD9670 Register Function 0x000 SPI reset. 0x002 Set speed mode. 0x004, 0x005 Set local registers to all channels. 0x011 Set LNA, VGA, and PGA gain. 0x10C Set SPI TX_TRIG± and Index Profile 1. 0x113 Enable/bypass digital filters,

demodulator, and decimator. 0x00F Set low-pass filter cutoff frequency and

mode. 0x021 16-bit, 8-lane, frame clock output (FCO)

covers entire frame. 0x008 Time gain compensation (TGC) run

mode. 0x182 Autoconfigure phase-locked loop (PLL). 0x199 Autoset FCO and data clock output

(DCO). 0x02B Set analog low-pass filter and high-pass

filter to defaults and tunes filters. 0x014 Set output data format. 0x188 Enable start code. 0x10C Set SPI TX_TRIG± and Index Profile 1. 0x19B Serial format.

7. Select either the Real Mode or the IQ Mode macro from the dropdown box (see Figure 5) and select the Enable checkbox. To run the selected macro, click the Run button to conduct a write operation (see Figure 5).

RUN BUTTON

SELECT MODE

ENABLE TAB

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Figure 5. Select, Enable, and Run Commands in MacroEditor

8. Launch the VisualAnalog software to use the canvas templates listed in the AD9670 directory in the Categories pane (see Figure 6). The Samples canvas shows time domain output samples vs. sample count.

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Figure 6. VisualAnalog Canvas Selection Window








9. If the VisualAnalog software opens and only shows the task bar, as shown in Figure 7, click the down arrow on the right side of the window to expand the AD9670 Samples canvas (shown in Figure 8) to see the signal processing flow.

10. Next, load the FPGA binary file into the hardware. To load the file, click the Settings button in the ADC Data Capture block (see Figure 8).

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Figure 7. VisualAnalog in Window Collapse Mode

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SETTINGS

Figure 8. VisualAnalog Sample Canvas







11. When the ADC Data Capture Settings window opens, click the Capture Board tab and then click the Browse… button. Select the ad9670_lvds_mar2012.bin file and click Program, which illuminates the Done LED D6 indicator on the HSC-ADC-EVALCZ board. Click OK to close the window.

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Figure 9. ADC Data Capture Settings Window

12. The AD9670 is now running and fully configured for data capture mode. The VisualAnalog software offers two data capture modes: onetime and infinite loop. Click the blue right arrow (see Figure 7 or Figure 8) to run the canvas in onetime mode and click the green repeat button (see Figure 7 or Figure 8) to run the canvas in infinite loop mode. The Samples canvas then opens two windows showing 8192 time domain samples for Channel A and Channel B (see Figure 10 for the Channel A window).

BUTTONS FOR ZOOMING INAND RESIZING

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Figure 10. Data Capture Window

13. Another loadable canvas, the AD9670_Average_FFT.vac canvas, runs average fast Fourier transform (FFT) calculations of the captured samples. The average count is set to five captures. Therefore, either run the canvas five times to display the first FFT output or leave it in continuous run mode to keep the canvas functioning.

14. Figure 11 shows both the FFT output and how the analog and digital high-pass filters shape the noise floor in the low frequency region.

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Figure 11. Average FFT Canvas







15. To disable the digital high-pass filter, select the HP Filter Bypass checkbox in the Memory Map window (see Figure 12) and then click the Manual Tx Trigger button (see Figure 12).

ENABLE THE HIGH-PASS DIGITAL BYPASS

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Figure 12. Disabling the Digital High-Pass Filter Bypass in the Memory Map

Window

16. Disabling the digital high-pass filter increases the noise floor shape at low frequencies and results in a flat noise floor (see Figure 13).

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Figure 13. Average FFT Canvas with the Digital High-Pass Filter Disabled

17. To enable the demodulator and decimator, select and run the IQ Mode, 40Msps macro in the MacroEditor window (see Figure 4).




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TS

OP

TIO

NA

L C

LOC

K C

IRC

UIT

S &

CW

RE

FER

EN

CE

DE

CO

UP

LIN

G C

AP

AC

ITO

RS

OFFO

NA

D95

16

CLO

CK

OS

CIL

LATO

R

1TP

304

1TP

303

1TP

302

1TP

301

C31

7C

316

R32

5

R33

3R

331

R33

0R

329

1 4

6 57 8

32

U30

2

54

32

1J3

07

R327

R33

25

43

2

1J3

06

R326

R32

8

R34

0

R33

8

R33

9

R33

7

R32

4

10987654321J304

R31

3

R31

5

R31

4R

312

C32

9C

328

C32

7C

323

C32

4C

325

C32

6

C31

4

C31

5

R32

2

R32

3

12

3D

302

C31

3

T302

R321

54

32

1J305

C30

7

C30

8

C30

9

C31

0

C33

2

C31

2

C33

3

R34

1

R31

8

R32

0R

319

R33

5

R30

7

12

3D

301

R30

8

C30

6

R30

5

64 2

3

1T3

01

R30

6

C30

4

C30

5

R30

45

43

2

1J3

03

C30

2

R30

35

43

2

1J3

02

C30

1R

301

C30

3

R31

6

R31

7

C31

1

C33

1C

330

544127

6160575150493832313012111

4

8

6 21

2216 5823

2

63647 24

PAD

36344547292639425255 353346482825404353569

3594437

17 62

5

141310

U30

1

R33

4

R33

6

C32

2C

321

C32

0C

319

4

13

2

OS

C30

1

3 2 1

J301

R30

2

R311

R310

R309

C31

8

0.1U

F

0.1U

F0.

1UF

0.1U

F

AD

N46

63B

RZ

AD

T1-1

WT+

MM

BD

4148

SE

MM

BD

4148

SE

5001

5001

5001

5001

DN

I

TSW

-105

-08-

G-D

200

4.12

K

100

100

100

100

DN

I

200

200

10K

10K

10K

10K

49.9 49.9 49.9

49.9

5.1K

0

00

0

0

0

00

00

0

0

00

0

0

0 0

0 0

0

0 0

DN

I

DN

I

DN

I

DN

I

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F0.

1UF

0.1U

F0.

1UF

0.1U

F

0.1U

F0.

1UF

0.1U

F0.

1UF

0.1U

F

0.1U

F0.

1UF

0.1U

F

DN

I

DN

I

DN

I

DN

I

10U

F

0.02

2UF

3900

PF

.22U

F

CP

AV

DD

_3P

3V

CLK

_LV

DS

_P

CLK

_LV

DS

_N

CLK

_LV

PE

CL_

P

CLK

_LV

PE

CL_

NLF

TX_T

RIG

OP

T_C

LKN

AD

9516

-0B

CP

Z

CLK

_LV

DS

_PC

LK_L

VD

S_N

CW

AD

C_C

LK

AD

9516

_CS

B

AD

9516

_RE

SE

T

BY

PA

SS

_LD

O

AD

T1-1

WT+

AV

DD

_3P

3V

AV

DD

_3P

3V

SY

NC

B

CLK

_LV

PE

CL_

NC

LK_L

VP

EC

L_P

SY

NC

B

SD

I

RE

F_S

EL

LF

CLK

_N

RS

T_P

OP

T_C

LKP

MLO

_NE

G

MLO

_PO

S

CLK

_P

STA

TUS

BY

PA

SS

_LD

O

AV

DD

_3P

3V

AV

DD

_3P

3V

OP

T_C

LKN

AV

DD

_3P

3V

RE

F_S

EL

PD

B

OP

T_C

LKP

CLK

_N

CLK

_P

CP

SD

O

PD

B

SC

LK

TX_T

RIG

_N

RS

T_N

TX_T

RIG

_P

10K

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

PA

DG

ND

RE

FIN

(RE

F2)

RE

FIN

(RE

F1)

SD

IOS

CLK

CLK

CLK

LF

VS

_LV

PE

CL

CP

RS

ET

RS

ET

PD

RE

SE

T

CS

BY

PA

SS

SY

NC

RE

F_S

EL

VC

P

OU

T9

OU

T8

OU

T7

OU

T6

OU

T5

OU

T4

OU

T3

OU

T2

OU

T1

OU

T0

OU

T9

OU

T8

OU

T7

OU

T6

OU

T5

OU

T4

OU

T3

OU

T2

OU

T1

OU

T0

SD

OS

TATU

SC

PLDR

EFM

ON

VS

VC

C

DO

UT2

_NE

GD

OU

T2_P

OS

DO

UT1

_NE

GD

OU

T1_P

OS

GN

D

DIN

2

DIN

1

GN

DG

ND

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

VC

CTR

ISTA

TE C

TRL

GN

DO

UT

17260-017





GA

IN R

EF

SP

I CIR

CU

ITR

YD

IGIT

AL

OU

TPU

TS A

ND

SP

I TO

FIF

O5

SE

DR

IVE

GA

IN D

RIV

E O

PTI

ON

S

GA

IN-

PO

T D

IVID

ER

DIF

F D

RIV

E

PLA

CE

ME

NT

SP

AC

ING

TO

MA

TCH

AD

C E

VA

L B

RD

S F

OR

MA

TIN

G W

ITH

FIF

O5

GA

IN+

C40

3

R42

1 1TP

403

R42

3

1TP

401

1TP

402

R41

5

R40

85

43

2

1J4

03

C41

2C

411

C41

0C

409

C40

8R

422

R42

5

R42

4

62

581

73 4

U40

4

R41

8

C40

6

C40

5

R41

9

R42

0

C40

7

C40

4

R41

7

R41

6

48U

403

756

U40

3

132

U40

3

54

32

1J4

02

R40

7

R409R410

32

1

R41

1

B10B

9B

8B

7B

6B

5B

4B

3B

2B

1

P40

2

D10D

9D

8D

7D

6D

5D

4D

3D

2D

1

DG

10D

G9

DG

8D

G7

DG

6D

G5

DG

4D

G3

DG

2D

G1

A10A

9A

8A

7A

6A

5A

4A

3A

2A

1

P40

2

C10C

9C

8C

7C

6C

5C

4C

3C

2C

1

P40

1

A10A

9A

8A

7A

6A

5A

4A

3A

2A

1

P40

1

R42

7R

426

C10C

9C

8C

7C

6C

5C

4C

3C

2C

1

BG

10B

G9

BG

8B

G7

BG

6B

G5

BG

4B

G3

BG

2B

G1

D10D

9D

8D

7D

6D

5D

4D

3D

2D

1

P40

1

DG

10D

G9

DG

8D

G7

DG

6D

G5

DG

4D

G3

DG

2D

G1

P40

1B

10B9

B8

B7

B6

B5

B4

B3

B2

B1

P40

1

BG

10B

G9

BG

8B

G7

BG

6B

G5

BG

4B

G3

BG

2B

G1

P40

1

R42

9R

428

R43

0R

431

R43

2R

433

R43

4R

435

R40

6

R40

4 R40

5

C40

1

46

5 2

31

U40

1

C40

2

46

5 2

31

U40

2

R40

1

R40

3R

402

10 9 8 7 6 5 4 3 2 1

J401

22U

FD

NI

22U

F

22U

F

NC

7WZ1

6P6X

NC

7WZ0

7P6X

AD

R43

4AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

6469

169-

164

6916

9-1

5001

5001

5001

TSW

-105

-08-

G-D

10K

4.12

K

8.66

K

221

221

82K

1K

10

1K

1K

1K

100

100

100

100

100

100

100

100

100

100

100

DN

I

DN

ID

NI

DN

I

DN

I

DN

ID

NI

DN

ID

NI

DN

I

10K

10K

10K

49.9

49.9

24

24

24

24

DN

I

DN

I0 D

NI

1000

PF

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.00

1UF

SC

LK_D

UT

AV

DD

_DU

TA

D95

16_C

SB

AV

DD

_3P

3V

AV

DD

_DU

T

FCO

_P

TX_T

RIG

SD

O_P

RC

Q

SD

O_C

HA

SD

I_C

HA

CS

B1_

CH

AC

HD

_P

FCO

_N

CH

C_P

SD

O_P

RC

IC

NV

_PR

CI

SC

K_P

RC

I

CS

B2_

CH

A

GA

IN_P

AD

9516

_RE

SE

T

CN

V_P

RC

Q

SC

K_P

RC

Q

CH

C_N

CH

B_N

CH

A_N

DC

O_N

CH

F_N

CH

G_N

CH

D_N

CH

H_N

CH

A_P

CH

B_P

CH

F_P

CH

G_P

CH

H_P

SC

LK_C

HA

CH

E_P

SD

IO_D

UT C

SB

_DU

T

AV

DD

_DU

T

SC

LKS

CLK

_CH

AS

DI

SD

I_C

HA

SD

OS

DO

_CH

A

P5V

_AV

DD

0.8V

_RE

F

4.09

6_G

AIN

_RE

F

P5V

_AV

DD

N5V

_AV

DD

CS

B1_

CH

A

CS

B2_

CH

A

4.09

6_G

AIN

_RE

F

AV

DD

2_D

UT

GA

IN_N

0.8V

_RE

F

CH

E_N

DC

O_P

GN

D

GN

D

GN

D

GN

D

GN

D

TRIM

VIN

GN

DN

IC

DN

CC

OM

PD

NC

VO

UT

GN

D

GN

D

V–

V+

GN

D

GN

D

PLUG HEADER PLUG HEADER PLUG HEADER

GN

D

PLUG HEADER

PLUG HEADER

PLUG HEADER

PLUG HEADER PLUG HEADER


GN

DG

ND


GN

D

GN

D

GN

D

VC

C

Y1

A1

A2

GN

D

Y2

GN

D

GN

D

Y2

Y1

A2

A1

GN

D

VC

C

GN

D

GN

D

17260-018





QO

UT

CW

OU

TPU

T C

IRC

UIT

RY

AN

ALO

G IO

UT

NO

TE: L

409-

L414

AR

EP

OP

ULA

TED

WIT

H 0

OH

M.

AN

ALO

G

NO

TE: L

403-

L408

AR

E P

OP

ULA

TED

WIT

H 0

OH

M

R54

7

R53

1

R52

8

R52

9R50

3

R50

4

C54

4C

543

R50

5

C52

4

R52

1

62

581

73 4

U50

6

R53

0

C52

8

C52

7R52

7

R53

3C

431

R53

2

C55

6

R52

6

C52

9

75 6

U50

3132

U50

3

U50

1U

502

U50

3U

504

C50

3

C50

2R50

2R50

8C

505

R50

7

C50

1

R50

1

132

U50

1

R50

6

C50

4

756

U50

1

C55

5C

554

C54

8

C52

1

C55

3

C54

7

C52

0

2 1

L507

C51

9

102

79 8 13 4

5

6

U50

5

1IP

2

1IN

2

C52

6C

525

C51

8C

517

R52

0

C51

5

L505

C51

6

L506 C

523

C52

2R

523

R52

4C

552

C54

6

2 1

L514

C54

5

C55

1C

550

1

QP

2

102

79 8 13 4

5

6

U50

7

1

QN

2

C54

9

C54

2

R54

6

C54

1

C53

9

L512

C54

0

L513

R517

C50

9

R51

3

R50

9C

506

1IP

1

132

U50

2

C51

3

L503

C51

1

C51

4

L504

C51

2

54

32

1J5

01

L501

R51

8

L502

R51

9

R52

2

R52

5

54

32

1J5

02R

545

R51

5

R51

6

75 6

U50

2

C50

8

R51

0

R51

2R

511

C51

0

R51

4 C53

3

R53

9

C53

7

L510

C53

8

L511

C53

5

R54

3 L508

C53

6

L509

R54

4

132

U50

4

R54

1

R54

2

R53

4C

530

1Q

P1

R53

6

C53

2R

538

R53

7

R54

0

75 6

U50

4

C53

4

R53

5C

531

1

QN

1

C50

7

1

IN1

22U

F

22U

F

50OHMS

50OHMS

AD

R43

4AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

A48

96-2

AR

MZ

AD

7982

BR

MZ

AD

7982

BR

MZ

WH

TWH

T

WH

T

WH

T

WH

T

WH

T

WH

T

WH

T

0

0

00

0

0

0

0

00

0

0

1.91

K

1.91

K1.91

K

1.91

K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K 1K

1KDN

I

DN

I

DN

I

DN

I

20

20

20

20 DN

I

DN

I

DN

I

DN

I

82K

20K

20K

20K

20K

100 10

0D

NI

DN

I

10K

10K

10K

10K

DN

I

DN

I

49.9

49.9

0

0 0

0 0

0

0

0

0

0

0

0 0

0

DN

I

DN

I

150p

F

150p

F

150p

F

150p

F

150p

F

150p

F

1200

pF

1200

pF

1200

pF

1200

pF

2.2U

F

2.2U

F2.2U

F

2.2U

F

1000

0pF

3300

pF

3300

pF

3300

pF

3300

pFD

NI

DN

I

DN

IDN

I

0.1U

F

0.1U

F

0.1U

F0.

1UF

0.1U

F

0.1U

F0.

1UF

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F0.

1UF

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F0.

1UF

0.1U

F

0.1U

F

0.1U

F

0.1U

F

DN

I

DN

I

DN

I

DN

I

DN

I

DN

ID

NI

DN

I

DN

ID

NI

DN

I

DN

I

10U

F

10U

F

10U

F

2700

pF27

00pF

2700

pF27

00pF

CN

V_P

RC

I

CN

V_P

RC

Q

CW

Q_P

OS

CW

I_N

EG

CW

I_P

OS

CW

Q_N

EG

AV

DD

2_D

UT

AV

DD

2_D

UT

P5V

_AV

DD

PR

CI N5V

_AV

DD

P5V

_AV

DD

SD

O_P

RC

Q

SD

O_P

RC

I N5V

_AV

DD

2P5V

_PR

C

2P5V

_PR

C

PR

CI

PR

CQ

VR

EF_

CW

SC

K_P

RC

Q

SC

K_P

RC

I

PR

CQ

VR

EF_

CW

P5V

_AV

DD

VR

EF_

CW

CW

AD

C_C

LK

VR

EF_

CW

GN

D

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

D

TRIM

VIN

GN

DN

IC

DN

CC

OM

PD

NC

VO

UT

GN

DGN

DG

ND

GN

D

V–

V+

V–

V+

V–

V+

V–

V+

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

VIO

VD

D

RE

F

SD

O

GN

D

CN

VS

CK

SD

IIN

_NE

GIN

_PO

S

GN

D

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

VIO

VD

D

RE

F

SD

O

GN

D

CN

VS

CK

SD

IIN

–IN

+

GN

D

GN

DG

ND

17260-019





RL1

220T

-R04

7

OP

TIO

NA

L C

LNA

CO

NN

EC

TIO

NS

PO

WE

R S

UP

PLY

OP

TIO

N F

OR

HIG

H Z

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17260-020





NOTES

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG17260-0-1/19(0)

https://www.analog.com?doc=AD9670EBZ-UG-1459.pdf
