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AD7768-1 EVALUATION BOARD SCHEMATIC
1 15
<User Define><User Define><User Define>
: Pitch-pitch StyleVendor StylePACKAGE : N/A-lead N/A N/A-family
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
no_template
ECodeID1:1
02_044287TBD
-
-
-
-
-
<PTD_ENGINEER>
-
-
-
-
REV
2REVISIONS
1
OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. JP#USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER
8
CONNECTORFUNCTIONCODE DEVICE
2
2
6JUMPER TABLE
4
7
5
A
3
DATE APPROVED
D
B
DESCRIPTION
34
OFFON
5
57
OEM PART# HANDLER
6
C
B
8
SOCKET OEMBK/BD SPEC.P.O SPEC.
A
1
RELAY CONTROL CHART
3 14
C
NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS
CHECKER
DESIGNER
PTD ENGINEER
TEST ENGINEER
DECIMALS
X.XXX +-0.005X.XX +-0.010
MASTER PROJECT TEMPLATE
TOLERANCES
+-1/32FRACTIONS
+-2SIZE
DDDD
SCHEMATIC
DRAWING NO.
SCALE CODE ID NO.
SHEET OF
REV.
DA A
ENV C
L GSE
ODATE
ANGLES
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES
TESTER TEMPLATE
TEMPLATE ENGINEER
HARDWARE SERVICES
HARDWARE SYSTEMS
COMPONENT ENGINEER
TEST PROCESS
HARDWARE RELEASE
* SEE ASSEMBLY INSTRUCTIONS
CONTROL
D
AIN BLOCK: DRIVER AMP AND VCM BUFF OPT
KEEP ALL DECOUPLING
REF BLOCK: REF CHIP AND BUFFER OPT
RESET ADCS
TAKE FROM SDP-H CONNECTIONS
TO AMPLIFIER MODE SELECTION
OR PIN MODE SWITCH
NOTE: ROUTE REF+ AND REF- AS A DIFFERENTIAL PAIR
POWER BLOCK: ALL LDOS AND CONNECTORS
MAIN CONNECTIONS
AND 0.1UF CLOSESTCLOSE TO ADC PINS
KEEP ALL DECOUPLINGCLOSE TO ADC PINSAND 0.1UF CLOSEST
CLOSE TO ADC PINSAND 0.1UF CLOSEST
KEEP ALL DECOUPLING
LVDS TERMINATION
2 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
BLK
DNI
BLK
DNI
BLK
DNI
BLK
DNI
BLK
DNI
C060
3
DNI
TBD0603
TBD0603
0
TBD0603
DNI
DNI
DNI
TBD0603
0
1UF
DNI
0.1U
F
PTS830 GM140 SMTR LFS10
K
0
TBD0603
DNI
0.1U
F
0
50
0.1U
F
0.1U
F
0.1UF
DNI0
10UF
0.1UF
1UF
1UF
0.1UF
0.1U
F
C060
3
1UF
C121
0
DNI
TBD1
206
1UF
DNI
TBD0
603
0
AD7768-1BCPZ
TBD0
603
R1
R64
R144
R149
R143
R3/RESET C1
R4
R5
RST_1
R6
C2 C4
U2
C7
C6
C11
DEC_1
FILT_1
MDE1_1
R13
R12
R11
MDE0_1R10
R8
C14
C16
C18
C20
C26
C23
C22
C28
R18
C10
GPIO0_OUTPUT
VCM_ADC1
AVDD1
GNDIOVDD
CARRIER_POWER_GOOD+12V_FMC
GPIO2_1
MODE1_PIN_1
GPIO0_1
GPIO0_OUTPUT
AVDD2AVSS
+7V_SUPPLY
RESET_1 DEC_PIN_1
GPIO3_1
MODE0_PIN_1
GPIO1_1
AVDD2
FILT_PIN_1
GND
VCM_ADC1
AVSS
IOVDD
GND
AVSSGND
AVSS
RESET_ADC1
IOVDD
SYNC_IN_ADC1 SYNC_OUT_ADC1
PIN_SPI_ADC1
GND
CLK_SEL_ADC1
DOUT_ADC1CS_ADC1
XTAL1_ADC1MCLK_ADC1
DRDY_ADC1
AVSS
AVDD1
SCLK_ADC1SDI_ADC1
AVSS
4321
1
1
1
1
1
AIN_BLOCK_CH2
+7V_SUPPLYAVDD1AVSSGNDIOVDDVCM
AMP2_AOUT+AMP2_AOUT-
GPIO0_OUTPUT
POWER_ALL
CARRIER_POWER_GOOD+12V_FMC
AVDD1AVDD2
AVSSGND
IOVDD+7V_SUPPLY
REFERENCE_BLOCK
+7V_SUPPLYAVSS
+VREF
PAD
VCM
AIN+AIN-
REF-REF+
AVDD1 AVDD2
AVSS
REGCAPA
DRDY_N
GPIO3/DEC_CTRLGPIO2/FILTER
GPIO1/PWR1GPIO0/PWR0
MCLK/XTAL2XTAL1
CS_NSDISCLK
DOUT/RDY_N
CLK_SEL
DGNDPIN_N/SPI
IOVDD
REGCAPD
SYNCOUT_NSYNCIN_N
RESET_N
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
EEPROM
H1 (VREF_A_M2C)
SHOULD BE USED BEFORE THE _N LINE OF THE SAMESINGLE-ENDED SIGNALING IS USED, THE _P LINEMOVING UP THE LA BUS UNTIL IT IS FULL. WHENPINS MUST BE ASSIGNED STARTING WITH LA00 AND
BOARD PRESENT PIN (H2) MUSTALWAYS BE TIED TO GROUND
NO CONNECT
PAIR IS USED.
12P0V. 1A MAX CURRENT LIMIT3P3V. 3A MAX CURRENT LIMITVADJ. 2A MAX CURRENT LIMIT. 1.2V TO 3.3V.
POWER SUPPLIES:
FPGA FMC CONNECTIONS
NO CONNECTNO CONNECT
NO CONNECTNO CONNECT
NO CONNECTNO CONNECT
ARE NOT CONNECTED ON THE SDP-H1:LIST OF FMC-LPC CONNECTOR PINS THAT
D5 (GBTCLK0_M2C_N)
C3 (DP0_C2M_N)
C7 (DP0_M2C_N)
C2 (DP0_C2M_P)
C6 (DP0_M2C_P)
D4 (GBTCLK0_M2C_P)
BE SHORTED TOGETHER (AS SHOWN) SO AS NOT TO BREAK JTAG CHAIN
I2C ADDRESS SET BY CONTROLLER BOARD.I2C LINE PULL-UP RESISTORS ON FPGA BOARD.EEPROM REQUIRED IN VITA57.1 STANDARD.
NOT USED
IF EVAL BOARD DOES NOT USE JTAG TDI AND TDO THEN THEY MUST
3 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
ASP-134604-01M24C02-RMN6TP
ASP-134604-01ASP-134604-01ASP-134604-01
U1
P1 P1 P1 P1
GPIO3_1
SYNC_OUT_1
DOUT_1
SDI_1
GPIO0_1
RESET_1GPIO1_1
DRDY_1
SCLK_1
GND
GA1GA0
3P3VAUX
+12V_FMC
GND
GA0
GPIO2_1
SYNC_IN_1
GND
CARRIER_POWER_GOOD
3P3VAUX
GA1
MCLK_1
VADJ
GND
CS_1
MCLK_RETURN
VADJ
GND
GND
7
4
8
5
6321
C31C30
C26C27
C22C23
C18C19
C14C15
C10C11
C40
C38
C36
C33C32
C29C28
C25C24
C21C20
C17C16
C13C12
C9C8
C5C4
C1
C34
C6C7
C2C3
C37
C35
C39
D34D33
D31D30D29
D1
D26D27
D23D24
D20D21
D17D18
D14D15
D11D12
D8D9
D39
D37
D28
D25
D22
D19
D16
D13
D10
D7D6
D3D2
D4D5
D35
D32
D40
D38
D36
G39
G36G37
G33G34
G30G31
G27G28
G24G25
G21G22
G18G19
G15G16
G12G13
G9G10
G6G7
G40
G38
G35
G32
G29
G26
G23
G20
G17
G14
G11
G8
G5G4
G1G2G3
H1
H40
H2
H37H38
H34H35
H31H32
H28H29
H25H26
H22H23
H19H20
H16H17
H13H14
H10H11
H7H8
H39
H36
H33
H30
H27
H24
H21
H18
H15
H12
H9
H6
H3H4H5
VSS
SCL
SDA
WC_N
E2E1E0
VCC
GND3P3VGND12P0VGND12P0VGA0GNDGNDSDASCLGNDGNDLA27_NLA27_PGNDGNDLA18_N_CCLA18_P_CCGNDGNDLA14_NLA14_PGNDGNDLA10_NLA10_PGNDGNDLA06_NLA06_PGNDGNDDP0_M2C_NDP0_M2C_PGNDGNDDP0_C2M_NDP0_C2M_PGND
3P3VGND3P3VGND3P3VGA1TRST_LTMS3P3VAUXTDOTDITCKGNDLA26_NLA26_PGNDLA23_NLA23_PGNDLA17_N_CCLA17_P_CCGNDLA13_NLA13_PGNDLA09_NLA09_PGNDLA05_NLA05_PGNDLA01_N_CCLA01_P_CCGNDGNDGBTCLK0_M2C_NGBTCLK0_M2C_PGNDGNDPG_C2M
GNDVADJGNDLA33_NLA33_PGNDLA31_NLA31_PGNDLA29_NLA29_PGNDLA25_NLA25_PGNDLA22_NLA22_PGNDLA20_NLA20_PGNDLA16_NLA16_PGNDLA12_NLA12_PGNDLA08_NLA08_PGNDLA03_NLA03_PGNDLA00_N_CCLA00_P_CCGNDGNDCLK1_M2C_NCLK1_M2C_PGND
VADJGNDLA32_NLA32_PGNDLA30_NLA30_PGNDLA28_NLA28_PGNDLA24_NLA24_PGNDLA21_NLA21_PGNDLA19_NLA19_PGNDLA15_NLA15_PGNDLA11_NLA11_PGNDLA07_NLA07_PGNDLA04_NLA04_PGNDLA02_NLA02_PGNDCLK0_M2C_NCLK0_M2C_PGNDPRSNT_M2C_LVREF_A_M2C
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
MCLK SELECTION
NOTE: TREAT MCLK AND XTAL1 TRACES ASA DIFFERENTIAL PAIR. KEEP TRACE LENGTHS
FOR SCOPE PROBESKEEP TP CLOSE TO SDP-H1
OVERSHOOT/ TERMINATION
XTAL1 TO GND IF CLK_SEL 0
DATA INTERFACE
PIN MODE OPTIONS
PIN MODE SWITCH
SELECT PIN MODE OR SPI
ADC DIGITAL CONNECTIONS
SYNC IN/OUT
NOTE: REMOVE GND FROM UNDER XTAL
TO USE THIS AS EXTERNAL CLKDISCONNECT OTHER OPTIONS
THE SAME
CAP SPACE FOR CLOCK
4 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
DNI
0
5015BLK
0
0
DNITBD0603
BLK
DNI
5015
DNITBD0603
DNI
DNI
BLK
0
BLK
1-1337482-0
16.384MEGHZ
0
DNI
20PF
DNI
1-1337482-0
TBD0603
BLK
DNI
BLK
BLK
DNI
BLK
DNI
BLK
DNI
BLK
DNI
20PF
TBD0603DNI
TBD0603DNI
TBD0603
TBD0603DNI
0
DNITBD0603
0DNI
DNI
TBD0603
0
10K
10K
10K
10K
DNI
DNITBD0603
0
219-4MST
TBD0603
0
BLK
DNI
GND1
GND2
MCLK1A
C3
C13
C5
C8
S_OUT1
S_IN1
R25
R30
R29
SDI_1R22
SCLK_1
R21
CSEL_1
CSEL1B
CSEL1A
R27
MCLK_1
CS_1
DRDY_1
DOUT_1
R35
R34
R33
MCLK1C
J1
C30
Y1
C31
R36
J2XTLG
ND
XTL1_1
R20
R26
R31
R32
PMODE1
SPI1_B
/PIN_1
SPI1_A
MCLK_1
SCLK_1SCLK_ADC1
GND
GND
SDI_1SDI_ADC1
GND
DOUT_ADC1DOUT_1
XTAL1_ADC1
CS_1CS_ADC1
MCLK_ADC1
SYNC_IN_ADC1
GND
GND
CLK_SEL_ADC1
IOVDD
MCLK_RETURN
PIN_SPI_ADC1
IOVDD
MODE1_PIN_1
GND
FILT_PIN_1DEC_PIN_1
GND
IOVDD
MODE0_PIN_1
SYNC_IN_1
SYNC_OUT_1SYNC_OUT_ADC1
GND
DRDY_1DRDY_ADC1
1
1
1
1
1
1
1
1
1
1
1
5 4 3 2
1
31
42
5432
1
1
1B2B3B4B 4A
3A2A1A
1
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
FURTHER DECOUPLING AT THE PINS
REFERENCE BLOCK - ALL
TPS ON SUB-BLOCKSADA4807-2 - OTHER HALF USED FOR VCM
KEEP CLOSE TO ADC TO REDUCE ERROR
5 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
0
DNI
DNI
0
0
4.7U
F
0RBUF_B
RBUF_A
C15
R2
RBUF_CAVSS
AVSS
+VREF
AVSS
+7V_SUPPLY
NP
OUT
IN
IN
REF_4P096V_ADR4450B+7V_SUPPLYAVSS
4P096VREF
REF_BUFFER_ADA4807
BUFFERED_VREF
VREF_IN
AVSS+7V_SUPPLY
REF_RCOUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
ADA4807 - REF BUFFER
POSSIBLETO DEVICE ASPLACE 0.1UF AS CLOSE
CLEAR GND/PWR PLANES
BENATH IN/OUT PINS
REF/VCM BUFF SUPPLIES
6 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
1N4148W-7-F
1N4148W-7-F1001K
BLK
100U
F 10UF
10UF
DNI
ADA4807-2ARMZ
100
ADA4807-2ARMZ
0 1.1K
100UF
3.3
0.1U
F
10K
100U
F
D3
D4
R85
C74
C75
R88
R87R84
R86
C71
R83
R82
C70
C72
REFB1
C73
A1
A1
VREF_IN
AVSS
BUFFERED_VREF
REF_RCOUT
REF_RCOUT
AVSS
+7V_SUPPLY
A
C A
C
NP
NP
NP
NP
NP
1
4
8
13
2
OUT
IN
IN
IN
VS+
VS-
IN
OUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
KEEP CLOSE TO ADC TO REDUCE ERROR
TRACK DIFFERENTIAL REF INPUT FROM HERE
4.096V REFERENCE
TEST POINTDO NOT CONNECT
7 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
BLK
BLK
0.1U
F
1UF
TBD0
603
0.1U
F
DNI
DNIADR4540BRZ
AVSS9
C17
C19
U4
C21
C24
VREF
4P096VREF+7V_SUPPLY
AVSS 1
628
75314
1
IN
IN
NCNCNCNC
VIN
GND TP
VOUT OUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
DISTRBUTE ON BOARD
NOTE: DISTRBUTE THROUGHOUT THE BOARD
PLANE TOGETHERSTITCHES AVSS AND GND
5V LDO
-2V5 LDO
RESISTOR OPTIONS
3V3 LDO
POWER - ALL
AVSS
LDOS
7V LDO
AVSS GROUNDED BY DEFAULT
ONE STAR POINT GND HERE
INDIVIDUAL SUPPLY - SET EXTERNALLY
AVDD2
IOVDD
AVDD1
NOTE: DISABLED BY DEFAULT
LABEL:+V, GND AND -VLABEL A, C
LABEL WITH A, B
IOVDD OFF SDP-H
LABEL A, C
OPTION TO ALWAYS POWER
INPUT VOLTAGE OPTIONS
8 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
22-0
3-20
31 DNI
10UF
NSR0240HT1G
0
DNI
DNI
0.1U
F
10UF
BLK
BLK0
0
0
BLK
DNI
BLK
10UF
0.1U
F
0
0
DNI
BLK
0
CTB932HE/5
DNI
DNI
BLK
CTB932HE/5
TBD0603
0
0
BLK
TBD0603
TBD0603DNI
DNITBD0603
0
TBD0603BLK
10UF
0
BLK
0
TBD0603
BLK
BLK
DNI
0
BLK
DNI
BLK
0
0
0
DNI
DNI
BLK
0.1U
F
10UF
BLK
DNI
BLK
DNI
BLK
DNI
0
0
0
0
DNI
DNI
BLKDNI
DNI
10UF
0.1U
F
DNI
0
0BLK BLK
0
DNI
DNI
NSR0240HT1G
0
D1
+VIN
VINSEL
GND5
C44
P5
P6
R53
R57
R52
PGOOD
5VD
DGND
3V3
5VA
AVSS1
2V5
1V8
-15V
+15V
R44
R42
R49
R50
R48
R47
R51
R46
R45
R43
AVSSG6
AVSSG5
AVSSG4
D2
AVSSG3
AVSSG2
AVSSG1
AMPV_B
AMPV_A
C45
C54
C53
C52
C51
C48
C50
C49
C47
GND7
-VIN
AMPPWR
GND6
AVSS
AVDD2
AVDD1
IOVDD
GAVSSA
AVSS_B
AVSS_A
AVDD2B
AVDD1B
IOVDDB
AVDD2A
AVDD1A
IOVDDACARRIER_POWER_GOOD
VIN_SEL
GND
+VIN
-VIN
GND
CARRIER_POWER_GOOD
+VIN
-VIN
AVSS_EXT
AVDD1_EXT
7V_LDO_OUT
AVDD1_EXT
GND
7V_LDO_OUT
GND
IOVDD_EXT
IOVDD
AVDD1
AVSS_EXT
GND
AVDD2
AVDD1
AVSS
GND
+7V_SUPPLY
AVSS
IOVDD_EXT
AVDD2_EXT
GND
AVDD2_EXT
CARRIER_POWER_GOOD
AVSSVIN_SEL
+12V_FMC
32
1
54321
54321
1
1
1
1
1
1
1
1
1
1
AC
A C
1
1
1
1
1
1
1
1
1
1
-2v5_powerGND
-2V5_OUT
NEG2V5_ENLDO_VIN_NEG
BA
7v_power
LDO_VIN7V_EN
+7V_SUPPLY
AVSS
IN
IN
5v_power
LDO_VIN5V_EN
+5V_AVDD
AVSS
3v3_power
3V3_EN
+3V3_IOVDD
LDO_VINGND
OUT
OUT
OUT
OUT
OUT
OUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
3V3 SUPPLY
ADJUSTABLE OPTION:
EG GREATER THAN 3.3V FOR -3.3 OPTIONONLY HIGHER THAN NOMINAL POSSIBLE
9 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
TBD0
603
0
TBD0
603
DNI
DNI
TBD0
603
0
1000
PF
ADP7118ARDZ-3.3
DNI
2.2U
F
2.2U
F
R9
R7
C102
C100
C101
R127
R126
U8
C103
LDO_VIN
GND
GND
+3V3_IOVDD
3V3_EN
21
87
63
PAD4
5
IN OUT
IN
IN
VOUTVIN
PAD
VIN
SS
EN
GND
SENSE/ADJ
VOUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
5V SUPPLY
SHORT R1 ANDREMOVE R2FOR 2.5V OUT
VOUT = 2.5(1+ (10K/10K)) = 5V
VOUT = 2.5(1+ (R1/R2))
10 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
2.2U
F
ADP7118ARDZ-2.5
1000
PF
10K
10K
TBD0
603
DNI
TBD0
603
DNI
2.2U
F
0
C106
C104 C1
05
R128
R129
C107
R_5V
_BR_
5V_A
U9
AVSS
+5V_AVDD
5V_EN
AVSS
LDO_VIN
21
87
63
PAD4
5
IN
IN
IN
VOUTVIN
PAD
VIN
SS
EN
GND
SENSE/ADJ
VOUT OUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
VOUT = 1.2(1+ (20K/4.22K)) = 6.89V = ~ 7V
VOUT = 1.2(1+ (20K/7.32K)) = 4.48V = ~ 4.5V
7V SUPPLY
VOUT = 1.2(1+ (R1/R2))
11 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
0
2.2U
F
TBD0
603
DNI
TBD0
603
DNI
1000
PF 20K
ADP7118ARDZ
2.2U
F
4.22
K
R138
C118
C119
R139
R140
R141
U10
C120
C121
7V_EN
AVSS
LDO_VIN
AVSS
+7V_SUPPLY
21
87
63
PAD4
5
IN
IN
IN
VOUTVIN
PAD
VIN
SS
EN
GND
SENSE/ADJ
VOUT OUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
NOT ENABLED BY DEFAULT
ON BOARD MOST NEG POINTEPAD CONNECTED TO
-2.5V SUPPLY
12 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
ADP7182ACPZN-2.5-R7
DNI
DNITBD0603
TBD0
603
2.2U
F
DNI
TBD0
603
2.2U
F
2V5NEN
C122 C1
23
R142 U11
C124
NEG2V5_EN
LDO_VIN_NEG
GND
-2V5_OUT16
42 5PA
D
3IN
IN
IN
NCNC EPAD
VIN
GND
ENVOUT OUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
DRIVER AMP
VCM BUFFER
PLACE RC AS CLOSE TO ADC2 AIN PINS AS POSSIBLE
AIN-AIN-
AIN+
DC TERMINAL BLOCKS
ANALOG INPUTS
NOTE: DISTANCE APART AS PER AMC STANDARD SPACING
AIN BLOCK INPUTSSMBS
AIN+
AIN ADC 2 - ADA4940
AMPLIFIER MEZZANINE CARD - OPTIONAL
NOTE: AIN+/AIN- DIMENSIONS APART TO MATCH10 LEAD PULSAR INTERPOSER BOARD
DIFFERENTIAL INPUT SIGNALS- TRACE LENGTHS MUST MATCH
13 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
0 DNISSW-107-01-T-S
0
TBD0603
DNI0
0
TBD0603
DNI
DNI
TLW-107-05-G-S
DNI
TBD0603
DNI0
TBD0603
1727023
TBD0603
0DNI
DNI
TBD0
603
DNI
DNI
TBD0603
DNI
DNI
1-1337482-0
1-1337482-0
0
120P
F
BLK
DNI
120P
F
TBD0603
TBD0603
DNI
BLK
TBD0603
820
82
AIN-
AIN+
AIN1-
AIN1+
P3
R56
R55
R54 P4P2
BINC-
BINC+
BINB-
BINA-
BINB+
BINA+
BUFC-
BUFC+
BUFB-
BUFA-
BUFA+
BUFB+
R60
R59
C37
C36
C38
AMODEB
AMODEA
AVSS
AVSS
AMC_AIN-
+7V_SUPPLY
VCM
AVSS
AVSS
AMC_OUT-
AVSS
AVSS
AMC_OUT+
AVDD1
+7V_SUPPLY
GPIO0_OUTPUT
AVDD1
GPIO0_OUTPUT
VCM
AVSS
AVDD1
IOVDD
AVSS
AVSS
GND
+7V_SUPPLYBYPASS_BUF2+
AMC_AIN-
AVSS
AMP2_AOUT+
AMC_AIN+
VCM
AVSS
AMC_AIN+
BYPASS_BUF2-AMP2_AOUT-
AMC_OUT+
AMC_OUT-
+7V_SUPPLY
AVSS
BYPASS_BUF2+
BYPASS_BUF2-
1
1
5432
1
5432
1
321
7654321
7654321
IN
IN
VCM_BUFFER_ADA4807
AVDD1AVSS
VCM
VCM_OUT
IN
OUT
OUT
IN
AIN_DIFF_AMP
AMP2_AOUT-AMP2_AOUT+
VCM_IN
CLAMP-CLAMP+AVSSAMP_MODEAMP_LOGICAIN2-AIN2++7V_SUPPLY
IN
IN
IN
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
LEFT FLOATING
-VCLAMP ON ADA4945
AIN
LOGIC LEVEL
+VCLAMP ON ADA4945
DISABLE
AS PER DSAND POWER PLANESRF AND RG OF ANY GNDNOTE: CLEAR AREA NEAR
ADC DRIVER AMPLIFIER
0.1% 1KOHM RES
VCM INPUTRC ON PARENT BLOCK
LOGIC LEVEL + 1V AND BELOW = LOWLOGIC LEVEL + 1.4V AND ABOVE = HIGH
MODE ON ADA4945
TP FOR SCOPE PROBE
FOR SE TERMINATION
AMP POWER
14 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
TBD0603
DNI
TBD0603
DNIDNI
1UF
TBD0
603
0
00
1K
1K
TBD0
603
DNI
1K
1K
DNI
DNI
TBD0
603
TBD0
603
TBD0
603
DNI
DNI
1K
0.1U
F
DNI
DNI
BLK
DNI
BLK
DNI
BLK
DNI
BLK
BLK
DNI
BLK
DNI
BLK
TBD0
603
DNI
TBD0
603
DNI
TBD0
603
DNI
0
5015 5015
TBD0
603
ADA4940-1ACPZ-R7
10K
294KR15
R14
R16
AVSS6AVSS4 AVSS5
R67
R68
R70
R69
LOGIC +CLAMP
-CLAMPMODE
C56
C55
AAIN-
C60
LG_B
LG_A VC+A
VC+B
C59
AAIN+
MDE
_B
VC-AMDE_A
VC-B
R66
R65
C58
C57
C61
U3
+7V_SUPPLY
LOGIC +VCLAMP
AIN2-
AIN2+
AVSS
AMP2_AOUT-
AMP2_AOUT+
AVSS
VCOMVCM_IN
AVSS
AVSS
CLAMP+
-VCLAMP
AMP_MODE
AVSS
AVSS
VCOM
-VCLAMP
+VCLAMPLOGIC
+7V_SUPPLY +7V_SUPPLY
+7V_SUPPLY
AVSS
MODE
MODE
AVSS
CLAMP-
AVSS
AMP_LOGIC
AVSS
11 1
1 1
11
1
1
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
DISABLE_N
+FB-FB
PAD
VOCM
-VS
+VS
-IN+IN
+OUT-OUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
VCM BUFFER
DEFAULT: STRAIGHT THROUGH UNBUFFERED
CLEAR GND/PWR PLANESBENATH IN/OUT PINS
VCM OUTPUT
15 15
<DESIGN_VIEW>
: Modulator out verisionProduct(s): AD7768-1HW TYPE : Customer Evaluation
1:1
E02_044287
<PTD_ENGINEER>
DNI
BLK
1-1337482-0
0
3.3
10UF
0
100
1.1K
100UF
ADA4807-2ARMZ
DNI
100U
F1K
10K
TBD0
603
0
TBD0603
100
100U
F
1N4148W-7-F
1N4148W-7-F
0
D5
D6
C33
R39
R38
R40
C29
R37
C25
C27
R28
R24
VCMOUT
R41
VCM_B
VCM_A
R23
R17
R19
A1VCM
VCM_OUT
VCM
AVSS
AVDD1
VCM
AVSS
A
C A
C
NP
NP
NP
NP
5432
1
75
6 1
IN
IN
IN
OUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE