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AD7626Interface

AD7626 Interface - LVDS7

AD7626

CONVERSION4

CONTROLCMOS (CNV+ ONLY)

ORLVDS CNV+ AND CNV–

USING 100ΩTERMINATION RESISTOR

DIGITAL INTERFACE SIGNALS

DIGITAL HOSTLVDS TRANSMIT AND RECEIVE

CNV–

CNV+

D–

D+

VIO

GND

DCO–

DCO+

CLK–

CLK+

VIO(2.5V)

100Ω

PADDLE

8 9 10 11 12 13 14 15 16 17

100Ω100Ω

NC

TO ENABLE SELF-CLOCKED MODE, TIE DCO+ (Pin 15) TO GND

Use DCO+/- and D+/- as synchronous LVDS data and clock outputs

tMSB and tCLKL set the limits for the CLK+/- quiet window

SAMPLEN

tMSB(N)

tCLKL(N-1)

SAMPLEN+1

Burst 16 CLK+/-

CLK+/- Quiet

D+

D-

DATA (N+1)

CLK+/- Quiet

tMSB(N+1)

tCLKL(N)

CLK+

CLK-

CNV+

CNV-

tCYC tCYC

DATA (N)DATA (N-1)

Burst 16 CLK+/-

Conversion Ratet = N t = N+1 t = N+2

DCO+

ECHO CLOCK MODE-Creating Burst CLK+/- , tMSB

•D+/- is Invalid in the CLK+/- Quiet Window – Highlighted in Yellow

•D+/- is output synchronous to DCO+/-

•The quiet window is effectively set by tMSB and tCLKL

•tMSB is the min time from the CNV rising edge until that conversion data is ready to be clocked out – i.e. once tMSB elapses a burst of 16 CLK+/- may be applied for data acquisition

SAMPLEN

tMSB(N)

tCLKL(N-1)

SAMPLEN+1

Burst 16 CLK+/-

CLK+/- Quiet

D+

D-

DATA (N+1)

CLK+/- Quiet

tMSB(N+1)

tCLKL(N)

CLK+

CLK-

CNV+

CNV-

tCYC tCYC

DATA (N)DATA (N-1)

Burst 16 CLK+/-

Conversion Ratet = N t = N+1 t = N+2

DCO+

ECHO CLOCK MODE-Creating Burst CLK+/- , tCLKL

•For the same data result – tMSB and tCLKL are referenced from consecutive CNV rising edges

•The other limit for the quiet window is set by tCLKL

•tCLKL timing spec ensures that you have finished clocking the current conversion result prior to the next result being ready internally in the device i.e. you’re not clock results from two different conversions