A/D Flash MCU with EEPROM HT66F60A HT66F70AA/D Flash MCU with EEPROM. General Description. The HT66Fx0A series of devices are Flash Memory A/D type 8-bit high performance RISC architecture

A/D Flash MCU with EEPROM

HT66F60AHT66F70A

Revision: V1.40 Date: ��st �� 01��st �� 01�

Rev. 1.40 � ��st �� 01� Rev. 1.40 3 ��st �� 01�

HT66F60A/HT66F70AA/D Flash MCU with EEPROM

Table of Contents

Features ............................................................................................................ 7CPU Feat�res ........................................................................................................................ �Peripheral Feat�res ................................................................................................................ �

General Description ......................................................................................... 8Selection Table ................................................................................................. 8Block Diagram .................................................................................................. 9Pin Assignment .............................................................................................. 10Pin Description .............................................................................................. 12Absolute Maximum Ratings .......................................................................... 18D.C. Characteristics ....................................................................................... 18A.C. Characteristics ....................................................................................... 21A/D Converter Electrical Characteristics ..................................................... 22LVD & LVR Electrical Characteristics .......................................................... 22Comparator Electrical Characteristics ........................................................ 23Power on Reset Electrical Characteristics ................................................. 23System Architecture ...................................................................................... 24

Clockin� and Pipelinin� ......................................................................................................... �4Pro�ram Co�nter ................................................................................................................... �5Stack ..................................................................................................................................... �6�rithmetic and Lo�ic Unit – �LU ........................................................................................... �6

Flash Program Memory ................................................................................. 27Str�ct�re ................................................................................................................................ ��Special Vectors ..................................................................................................................... ��Look-�p Table ........................................................................................................................ ��Table Pro�ram Example ........................................................................................................ �9In Circ�it Pro�rammin� – ICP ............................................................................................... 30On-Chip Deb�� S�pport – OCDS ......................................................................................... 31In �pplication Pro�rammin� – I�P ........................................................................................ 31

Data Memory .................................................................................................. 39Str�ct�re ................................................................................................................................ 39General P�rpose Data Memory ............................................................................................ 40Special P�rpose Data Memory ............................................................................................. 40

Special Function Register Description ........................................................ 42Indirect �ddressin� Re�isters – I�R0� I�R1 ......................................................................... 4�Memory Pointers – MP0� MP1 .............................................................................................. 4�Bank Pointer – BP ................................................................................................................. 43�cc�m�lator – �CC ............................................................................................................... 43Pro�ram Co�nter Low Re�ister – PCL .................................................................................. 44Look-�p Table Re�isters – TBLP� TBHP� TBLH ..................................................................... 44Stat�s Re�ister – ST�TUS .................................................................................................... 44

Rev. 1.40 � ��st �� 01� Rev. 1.40 3 ��st �� 01�


EEPROM Data Memory .................................................................................. 46EEPROM Data Memory Str�ct�re ........................................................................................ 46EEPROM Re�isters .............................................................................................................. 46Readin� Data from the EEPROM ......................................................................................... 4�Writin� Data to the EEPROM ................................................................................................ 4�Write Protection ..................................................................................................................... 4�EEPROM Interr�pt ................................................................................................................ 4�Pro�rammin� Considerations ................................................................................................ 4�Pro�rammin� Examples ........................................................................................................ 49

Oscillator ........................................................................................................ 50Oscillator Overview ............................................................................................................... 50System Clock Configurations ................................................................................................ 50External Crystal/Ceramic Oscillator – HXT ........................................................................... 51External RC Oscillator – ERC ............................................................................................... 5�Internal Hi�h Speed RC Oscillator – HIRC ........................................................................... 5�External 3�.�6�kHz Crystal Oscillator – LXT ........................................................................ 53Internal Low Speed Oscillator – LIRC ................................................................................... 54S�pplementary Oscillators .................................................................................................... 54

Operating Modes and System Clocks ......................................................... 55System Clock ........................................................................................................................ 55System Operation Modes ...................................................................................................... 56Control Re�ister .................................................................................................................... 5�Fast Wake-�p ........................................................................................................................ 60Operatin� Mode Switchin� .................................................................................................... 61NORM�L Mode to SLOW Mode Switchin� ........................................................................... 6�SLOW Mode to NORM�L Mode Switchin� ........................................................................... 63Enterin� the SLEEP0 Mode .................................................................................................. 64Enterin� the SLEEP1 Mode .................................................................................................. 64Enterin� the IDLE0 Mode ...................................................................................................... 64Enterin� the IDLE1 Mode ...................................................................................................... 65Standby C�rrent Considerations ........................................................................................... 65Wake-�p ................................................................................................................................ 66Pro�rammin� Considerations ................................................................................................ 66

Watchdog Timer ............................................................................................. 67Watchdo� Timer Clock So�rce .............................................................................................. 6�Watchdo� Timer Control Re�ister ......................................................................................... 6�Watchdo� Timer Operation ................................................................................................... 6�

Reset and Initialisation .................................................................................. 70Reset F�nctions .................................................................................................................... �0Reset Initial Conditions ......................................................................................................... �4

Input/Output Ports ......................................................................................... 78P�ll-hi�h Resistors ................................................................................................................ �0Port � Wake-�p ..................................................................................................................... �0I/O Port Control Re�isters ..................................................................................................... �0Pin-shared F�nctions ............................................................................................................ �0

Rev. 1.40 4 ��st �� 01� Rev. 1.40 5 ��st �� 01�


I/O Pin Str�ct�res .................................................................................................................. 93Pro�rammin� Considerations ................................................................................................ 94

Timer Modules – TM ...................................................................................... 94Introd�ction ........................................................................................................................... 94TM Operation ........................................................................................................................ 95TM Clock So�rce ................................................................................................................... 95TM Interr�pts ......................................................................................................................... 95TM External Pins ................................................................................................................... 96TM Inp�t/O�tp�t Pin Control ................................................................................................. 9�Pro�rammin� Considerations ................................................................................................ 9�

Compact Type TM – CTM .............................................................................. 99Compact TM Operation ......................................................................................................... 99Compact Type TM Re�ister Description.............................................................................. 100Compact Type TM Operatin� Modes .................................................................................. 104Compare Match O�tp�t Mode ............................................................................................. 104Timer/Co�nter Mode ........................................................................................................... 10�PWM O�tp�t Mode .............................................................................................................. 10�

Standard Type TM – STM .............................................................................110Standard TM Operation ........................................................................................................110Standard Type TM Re�ister Description ..............................................................................111Standard Type TM Operatin� Modes ...................................................................................115Compare Match O�tp�t Mode ..............................................................................................115Timer/Co�nter Mode ............................................................................................................11�PWM O�tp�t Mode ...............................................................................................................11�Sin�le P�lse Mode .............................................................................................................. 1�1Capt�re Inp�t Mode ............................................................................................................ 1�3

Enhanced Type TM – ETM ........................................................................... 125Enhanced TM Operation ..................................................................................................... 1�5Enhanced Type TM Re�ister Description ............................................................................ 1�6Enhanced Type TM Operatin� Modes................................................................................. 13�Compare O�tp�t Mode ........................................................................................................ 133Timer/Co�nter Mode ........................................................................................................... 13�PWM O�tp�t Mode .............................................................................................................. 13�Sin�le P�lse Mode .............................................................................................................. 144Capt�re Inp�t Mode ............................................................................................................ 146

Aanlog to Digital Converter ........................................................................ 149�/D Overview ...................................................................................................................... 149�/D Converter Re�ister Description .................................................................................... 149�/D Operation ..................................................................................................................... 153�/D Inp�t Pins ..................................................................................................................... 154S�mmary of �/D Conversion Steps ..................................................................................... 154Pro�rammin� Considerations .............................................................................................. 156�/D Transfer F�nction ......................................................................................................... 156�/D Pro�rammin� Example ................................................................................................. 15�

Rev. 1.40 4 ��st �� 01� Rev. 1.40 5 ��st �� 01�


Comparators ................................................................................................ 159Comparator Operation ........................................................................................................ 159Comparator Re�isters ......................................................................................................... 160Comparator Interr�pt ........................................................................................................... 16�Pro�rammin� Considerations .............................................................................................. 16�

Serial Interface Module – SIM ..................................................................... 162SPI Interface ....................................................................................................................... 16�SPI Re�isters ...................................................................................................................... 164SPI Comm�nication ............................................................................................................ 16�I�C Interface ........................................................................................................................ 169I�C Interface Operation ........................................................................................................ 169I�C Re�isters ....................................................................................................................... 1�0I�C B�s Comm�nication ...................................................................................................... 1�4I�C B�s Start Si�nal ............................................................................................................. 1�5Slave �ddress ..................................................................................................................... 1�5I�C B�s Read/Write Si�nal .................................................................................................. 1�6I�C B�s Slave �ddress �cknowled�e Si�nal ....................................................................... 1�6I�C B�s Data and �cknowled�e Si�nal ............................................................................... 1�6

Peripheral Clock Output .............................................................................. 179Peripheral Clock Operation ................................................................................................. 1�9Peripheral Clock Re�isters .................................................................................................. 1�0

Serial Interface – SPIA ................................................................................. 181SPI� Interface Operation .................................................................................................... 1�1SPI� re�isters ..................................................................................................................... 1��SPI� Comm�nication .......................................................................................................... 1�5SPI� B�s Enable/Disable .................................................................................................... 1��SPI� Operation ................................................................................................................... 1��Error Detection .................................................................................................................... 1��

Interrupts ...................................................................................................... 189Interr�pt Re�isters ............................................................................................................... 1�9Interr�pt Operation .............................................................................................................. �00External Interr�pt ................................................................................................................. �01Comparator Interr�pt ........................................................................................................... �01M�lti-f�nction Interr�pt ........................................................................................................ �01�/D Converter Interr�pt ....................................................................................................... �0�Time Base Interr�pt ............................................................................................................. �0�Serial Interface Mod�le Interr�pts ....................................................................................... �04SPI� Interface Interr�pt ....................................................................................................... �04External Peripheral Interr�pt ............................................................................................... �04EEPROM Interr�pt .............................................................................................................. �05LVD Interr�pt ....................................................................................................................... �05TM Interr�pts ....................................................................................................................... �05Interr�pt Wake-�p F�nction ................................................................................................. �06Pro�rammin� Considerations .............................................................................................. �06

Rev. 1.40 6 ��st �� 01� Rev. 1.40 � ��st �� 01�


Low Voltage Detector – LVD ....................................................................... 207LVD Re�ister ....................................................................................................................... �0�LVD Operation ..................................................................................................................... �0�

SCOM Function for LCD .............................................................................. 209LCD Operation .................................................................................................................... �09LCD Bias Control ................................................................................................................ �09

Configuration Options ................................................................................. 210Application Circuits ..................................................................................... 210Instruction Set ...............................................................................................211

Introd�ction ..........................................................................................................................�11Instr�ction Timin� .................................................................................................................�11Movin� and Transferrin� Data ..............................................................................................�11�rithmetic Operations ...........................................................................................................�11Lo�ical and Rotate Operation ............................................................................................. �1�Branches and Control Transfer ........................................................................................... �1�Bit Operations ..................................................................................................................... �1�Table Read Operations ....................................................................................................... �1�Other Operations ................................................................................................................. �1�

Instruction Set Summary ............................................................................ 213Table Conventions ............................................................................................................... �13Extended Instr�ction Set ..................................................................................................... �15

Instruction Definition ................................................................................... 217Extended Instruction Definition ........................................................................................... ��

Package Information ................................................................................... 2344�-pin LQFP (�mm×�mm) O�tline Dimensions .................................................................. �3564-pin LQFP (�mm×�mm) O�tline Dimensions .................................................................. �36

Rev. 1.40 6 ��st �� 01� Rev. 1.40 � ��st �� 01�


Features

CPU Features • OperatingVoltage:

♦ fSYS=8MHz:2.2V~5.5V♦ fSYS=12MHz:2.7V~5.5V♦ fSYS=16MHz:4.5V~5.5V

• Upto0.25μsinstructioncyclewith16MHzsystemclockatVDD=5V• Powerdownandwake-upfunctionstoreducepowerconsumption• Fiveoscillators:

♦ ExternalCrystal--HXT♦ External32.768kHzCrystal--LXT♦ ExternalRC--ERC♦ InternalRC--HIRC♦ Internal32kHzRC--LIRC

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP• Fullyintegratedinternal8MHzocilllatorrequiresnoexternalcomponents• Allinstructionsexecutedin1~3instructioncycles• Tablereadinstructions• 114powerfulinstructions• Upto16-levelsubroutinenesting• Bitmanipulationinstruction

Peripheral Features • FlashProgramMemory:16k×16~32k×16

• DataMemory:1024×8~2048×8• True EEPROMMemory:128×8• InApplicationProgrammingfunction• WatchdogTimerfunction• Upto61bidirectionalI/Olines• Softwarecontrolled4-SCOMlinesLCDdriverwith1/2bias• Multiplepin-sharedexternalinterrupts• MultipleTimerModulefortimemeasure,inputcapture,comparematchoutput,PWMoutputor singlepulseoutputfunction

• SerialInterfacesModule–SIMforSPIorI2C• SinglesefialSPIinterface–SPIA• DualComparatorfunctions• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals• Multi-channel12-bitresolutionA/Dconverter• Lowvoltageresetfunction• Lowvoltagedetectfunction• Widerangeofavailablepackagetypes• Flashprogrammemorycanbere-programmedupto100,000times• Flashprogrammemorydataretention>10years• True EEPROMdatamemorycanbere-programmedupto1,000,000times• True EEPROMdatamemorydataretention>10years

Rev. 1.40 � ��st �� 01� Rev. 1.40 9 ��st �� 01�


General DescriptionTheHT66Fx0AseriesofdevicesareFlashMemoryA/D type8-bithighperformanceRISCarchitecturemicrocontrollers,designed for awide rangeof applications.Offeringusers theconvenienceofFlashMemorymulti-programmingfeatures,thesedevicesalsoincludeawiderangeoffunctionsandfeatures.OthermemoryincludesanareaofRAMDataMemoryaswellasanareaoftrue EEPROMmemoryforstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.

Analog features includeamulti-channel12-bitA/Dconverteranddualcomparator functions.Multiple andextremely flexibleTimerModulesprovide timing,pulsegenerationandPWMgeneration functions. Communication with the outside world is catered for by includingfullyintegrated SPI or I2C interface functions, two popular interfaceswhich provide designerswith a means of easy communication with external peripheral hardware. Protective featuressuch as an internalWatchdog Timer, LowVoltage Reset and LowVoltage Detector coupledwith excellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostile electrical environments. A full choice of HXT, LXT, ERC, HIRC and LIRC oscillatorfunctions are provided including a fully integrated system oscillator which requires noexternal components for its implementation. The ability to operate and switch dynamicallybetween a range of operatingmodes using different clock sources gives users the ability tooptimisemicrocontrolleroperationandminimisepowerconsumption.

The inclusion of flexible I/O programming features, Time-Base functions along with manyother features ensure that the devices will find excellent use in applications such as electronicmetering,environmentalmonitoring,handheld instruments,householdappliances, electronicallycontrolledtools,motordrivinginadditiontomanyothers.

Selection TableMost featuresarecommon toalldevices.Themain featuresdistinguishing themareProgramMemoryandDataMemorycapacity.Thefollowing tablesummarises themainfeaturesofeachdevice.

Part No. Program Memory

Data Memory

Data EEPROM I/O External

InterruptA/D

Converter Timer Module SIM SPIA Time Base Comparators Stacks package

HT66F60� 16k × 16 10�4 × � 1�� × � 61 4 1�-bit × 1�10-bit CTM × �16-bit STM × 310-bit ETM × 1

√ √ � � 16 4�/64 LQFP

HT66F�0� 3�k × 16 �04� × � 1�� × � 61 4 1�-bit × 1�10-bit CTM × �16-bit STM × 310-bit ETM × 1

√ √ � � 16 4�/64 LQFP

Note:Asdevicesexistinmorethanonepackageformat,thetablereflectsthesituationforthepackagewiththemostpins.

Rev. 1.40 � ��st �� 01� Rev. 1.40 9 ��st �� 01�


Block Diagram

� � � � � � � �

� � � � � � � ��

� � ��

� � ��

� � � � � � � ��

� � � � � � ��

� � � � � � ��

� � � � � � � ��

� � � ��

� � � ��

� � � � ��

� ��

� � � � �

� � � � � � �

� � ��

� � ��

� � � � � � � � � � �

� � � � � � � � � � �

� � � � � � ��

� � � � �

Rev. 1.40 10 ��st �� 01� Rev. 1.40 11 ��st �� 01�


Pin Assignment

PH

0/TP0/TP0B

/�N

0/VR

EF/C

0X

PF1/�N11/C1PPF0/�N10/C1NPE�/�N9/INT1PE6/�N�/INT0

VSSVDD

PB4/XT�PB3/XT1

VSS�PB1/OSC1PB�/OSC�

PE5/TP3/TP3B

PE4/TP1B

/TP1BB

/TP1IB

PB0/R

ES

PF�PE

3/SD

O�

/TCK

3PE

�/SD

I�/IN

T�PE

1/SC

K�/IN

T1

PC0/TP1B

/TP1BB

/TP1IB

/SC

OM

0PC

1/TP1B/TP1B

B/TP

1IB/S

CO

M1

PC�/S

CO

M3/TP

1�/TP

1I�PC

6/SC

OM

�/TP0/TP

0BPD

5/TP0/TP0B

PD4/TP�/TP�B/TP�IPD3/TP3/TP3B/SDO/SCK/SCL/TCK1PD�/SDI/SD�/TCK0PD1/TP�/TP�B/TP�I/SDO/SCK/SCLPD0/TP3/TP3B/SCS/TCK�PC5/INT3/TP0/TP0B/TP1B/TP1BB/TP1IB/INT1/PCKPC4/INT�/TCK3/TP�/TP�B/TP�I/INT0/PINTPC3/PINT/TP�/TP�B/TP�I/C1XPC�/PCK/TCK�/C0XPD�/SCSPD6/SCK/SCLPB�/SDI/SD�

PB6/S

DO

P��

P�0

PB

5/SC

S

13 14 15 16 1� 1� 19 �0 �1 �� 3 �4

P�

�/SCK

/SC

L/�N�

P�6/S

DI/S

D�/�N

6P

�5/SD

O/�

N5/C

1XP

�4/IN

T1/TCK

1/�N4

P�

3/INT0/�

N3/C

0NPH

1/TCK

0/�N

�/C0P

P�1/TP

1�/TP

1I�/�N1

1

�

3

4

5

6

�

�

9

10

11

1�

��

�6

�5

��

�9

30

31

3�

33

34

35

364� 4� 46 45 44 43 4� 41 40 39 3� 3�

PE0/S

CS�

/INT0

HT66F60A/HT66F70A 48 LQFP-A

PH0/TP0/TP0B/�N0/VREF/C0X 1

�

3

4

5

6

�

�

9

10

11

1�

13

14

15

16


PF6VSSVDD

PB4/XT�PB3/XT1


PF4PF3

PE5/TP3/TP3B

PE

4/TP1B

/TP1B

B/TP

1IBP

B0/R

ES

PF5

PF�

PE

3/SD

O�/TC

K3

PE

�/SD

I�/IN

T�P

E1/S

CK

�/INT1

PC

0/TP1B

/TP1B

B/TP

1IB/SC

OM

0P

C1/TP

1B/TP

1BB

/TP1IB

/SCO

M1

PC

�/SC

OM

3/TP1�/TP

1I�P

C6/S

CO

M�/TP

0/TP0B

PG

0/C0X

PG

1/C1X

PD

5/TP0/TP

0BP

D4/TP

�/TP�B/TP

�I

39

3�

3�

36

35

34

33

40

41

4�

43

44

45

46

4�

4�

PG4/TP4/TP4B/TP4IPG3/TP4/TP4B/TP4IPG�/TCK4PD3/TP3/TP3B/SDO/SCK/SCL/TCK1PD�/SDI/SD�/TCK0PD1/TP�/TP�B/TP�I/SDO/SCK/SCLPD0/TP3/TP3B/SCS/TCK�PC5/INT3/TP0/TP0B/TP1B/TP1BB/TP1IB/INT1/PCKPC4/INT�/TCK3/TP�/TP�B/TP�I/INT0/PINTPC3/PINT/TP�/TP�B/TP�I/C1XPC�/PCK/TCK�/C0XPD�/SCSPD6/SCK/SCLPB�/SDI/SD�PB6/SDOPH5/SDO�

PH4/S

DI�

P�

�P

�0

PH

3/SCK

�P

H�/SC

S�

PG

�/TP5/TP5B

/TP5I

PG

6/TP5/TP5B

/TP5I

PG

5/TCK

5P

B5/SC

S

1� 1� 19 �0 �1 �� 3 �4 �5 �6 �� 9 30 31 3�

64 63 6� 61 60 59 5� 5� 56 55 54 53 5� 51 50 49

P�

�/SC

K/S

CL/�

N�

P�

6/SDI/S

D�

/�N

6P

�5/SD

O/�

N5/C

1XP

�4/IN

T1/TCK1/�

N4

P�3/IN

T0/�N

3/C0N

PH

1/TCK

0/�N

�/C0P

P�1/TP1�

/TP1I�/�

N1

PE

0/SC

S�/IN

T0

HT66F60A/HT66F70A64 LQFP-A

Rev. 1.40 10 ��st �� 01� Rev. 1.40 11 ��st �� 01�


PH

0/TP0/TP0B

/�N

0/VR

EF/C

0X


VSSVDD

PB4/XT�PB3/XT1


PE5/TP3/TP3B

PE4/TP1B

/TP1BB

/TP1IB

PB0/R

ES

PF�PE

3/SD

O�

/TCK

3PE

�/SD

I�/IN

T�PE

1/SC

K�/IN

T1

PC0/TP1B

/TP1BB

/TP1IB

/SC

OM

0PC

1/TP1B/TP1B

B/TP

1IB/S

CO

M1

PC�/S

CO

M3/TP

1�/TP

1I�PC

6/SC

OM

�/TP0/TP

0BPD

5/TP0/TP0B

PD4/TP�/TP�B/TP�IPD3/TP3/TP3B/SDO/SCK/SCL/TCK1PD�/SDI/SD�/TCK0PD1/TP�/TP�B/TP�I/SDO/SCK/SCLPD0/TP3/TP3B/SCS/TCK�PC5/INT3/TP0/TP0B/TP1B/TP1BB/TP1IB/INT1/PCKPC4/INT�/TCK3/TP�/TP�B/TP�I/INT0/PINTPC3/PINT/TP�/TP�B/TP�I/C1XPC�/PCK/TCK�/C0XPD�/SCSPD6/SCK/SCLPB�/SDI/SD�

PB6/S

DO

P�

�/ICPC

K/O

CD

SC

KP

�0/IC

PD�

/OC

DS

D�

PB

5/SC

S

13 14 15 16 1� 1� 19 �0 �1 �� 3 �4

P�

�/SCK

/SC

L/�N�

P�6/S

DI/S

D�/�N

6P

�5/SD

O/�

N5/C

1XP

�4/IN

T1/TCK

1/�N4

P�

3/INT0/�

N3/C

0NPH

1/TCK

0/�N

�/C0P

P�1/TP

1�/TP

1I�/�N1

1

�

3

4

5

6

�

�

9

10

11

1�

��

�6

�5

��

�9

30

31

3�

33

34

35

364� 4� 46 45 44 43 4� 41 40 39 3� 3�

PE0/S

CS�

/INT0

HT66V70A48 LQFP-A

PH0/TP0/TP0B/�N0/VREF/C0X 1

�

3

4

5

6

�

�

9

10

11

1�

13

14

15

16


PF6VSSVDD

PB4/XT�PB3/XT1


PF4PF3

PE5/TP3/TP3B

PE4/TP

1B/TP

1BB

/TP1IBP

B0/RE

S

PF5

PF�

PE3/S

DO

�/TCK

3P

E�/SD

I�/IN

T�P

E1/SC

K�/IN

T1

PC

0/TP1B

/TP1B

B/TP1IB

/SC

OM

0P

C1/TP

1B/TP

1BB

/TP1IB/S

CO

M1

PC

�/SC

OM

3/TP1�

/TP1I�

PC

6/SC

OM

�/TP0/TP

0BP

G0/C

0XP

G1/C

1XP

D5/TP

0/TP0B

PD

4/TP�/TP

�B/TP�I

39

3�

3�

36

35

34

33

40

41

4�

43

44

45

46

4�

4�

PG4/TP4/TP4B/TP4IPG3/TP4/TP4B/TP4IPG�/TCK4PD3/TP3/TP3B/SDO/SCK/SCL/TCK1PD�/SDI/SD�/TCK0PD1/TP�/TP�B/TP�I/SDO/SCK/SCLPD0/TP3/TP3B/SCS/TCK�PC5/INT3/TP0/TP0B/TP1B/TP1BB/TP1IB/INT1/PCKPC4/INT�/TCK3/TP�/TP�B/TP�I/INT0/PINTPC3/PINT/TP�/TP�B/TP�I/C1XPC�/PCK/TCK�/C0XPD�/SCSPD6/SCK/SCLPB�/SDI/SD�PB6/SDOPH5/SDO�

PH

4/SD

I�P�

�/ICP

CK/O

CD

SC

KP�

0/ICP

D�/O

CD

SD

�P

H3/S

CK

�P

H�/S

CS

�P

G�/TP

5/TP5B/TP5I

PG

6/TP5/TP5B

/TP5IP

G5/TC

K5

PB5/S

CS

1� 1� 19 �0 �1 �� 3 �4 �5 �6 �� 9 30 31 3�

64 63 6� 61 60 59 5� 5� 56 55 54 53 5� 51 50 49

P��/S

CK/SC

L/�N

�P

�6/SD

I/SD�

/�N

6P

�5/SD

O/�N

5/C1X

P�

4/INT1/TC

K1/�N

4P�

3/INT0/�N

3/C0N

PH

1/TCK

0/�N�/C

0PP

�1/TP

1�/TP1I�

/�N

1

PE0/S

CS�

/INT0

HT66V70A64 LQFP-A

Note: 1. If thepin-sharedpin functionshavemultipleoutputs simultaneously, thepin-shared function isdeterminedby the corresponding software controlbits except the functionsdeterminedby theconfigurationoptions.

2.TheHT66Vx0Adeviceis theEVchipof theHT66Fx0Aseriesofdevices.Itsupports the“On-ChipDebug”functionfordebuggingduringdevelopmentusingtheOCDSDAandOCDSCKpinsconnectedtotheHoltekHT-IDEdevelopmenttools.

Rev. 1.40 1� ��st �� 01� Rev. 1.40 13 ��st �� 01�


Pin DescriptionPad Name Function OPT I/T O/T Description

P�0/ICPD�/OCDSD�

P�0 P�WUP�PU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p and wake-�p

ICPD� — ST CMOS ICP Data/�ddressOCDSD� — ST CMOS OCDS Data/�ddress� for EV chip only

P�1/TP1�/ TP1I�/�N1

P�1P�WUP�PUP�S0

ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p and wake-�p

TP1� P�S0 — CMOS TM1 � o�tp�tTP1I� IFS� ST — TM1 � inp�t�N1 P�S0 �N — �/D Converter analo� inp�t

P��/ICPCK/OCDSCK

P�� P�WUP�PU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p and wake-�p

ICPCK — ST CMOS ICP Clock pinOCDSCK — ST — OCDS Clock pin� for EV chip only

P�3/INT0/ �N3/C0N



INT0INTEGINTC0IFS0

ST — External Interr�pt 0

�N3 P�S1 �N — �/D Converter analo� inp�tC0N P�S1 �N — Comparator 0 invertin� inp�t

P�4/INT1/ TCK1/�N4

P�4P�PUP�WUP�S�


INT1INTEGINTC0IFS0


TCK1 IFS1 ST — TM1 inp�t�N4 P�S1 �N — �/D Converter analo� inp�t

P�5/SDO/ �N5/C1X

P�5P�WUP�PUP�S�


SDO P�S� — CMOS SPI data o�tp�t�N5 P�S� �N — �/D Converter analo� inp�tC1X P�S� — CMOS Comparator 1 o�tp�t

P�6/SDI/ SD�/�N6



SDI P�S3IFS4 ST — SPI data inp�t

SD� P�S3IFS4 ST NMOS I�C data line

�N6 P�S3 �N — �/D Converter analo� inp�t

P��/SCK/ SCL/�N�

P��P�WUP�PUP�S3


SCK P�S3IFS4 ST CMOS SPI serial clock

SCL P�S3IFS4 ST NMOS I�C clock line

�N� P�S3 �N — �/D Converter analo� inp�t

Rev. 1.40 1� ��st �� 01� Rev. 1.40 13 ��st �� 01�


Pad Name Function OPT I/T O/T Description

PB0/RESPB0 PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p RES CO ST — Reset pin

PB1/OSC1PB1 PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

OSC1 CO HXT — HXT/ERC oscillator pin & EC mode inp�t pin

PB�/OSC�PB� PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

OSC� CO — HXT HXT oscillator pin

PB3/XT1PB3 PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�pXT1 CO LXT — LXT oscillator pin

PB4/XT�PB4 PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�pXT� CO — LXT LXT oscillator pin

PB5/SCSPB5 PBPU

PBS� ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

SCS PBS�IFS4 ST CMOS SPI slave select

PB6/SDOPB6 PBPU

PBS3 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p and wake-�p

SDO PBS3 — CMOS SPI data o�tp�t

PB�/SDI/SD�

PB� PBPUPBS3 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p and wake-�p

SDI PBS3IFS4 ST — SPI data inp�t

SD� PBS3IFS4 ST NMOS I�C data line

PC0/TP1B/TP1BB/TP1IB/SCOM0

PC0 PCPUPCS0 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

TP1B PCS0 — CMOS TM1 B o�tp�tTP1BB PCS0 — CMOS TM1 inverted B o�tp�tTP1IB IFS� ST — TM1 B inp�t

SCOM0 PCS0 — SCOM LCD common o�tp�t

PC1/TP1B/TP1BB/TP1IB/SCOM1


TP1B PCS0 — CMOS TM1 B o�tp�tTP1BB PCS0 — CMOS TM1 inverted B o�tp�tTP1IB IFS� ST — TM1 B inp�t

SCOM1 PCS0 — SCOM LCD common o�tp�t

PC�/PCK/ TCK�/C0X

PC� PCPUPCS1 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

PCK PCS1 — CMOS Peripheral clock o�tp�tTCK� IFS1 ST — TM� inp�tC0X PCS1 — CMOS Comparator 0 o�tp�t

PC3/PINT/TP�/TP�B/TP�I/C1X


PINT IFS0 ST — Peripheral interr�ptTP� PCS1 — CMOS TM� o�tp�t

TP�B PCS1 — CMOS TM� inverted o�tp�tTP�I IFS� ST — TM� inp�tC1X PCS1 — CMOS Comparator 1 o�tp�t

Rev. 1.40 14 ��st �� 01� Rev. 1.40 15 ��st �� 01�



PC4/INT�/TCK3/TP�/TP�B/TP�I/INT0/PINT

PC4 PCPUPCS� ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

INT�INTEGINTC3IFS0

ST — External Interr�pt �

TCK3 IFS1 ST — TM3 inp�tTP� PCS1 — CMOS TM� o�tp�t

TP�B PCS1 — CMOS TM� inverted o�tp�tTP�I IFS� ST — TM� inp�t

INT0INTEGINTC0IFS0


PINT IFS0 ST — Peripheral interr�pt

PC5/INT3/TP0/TP0B/TP1B/TP1BB/TP1IB/INT1/PCK

PC5 PCPUPCS� ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

INT3 INTEGINTC3 ST — External Interr�pt 3

TP0 PCS� — CMOS TM0 o�tp�tTP0B PCS� — CMOS TM0 inverted o�tp�tTP1B PCS� — CMOS TM1 B o�tp�t

TP1BB PCS� — CMOS TM1 inverted B o�tp�tTP1IB IFS� ST — TM1 B inp�t

INT1INTEGINTC0IFS0


PCK PCS� — CMOS Peripheral clock o�tp�t

PC6/SCOM�/ TP0/TP0B


SCOM� PCS3 — SCOM LCD common o�tp�tTP0 PCS3 — CMOS TM0 o�tp�t

TP0B PCS3 — CMOS TM0 inverted o�tp�t

PC�/SCOM3/TP1�/TP1I�

PC� PCPUPCS3 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

SCOM3 PCS3 — SCOM LCD common o�tp�tTP1� PCS3 — CMOS TM1 � o�tp�tTP1I� IFS� ST — TM1 � inp�t

PD0/TP3/TP3B/SCS/TCK�

PD0 PDPUPDS0 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

TP3 PDS0 — CMOS TM3 o�tp�tTP3B PDS0 — CMOS TM3 inverted o�tp�t

SCS PDS0IFS4 ST CMOS SPI slave select

TCK� IFS1 ST — TM� inp�t

Rev. 1.40 14 ��st �� 01� Rev. 1.40 15 ��st �� 01�



PD1/TP�/TP�B/TP�I/SDO/SCK/SCL


TP� PDS0 — CMOS TM� o�tp�tTP�B PDS0 — CMOS TM� inverted o�tp�tTP�I IFS� ST — TM� inp�tSDO PDS0 — CMOS SPI slave select

SCK PDS0IFS4 ST CMOS SPI serial clock

SCL PDS0IFS4 ST NMOS I�C clock line

PD�/SDI/ SD�/TCK0

PD� PDPUPDS1 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

SDI PDS1IFS4 ST — SPI data inp�t

SD� PDS1IFS4 ST NMOS I�C data line

TCK0 IFS1 ST — TM0 inp�t

PD3/TP3/TP3B/SDO/SCK/SCL/TCK1


TP3 PDS1 — CMOS TM3 o�tp�tTP3B PDS1 — CMOS TM� inverted o�tp�tSDO PDS1 — CMOS SPI slave select



TCK1 IFS1 ST — TM1 inp�t

PD4/TP�/TP�B/TP�I

PD4 PDPUPDS� ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

TP� PDS� — CMOS TM� o�tp�tTP�B PDS� — CMOS TM� inverted o�tp�tTP�I IFS� ST — TM� inp�t

PD5/TP0/TP0BPD5 PDPU

PDS� ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

TP0 PDS� — CMOS TM0 o�tp�tTP0B PDS� — CMOS TM0 inverted o�tp�t

PD6/SCK/SCL




PD�/SCSPD� PDPU

PDS3 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

SCS PDS3IFS4 ST CMOS SPI slave select

PE0/SCS�/INT0

PE0 PEPUPES0 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

SCS� PES0IFS5 ST CMOS SPI� slave select

INT0INTEGINTC0IFS0


Rev. 1.40 16 ��st �� 01� Rev. 1.40 1� ��st �� 01�



PE1/SCK�/INT1


SCK� PES0IFS5 ST CMOS SPI� serial clock

INT1INTEGINTC0IFS0


PE�/SDI�/INT�

PE� PEPUPES1 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

SDI� IFS5 ST CMOS SPI serial clock

INT�INTEGINTC3IFS0

ST — External Interr�pt �

PE3/SDO�/TCK3PE� PEPU

PES1 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

SDO� PES1 ST CMOS SPI� serial clockTCK3 IFS1 ST — TM3 inp�t

PE4/TP1B/TP1BB/TP1IB

PE4 PEPUPES� ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

TP1B PES� — CMOS TM1 B o�tp�tTP1BB PES� — CMOS TM1 inverted B o�tp�tTP1IB IFS� ST — TM1 B inp�t

PE5/TP3/TP3BPE5 PEPU

PES� ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

TP3 PES� — CMOS TM3 o�tp�tTP3B PES� — CMOS TM3 inverted o�tp�t

PE6/�N�/INT0


�N� PES3 �N — �/D Converter analo� inp�t

INT0INTEGINTC0IFS0


PE�/�N9/INT1

PE� PEPUPES3 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

�N9 PES3 �N — �/D Converter analo� inp�t

INT1INTEGINTC0IFS0


PF0/�N10/C1NPF0 PFPU

PFS0 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

�N10 PFS0 �N — �/D Converter analo� inp�tC1N PFS0 �N — Comparator 1 intertin� inp�t

PF1/�N11/C1PPF1 PFPU

PFS0 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

�N11 PFS0 �N — �/D Converter analo� inp�tC1P PFS0 �N — Comparator 1 non-intertin� inp�t

PF�~PF6 PFn PFPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

PG0/C0XPG0 PGPU

PGS0 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

C0X PGS0 — CMOS Comparator 0 o�tp�t

PG1/C1XPG1 PGPU

PGS0 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

C1X PGS0 — CMOS Comparator 1 o�tp�t

Rev. 1.40 16 ��st �� 01� Rev. 1.40 1� ��st �� 01�



PG�/TCK4PG� PGPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�pTCK4 — ST — TM4 inp�t

PG3/TP4/ TP4B/TP4I

PG3 PGPUPGS1 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

TP4 PGS1 — CMOS TM4 o�tp�tTP4B PGS1 — CMOS TM4 inverted o�tp�tTP4I IFS3 ST — TM4 inp�t

PG4/TP4/ TP4B/TP4I

PG4 PGPUPGS� ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

TP4 PGS� — CMOS TM4 o�tp�tTP4B PGS� — CMOS TM4 inverted o�tp�tTP4I IFS3 ST — TM4 inp�t

PG5/TCK5PG5 PGPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�pTCK5 — ST — TM5 inp�t

PG6/TP5/ TP5B/TP5I

PG6 PGPUPGS3 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p


PG�/TP5/ TP5B/TP5I

PG� PGPUPGS3 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p


PH0/TP0/TP0B/�N0/VREF/C0X

PH0 PHPUPHS0 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

TP0 PHS0 — CMOS TM0 o�tp�tTP0B PHS0 — CMOS TM0 inverted o�tp�t�N0 PHS0 �N — �/D Converter analo� inp�t

VREF PHS0 �N — �/D Converter reference inp�tC0X PHS0 — CMOS Comparator 0 o�tp�t

PH1/TCK0/ �N�/C0P

PH0 PHPUPHS0 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

TCK0 IFS1 ST — TM0 inp�t�N� PHS0 �N — �/D Converter analo� inp�tC0P PHS0 �N — Comparator 0 non-invertin� inp�t

PH�/SCS�PH� PHPU

PHS1 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

SCS� PHS1IFS5 ST CMOS SPI� slave select

PH3/SCK�PH3 PHPU

PHS1 ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

SCK� PHS1IFS5 ST CMOS SPI� serial clock

PH4/SDI�PH4 PHPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�pSDI� IFS5 ST CMOS SPI� serial data inp�t

PH5/SDO�PH5 PHPU

PHS� ST CMOS General p�rpose I/O. Re�ister enabled p�ll-�p

SDO� PHS� ST CMOS SPI� serial data o�tp�tVDD VDD — PWR — Positive Power s�pplyVSS VSS — PWR — Ne�ative Power s�pply. Gro�nd

Rev. 1.40 1� ��st �� 01� Rev. 1.40 19 ��st �� 01�


Pad Name Function OPT I/T O/T DescriptionVSS� VSS� — PWR — I/O Pad Power s�pply. Gro�nd

Note:I/T:Inputtype; O/T:OutputtypeOPT:Optionalbyconfigurationoption(CO)orregisteroptionPWR:Power; CO:ConfigurationoptionST:SchmittTriggerinput;CMOS:CMOSoutput; NMOS:NMOSoutputHXT:HighfrequencycrystaloscillatorLXT:Lowfrequencycrystaloscillator

Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOHTotal....................................................................................................................................-80mAIOLTotal..................................................................................................................................... 80mATotalPowerDissipation........................................................................................................ 500mW

Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

D.C. CharacteristicsTa=�5°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD1 Operatin� Volta�e (HXT) —fSYS=�MHz �.� — 5.5 VfSYS=1�MHz �.� — 5.5 VfSYS=16MHz 4.5 — 5.5 V

VDD� Operatin� Volta�e (ERC) —fSYS=6MHz �.� — 5.5 VfSYS=�MHz �.� — 5.5 VfSYS=1�MHz 4.5 — 5.5 V

VDD3 Operatin� Volta�e (HIRC) — fSYS=4/� MHz �.� — 5.5 V

IDD1

Operatin� C�rrent (HXT� fSYS=fH� fS=fSUB=fRTC or fLIRC)

3V No load� fH=�MHz� �DC off� WDT enable

— 1.0 1.5 m�5V — �.5 4.0 m�3V No load� fH=10MHz� �DC off�

WDT enable— 1.� �.0 m�

5V — �.� 4.5 m�3V No load� fH=1�MHz� �DC off�

WDT enable— 1.5 �.5 m�

5V — 3.5 5.5 m�

5V No load� fH=16MHz� �DC off� WDT enable — 4.5 �.0 m�

Rev. 1.40 1� ��st �� 01� Rev. 1.40 19 ��st �� 01�




IDD�

Operatin� C�rrent (ERC� fSYS=fH� fS=fSUB=fRTC or fLIRC)

3V No load� fH=6MHz� �DC off� WDT enable

— 0.9 1.5 m�5V — �.0 3.0 m�3V No load� fH=�MHz� �DC off�


5V — �.� 4.5 m�

5V No load� fH=1�MHz� �DC off� WDT enable — 4.0 6.0 m�

IDD3

Operatin� C�rrent (HIRC OSC� fSYS=fH� fS=fSUB=fRTC or fLIRC)

3V No load� fH=4MHz� �DC off� WDT enable

— 0.� 1.� m�5V — 1.5 �.5 m�3V No load� fH=�MHz� �DC off�


5V — �.� 4.5 m�

IDD4

Operatin� C�rrent (HXT� fSYS=fL� fS=fSUB=fRTC or fLIRC)

3V No load� fH=1�MHz� fL=fH/��DC off� WDT enable

— 0.9 1.5 m�5V — �.1 3.3 m�3V No load� fH=1�MHz� fL=fH/4�

�DC off� WDT enable— 0.6 1.0 m�

5V — 1.6 �.5 m�3V No load� fH=1�MHz� fL=fH/��

�DC off� WDT enable— 0.4� 0.� m�

5V — 1.� �.0 m�3V No load� fH=1�MHz� fL=fH/16�

�DC off� WDT enable— 0.4� 0.� m�

5V — 1.1 1.� m�3V No load� fH=1�MHz� fL=fH/3��

�DC off� WDT enable— 0.3� 0.6 m�

5V — 1.0 1.5 m�3V No load� fH=1�MHz� fL=fH/64�

�DC off� WDT enable— 0.36 0.55 m�

5V — 1.0 1.5 m�

IDD5

Operatin� C�rrent (LXT� fSYS=fL=fRTC� fS=fSUB=fRTC)

3V No load� �DC off� WDT enable� LXTLP=0� LVD&LVR disable

— 10 �0 μA5V — 30 50 μA3V No load� �DC off� WDT enable�

LXTLP=1� LVD & LVR disable— 10 �0 μA

5V — 30 50 μA

IDD6

Operatin� C�rrent (LIRC� fSYS=fL=fLIRC� fS=fSUB=fLIRC)

3V No load� �DC off� WDT enable�LVD&LVR disable

— 10 �0 μA

5V — 30 50 μA

ISTB1

Standby C�rrent (IDLE1) (HXT� fSYS=fH� fS=fSUB=fRTC or fLIRC)

3V No load� system H�LT� �DC off�WDT enable� fSYS=1�MHz

— 0.6 1.0 m�

5V — 1.� �.0 m�

ISTB�

Standby C�rrent (IDLE0) (HXT� fSYS=off� fS=fSUB=fRTC or fLIRC)


— 1.3 3.0 μA

5V — �.� 5.0 μA

ISTB3Standby C�rrent (IDLE0) (ERC� fSYS=off� fS=fSUB=fRTC)


— 1.3 3.0 μA5V — �.� 5.0 μA

ISTB4

Standby C�rrent (IDLE0) (HIRC� fSYS=off� fS=fSUB=fLIRC)

3V No load� system H�LT� �DC off�WDT enable� fSYS=�MHz

— 1.3 3.0 μA

5V — �.� 5.0 μA

ISTB5

Standby C�rrent (IDLE1) (HXT� fSYS=fL� fS=fSUB=fRTC or fLIRC)

3V No load� system H�LT� �DC off�WDT enable� fSYS=1�MHz/64

— 0.34 0.6 m�

5V — 0.�5 1.� m�

ISTB6

Standby C�rrent (IDLE0) (HXT� fSYS=off� fS=fSUB=fRTC or fLIRC)

3V No load� system H�LT� �DC off�WDT enable� fSYS=1�MHz/64

— 1.3 3.0 μA

5V — �.� 5.0 μA

ISTB�

Standby C�rrent (IDLE1) (LXT� fSYS=fL=fRTC� fS=fSUB=fRTC)

3V No load� system H�LT� �DC off�WDT enable� fSYS=3��6�Hz� LXTLP=1

— 1.9 4.0 μA

5V — 3.3 �.0 μA

Rev. 1.40 �0 ��st �� 01� Rev. 1.40 �1 ��st �� 01�




ISTB�Standby C�rrent (IDLE0) (LXT� fSYS=off� fS=fSUB=fRTC)

3V No load� system H�LT� �DC off�WDT enable� fSYS=3��6�Hz� LXTLP=1

─ 1.3 3.0 μA

5V — �.� 5.0 μA

ISTB9Standby C�rrent (IDLE0) (LIRC� fSYS=off� fS=fSUB=fLIRC)

3V No load� system H�LT� �DC off�WDT enable� fSYS=3�kHz

— 1.3 3.0 μA5V — �.� 5.0 μA

ISTB10

Standby C�rrent (SLEEP0) (HXT� fSYS=off� fS=fSUB=fRTC or fLIRC)

3V No load� system H�LT� �DC off�WDT disable� fSYS=1�MHz

— 0.1 1 μA

5V — 0.3 � μA

ISTB11Standby C�rrent (SLEEP1) (HXT� fSYS=off� fS=fSUB=fRTC)


— 1.3 5.0 μA5V — �.� 10.0 μA

ISTB1�Standby C�rrent (SLEEP1) (HXT� fSYS=off� fS=fSUB=fLIRC)


— 1.3 5.0 μA5V — �.� 10.0 μA

ISTB13

Standby C�rrent (SLEEP0) (LXT� fSYS=off� fS=fSUB=fLIRC or fRTC)

3V No load� system H�LT� �DC off�WDT disable� fSYS=3��6�Hz

— 0.1 1 μA

5V — 0.3 � μA

ISTB14Standby C�rrent (SLEEP1) (LXT� fSYS=off� fS=fSUB=fRTC)

3V No load� system H�LT� �DC off�WDT enable� fSYS=3��6�Hz

— 1.3 5.0 μA5V — �.� 10.0 μA

ISTB15

Stanby C�rrent (SLEEP) (HXT� fSYS=off� fS=fSUB=fRTC or fLIRC)

—No load� system H�LT� �DC off�WDT disable� fSYS=1�MHz�LVR enable and LVDEN=1

— 60 90 μA

VIL1Inp�t Low Volta�e for I/O port except RES pin

5—

0 — 1.5 V— 0 — 0.�VDD V

VIH1Inp�t Hi�h Volta�e for I/O port except RES pin

5—

3.5 — 5 V— 0.�VDD — VDD V

VIL� Inp�t Low Volta�e (RES) — — 0 — 0.4VDD VVIH� Inp�t Hi�h Volta�e (RES) — — 0.9VDD — VDD V

VSCOMVDD/� volta�e for LCD COMn �.5V~5.5V No load 0.4�5 0.500 0.5�5 VDD

IOL I/O Port Sink C�rrent3V VOL=0.1VDD 4 � — m�5V VOL=0.1VDD 10 �0 — m�

IOH I/O Port So�rce C�rrent3V VOH=0.9VDD -� -4 — m�5V VOH=0.9VDD -5 -10 — m�

RPHP�ll-hi�h Resistance of I/O Ports

3V — �0 60 100 kΩ5V — 10 30 50 kΩ

Rev. 1.40 �0 ��st �� 01� Rev. 1.40 �1 ��st �� 01�


A.C. CharacteristicsTa=�5°C


Min. Typ. Max. UnitVDD Condition

fSYS1 System clock (HXT) —�.�~5.5V 0.4 — � MHz�.�~5.5V 0.4 — 1� MHz4.5~5.5V 0.4 — 16 MHz

fSYS� System clock (ERC) 5V Ta=�5°C� External RERC=1�0kΩ -�% � +�% MHzfSYS3 System clock (HIRC) 5V Ta=�5°C -�% � +�% MHzfSYS4 System Clock (LXT) — — — 3��6� — HzfSYS5 System Clock (LIRC) 5V Ta=�5°C -3% 3� +3% kHz

tTIMERTCKn and timer capt�re Inp�t P�lse Width — — 0.3 — — μs

tRES External Reset Low P�lse Width — — 10 — — μstINT Interr�pt P�lse Width — — 10 — — μs

tSST

System Start-�p Timer Period (Wake-�p from H�LT� fSYS off at H�LT state� Slow Mode →Normal Mode� Normal Mode → Slow Mode)

—

fSYS=HXT or LXT(Slow Mode→Normal Mode(HXT)� Normal Mode→Slow Mode(LXT))

10�4 — — tSYS

fSYS=HXT or LXT(Wake-�p from H�LT� fSYS off at H�LT state)

10�4 — — tSYS

— fSYS=ERC or HIRC 16 — — tSYS

— fSYS=LIRC � — — tSYS

System Start-�p Timer Period(Wake-�p from H�LT� fSYS on at H�LT state)

— — � — — tSYS

System Start-�p Timer Period (Reset) — — 10�4 — — tSYS

tRSTD

System Reset Delay Time(Power On Reset� LVR reset� LVRC software reset� WDTC software reset)

— — �5 50 100 ms

System Reset Delay Time(RES reset� WDT normal reset) — — �.3 16.� 33.3 ms

tEERD EEPROM Read Time — — 1 � 4 tSYS

tEEWR EEPROM Write Timet — — 1 � 4 ms

Note: tSYS=1/fSYS

Rev. 1.40 22 August 28, 2017 Rev. 1.40 23 August 28, 2017


A/D Converter Electrical CharacteristicsTa=25˚C



AVDD A/D Converter Operating Voltage — — 2.2 — 5.5 VVADI A/D Converter Input Voltage — — 0 — VREF VVREF A/D Converter Reference Voltage — — 2 — AVDD V

DNL Differential non-linearity2.2V~2.7V VREF=AVDD=VDD, tADCK=8μs — ±15 — LSB2.7V~5.5V VREF=AVDD=VDD, tADCK=0.5μs -3 — +3 LSB

INL Integral non-linearity2.2V~2.7V VREF=AVDD=VDD, tADCK=8μs — ±16 — LSB2.7V~5.5V VREF=AVDD=VDD, tADCK=0.5μs -4 — +4 LSB

IADCAdditional Power Consumption if A/D Converter is used

3V No load (tADCK=0.5μs ) — 1.0 2.0 mA5V No load (tADCK=0.5μs ) — 1.5 3.0 mA

tADCK A/D Converter Clock Period2.2V~2.7V — 8.0 — 10 μs2.7V~5.5V — 0.5 — 10 μs

tADCA/D Conversion Time (Include Sample and Hold Time) — 12-bit A/D converter — 16 — tADCK

tADS A/D Converter Sampling Time — — — 4 — tADCK

tON2ST A/D Converter On-to-Start Time — — 2 — — μs

LVD & LVR Electrical CharacteristicsTa=25°C



VLVR1

Low Voltage Reset Voltage —

LVR Enable, 2.1V option

-5%

2.1

+5% VVLVR2 LVR Enable, 2.55V option 2.55VLVR3 LVR Enable, 3.15V option 3.15VLVR4 LVR Enable, 3.8V option 3.8VLVD1

Low Voltage Detector Voltage —

LVDEN=1, VLVD=2.0V

-5%

2.0

+5%

VVLVD2 LVDEN=1, VLVD=2.2V 2.2 VVLVD3 LVDEN=1, VLVD=2.4V 2.4 VVLVD4 LVDEN=1, VLVD=2.7V 2.7 VVLVD5 LVDEN=1, VLVD=3.0V 3.0 VVLVD6 LVDEN=1, VLVD=3.3V 3.3 VVLVD7 LVDEN=1, VLVD=3.6V 3.6 VVLVD8 LVDEN=1, VLVD=4.0V 4.0 VVBG Bandgap reference with buffer voltage — — -3% 1.25 +3% V

IBGAdditional Power Consumption if bandgap reference with buffer is used ─ ─ — 200 300 μA

ILVR Additional Power Consumption if LVR is used3V

LVR disable→LVR enable— 30 45 μA

5V — 60 90 μA

ILVD Additional Power Consumption if LVD is used

3V LVD disable→LVD enable(LVR disable)

— 40 60 μA5V — 75 115 μA3V LVD disable→LVD enable

(LVR enable)— 30 45 μA

5V — 60 90 μAtBGS VBG turn on stable time ─ ─ 10 ─ ─ mstLVR Low Voltage Width to Reset — — 120 — 480 μstLVD Low Voltage Width to Interrupt — — 20 45 90 μs

Rev. 1.40 �� st �� 01� Rev. 1.40 �3 ��st �� 01�




tLVDS LVDO stable time— For LVR enable, LVD off→on 15 — — μs— For LVR disable, LVD off→on 15 — — μs

tSRESET Software Reset Width to Reset — — 45 90 1�0 μs

Comparator Electrical CharacteristicsTa=25˚C



VCMP Comparator operatin� volta�e — — �.� — 5.5 V

ICMP Comparator operatin� c�rrent 3V — — 50 �5 μA5V — — �5 130 μA

VCMPOS Comparator inp�t offset volta�e — — -10 — +10 mVVHYS Hysteresis width — �0 40 60 mVVCM Comparator common mode volta�e ran�e — — VSS — VDD-1.4V V�OL Comparator open loop �ain — — 60 �0 — dB

tPD Comparator response time3V

With 100mV overdrive(Note) — �00 400 ns5V

Note:MeasuredwithcomparatoroneinputpinatVCM=(VDD-1.4)/2whiletheotherpininputtransitionfromVSSto(VCM+100mV)orfromVDDto(VCM-100mV).

Power on Reset Electrical Characteristics Ta=25˚C



VPOR VDD Start Volta�e to ens�re Power-on Reset — — — — 100 mVRRVDD VDD Rise Rate to ens�re Power-on Reset — — 0.035 — — V/ms

tPORMinim�m Time for VDD to remain at VPOR to ens�re Power-on Reset — — 1 — — ms

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Rev. 1.40 �4 ��st �� 01� Rev. 1.40 �5 ��st �� 01�


System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.TherangeofdevicestakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningscheme is implemented insuchaway that instruction fetchingand instructionexecutionareoverlapped,hence instructionsareeffectivelyexecuted inonecycle,with theexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitectural featuresensure thataminimumofexternalcomponents is required toprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthesedevicessuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derived fromeitheraHXT,LXT,HIRC,LIRCorERCoscillator issubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsareeffectivelyexecutedinoneinstructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

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System Clocking and Pipelining

Rev. 1.40 �4 ��st �� 01� Rev. 1.40 �5 ��st �� 01�


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Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionis executed except for instructions, such as “JMP” or “CALL” that demand a jump to anon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

DeviceProgram Counter

Porgram Counter High Byte Porgram Counter Low ByteHT66F60� PC13~PC�

PCL�~PCL0HT66F�0� PC14~PC�

Program Counter

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly;however,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

Rev. 1.40 �6 ��st �� 01� Rev. 1.40 �� st �� 01�


StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackhasmultiple levelsandisneitherpartof thedatanorpartof theprogramspace,andisneitherreadablenorwriteable.Theactivatedlevel is indexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.

Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

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Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA,LADD,LADDM,LADC,LADCM,LSUB,LSUBM,LSBC,LSBCM,LDAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA,LAND,LOR,LXOR,LANDM,LORM,LXORM,LCPL,LCPLA

• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC,LRRA,LRR,LRRCA,LRRC,LRLA,LRL,LRLCA,LRLC

• IncrementandDecrement:INCA,INC,DECA,DEC,LINCA,LINC,LDECA,LDEC

• Branchdecision:JMP,CALL,RET,RETI,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,LSZ,LSZA,LSNZ,LSIZ,LSDZ,LSIZA,LSDZA

Rev. 1.40 �6 ��st �� 01� Rev. 1.40 �� st �� 01�


Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthesedevicesseriestheProgramMemoryareFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberof times,allowing theuser theconvenienceofcodemodificationon thesamedevice.Byusingtheappropriateprogrammingtools,theseFlashdevicesofferuserstheflexibilitytoconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof16K×16bits to32K×16bits.TheProgramMemory isaddressedbytheProgramCounterandalsocontainsdata, tableinformationandinterruptentriesinformation.Tabledata,whichcanbe setup inany locationwithin theProgramMemory, isaddressedbyseparatetablepointerregisters.

Device Capacity BanksHT66F60� 16K × 16 0~1HT66F�0� 3�K × 16 0~3

TheseriesofdeviceshasitsProgramMemorydividedintotwoorfourBanks,Bank0~Bank1orBank0~Bank3respectively.TherequiredBankisselectedusingBit0orBit0~1oftheBPRegisterdependentuponwhichdeviceisselected.

0000H

0004H

003�H

Reset

Interr�pt Vector

16 bits

HT66F60�

1FFFH

Bank 1�000H

3FFFH

Reset

Interr�pt Vector

16 bits

HT66F�0�

Bank 1

Bank �

Bank 3

4000H

5FFFH6000H

�FFFH

Program Memory Structure

Rev. 1.40 �� st �� 01� Rev. 1.40 �9 ��st �� 01�


Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation0000Hisreservedforusebythesedevicesresetforprograminitialisation.Afteradeviceresetisinitiated,theprogramwilljumptothislocationandbeginexecution.

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe“TABRD[m]”or“TABRDL[m]” instructions respectivelywhen thememory[m] is locatedincurrentpage.If thememory[m]is locatedinotherpages, thedatacanberetrievedfromtheprogrammemoryusingthe“LTABRD[m]”or“LTABRDL[m]”instructionsrespectively.Whentheinstructionisexecuted,thelowerordertablebytefromtheProgramMemorywillbetransferredtotheuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

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Rev. 1.40 �� st �� 01� Rev. 1.40 �9 ��st �� 01�


Table Program ExampleTheaccompanyingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthedevice.ThisexampleusesrawtabledatalocatedinthelastpagewhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“3F00H”whichreferstothestartaddressofthelastpagewithinthe16KProgramMemoryoftheHT66F60Adevice.Thetablepointerissetupheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“3F06H”or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthepresentpageifthe“TABRD[m]”instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRD[m]instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Example: tempreg1 db ? ; temporary register #1 in current pagetempreg2 db ? ; temporary register #2 in current page : :mov a,06h ; initialise low byte table pointer - note that this address ; is referencedmov tblp, a ; to the last page or present page : :tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempreg1 ; Data at program memory address “3F06H” transferred to tempreg1 ; and TBLHdec tblp ; reduce value of table pointer by onetabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; Data at program memory address “3F05H” transferred to tempreg2 ; and TBLH. In this example the data “1AH” is transferred to ; tempreg1 and data “0FH” to register tempreg2 while the value “00H” ; will be transferred to the high byte register TBLH : :org 3F00h ; sets initial address of last page

dc 000Ah, 000Bh, 000Ch, 000Dh, 000Eh, 000Fh, 001Ah, 001Bh : :

Rev. 1.40 30 ��st �� 01� Rev. 1.40 31 ��st �� 01�


In Circuit Programming – ICPTheprovisionofFlashtypeProgramMemoryprovides theuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.

Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,and thenprogrammingorupgradingtheprogramatalaterstage.Thisenablesproductmanufacturerstoeasilykeeptheirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

Holtek Writer Pins MCU Programming Pins Pin DescriptionICPD� P�0 Pro�rammin� Serial DataICPCK P�� Pro�rammin� ClockVDD VDD Power S�pplyVSS VSS Gro�nd

TheProgramMemorycanbeprogrammedserially in-circuitusing this4-wire interface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditional linefor theclock.Twoadditionallinesarerequiredforthepowersupplyandonelineforthereset.Thetechnicaldetailsregardingthein-circuitprogrammingofthedevicesarebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

Duringtheprogrammingprocess,theusermusttakecareoftheICPDAandICPCKpinsfordataandclockprogrammingpurposestoensurethatnootheroutputsareconnectedtothesetwopins.

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Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1korthecapacitanceof*mustbelessthan1nF.

Rev. 1.40 30 ��st �� 01� Rev. 1.40 31 ��st �� 01�


On-Chip Debug Support – OCDSThereisanEVchipnamedHT66V70AwhichisusedtoemulatetheHT66Fx0Aseriesofdevices.TheHT66V70Adevicealsoprovides the“On-ChipDebug”function todebug theHT66Fx0Aseriesofdevicesduringdevelopmentprocess.Thedevices,HT66Fx0AandHT66V70A,arealmostfunctionalcompatibleexcept the“On-ChipDebug”functionandpackage types.UserscanusetheHT66V70Adevice toemulate theHT66Fx0Aseriesofdevicesbehaviorsbyconnecting theOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApinistheOCDSData/Addressinput/outputpinwhiletheOCDSCKpinistheOCDSclockinputpin.Whenusersuse theHT66V70AEVchipfordebugging, thecorrespondingpin functionssharedwiththeOCDSDAandOCDSCKpins in theHT66Fx0Aseriesofdeviceswillhavenoeffect in theHT66V70AEVchip.However,thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedas theFlashMemoryprogrammingpins for ICP.FormoredetailedOCDSinformation, refer to thecorrespondingdocumentnamed“Holteke-Linkfor8-bitMCUOCDSUser’sGuide”.

Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSD� OCDSD� On-Chip Deb�� S�pport Data/�ddress inp�t/o�tp�tOCDSCK OCDSCK On-Chip Deb�� S�pport Clock inp�t

VDD VDD Power S�pplyGND VSS Gro�nd

In Application Programming – IAPThisdeviceoffersIAPfunctiontoupdatedataorapplicationprogramtoflashROM.UserscandefineanyROMlocationforIAP,buttherearesomefeatureswhichusermustnoticeinusingIAPfunction.

• Erasepage:64words/page

• Writing:64words/time

• Reading:1word/time

In Application Programming Control RegisterTheAddress register,FARLandFARH,and theData registers,FD0L/FD0H,FD1L/FD1H,FD2L/FD2HandFD3L/FD3H, located inDataMemory section0, togetherwith theControlregistersr,FC0,FC1andFC2,locatedinDataMemorysection1arethecorrespondingFlashaccessregistersforIAP.AsindirectaddressingistheonlywaytoaccesstheFC0,FC1andFC2registers,all readandwriteoperations to the registersmustbeperformedusing the IndirectAddressingRegister,IAR1,andtheMemoryPointerpair,MP1LandMP1H.BecausetheFC0,FC1andFC2controlregistersarelocatedattheaddressof43H~45HinDataMemorysection1,thedesiredvaluerangedfrom43Hto45HmustfirstbewrittenintotheMP1LMemoryPointerlowbyteandthevalue“01H”mustalsobewrittenintotheMP1HMemoryPointerhighbyte.

Rev. 1.40 3� ��st �� 01� Rev. 1.40 33 ��st �� 01�


• FC0 Register

Bit 7 6 5 4 3 2 1 0Name CFWEN FMOD� FMOD1 FMOD0 FWPEN FWT FRDEN FRDR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 1 1 0 0 0 0

Bit7 CFWEN:FlashMemoryWriteenablecontrol0:Flashmemorywritefunctionisdisabled1:Flashmemorywritefunctionhasbeensuccessfullyenabled

Whenthisbitisclearedto0byapplicationprogram,theFlashmemorywritefunctionisdisabled.Notethatwritinga“1”intothisbitresults innoaction.Thisbit isusedtoindicatethattheFlashmemorywritefunctionstatus.Whenthisbit isset to1byhardware, itmeans that theFlashmemorywrite function isenabledsuccessfully.Otherwise,theFlashmemorywritefunctionisdisabledasthebitcontentiszero.

Bit6~4 FMOD2~FMOD0:Modeselection000:Writeprogrammemory001:Pageeraseprogrammemory010:Reserved011:Readprogrammemory101:Reserved110:FWENmode–FlashmemoryWritefunctionEnablemode111:Reserved

Bit3 FWPEN:Flashmemorywriteprocedureenablecontrol0:Disable1:Enable

Whenthisbitissetto1andtheFMODfieldissetto“110”,theIAPcontrollerwillexecutethe“Flashmemorywritefunctionenable”procedure.OncetheFlashmemorywritefunctionissuccessfullyenabled, it isnotnecessarytoset theFWPENbitanymore.

Bit2 FWT:FlashROMwritecontrolbit0:DonotinitiateFlashmemorywriteorFlashmemoryWriteprocessiscompleted1:InitiateFlashmemorywriteprocess

Thisbit issetbysoftwareandclearedbyhardwarewhentheFlashmemorywriteprocessiscompleted.

Bit1 FRDEN:Flashmemoryreadenablebit0:Flashmemoryreaddisable1:Flashmemoryreadenable

Bit0 FRD:Flashmemoryreadcontrolbit0:DonotinitiateFlashmemoryreadorFlashmemoryreadprocessiscompleted1:InitiateFlashmemoryreadprocess

Thisbit issetbysoftwareandclearedbyhardwarewhen theFlashmemoryreadprocessiscompleted.

Rev. 1.40 3� ��st �� 01� Rev. 1.40 33 ��st �� 01�


• FC1 Register

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D� D1 D0R/W R R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 55H:wholechipresetWhenuserwrites55Htothisregister, itwillgeneratearesetsignal toresetwholechip.

• FC2 Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — — CLWBR/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas“0”Bit0 CLWB:FlashMemoryWritebufferclearcontrol

0:DonotinitiateWirteBufferClearorWirteBufferClearprocessiscompleted1:InitiateWirteBufferClearprocess

Thisbit is setbysoftwareandclearedbyhardwarewhen theWirteBufferClearprocessiscompleted.

• FARL Register

Bit 7 6 5 4 3 2 1 0Name �� 6 �5 �4 �3 �� 1 �0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 FlashMemoryAddress[7:0]

• FARH Register

Bit 7 6 5 4 3 2 1 0Name — �14 �13 �1� �11 �10 �9 ��R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6~0 FlashMemoryAddress[14:8]

• FD0L Register

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 ThefirstFlashMemorydata[7:0]

• FD0H Register

Bit 7 6 5 4 3 2 1 0Name D15 D14 D13 D1� D11 D10 D9 D�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 ThefirstFlashMemorydata[15:8]

Rev. 1.40 34 ��st �� 01� Rev. 1.40 35 ��st �� 01�


• FD1L Register


Bit7~0 ThesecondFlashMemorydata[7:0]

• FD1H Register


Bit7~0 ThesecondFlashMemorydata[15:8]

• FD2L Register


Bit7~0 ThethirdFlashMemorydata[7:0]

• FD2H Register


Bit7~0 ThethirdFlashMemorydata[15:8]

• FD3L Register


Bit7~0 ThefourthFlashMemorydata[7:0]

• FD3H Register


Bit7~0 ThefourthFlashMemorydata[15:8]

Rev. 1.40 34 ��st �� 01� Rev. 1.40 35 ��st �� 01�


Flash Memory Write Function Enable ProcedureInordertoallowuserstochangetheFlashmemorydatathroughtheIAPcontrolregisters,usersmustfirstenabletheFlashmemorywriteoperationbythefollowingprocedurce:

• Write“110”intotheFMOD2~FMOD0bitstoselecttheFWENmode.

• SettheFWPENbitto“1”.Thestep1andstep2canbeexecutedsimultaneously.

• Thepatterndatawithasequenceof00H,04H,0DH,09H,C3Hand40HmustbewrittenintotheFD1L,FD1H,FD2L,FD2H,FD3LandFD3Hregistersrespectively.

• Acounterwithatime-outperiodof300μswillbeactivatedtoallowuserswritingthecorrectpatterndataintotheFD1L/FD1H~FD3L/FD3Hregisterpairs.ThecounterclockisderivedfromLIRCoscillator.

• If thecounteroverflowsorthepatterndataisincorrect, theFlashmemorywriteoperationwillnotbeenabledandusersmustagainrepeat theaboveprocedure.Then theFWPENbitwillautomaticallybeclearedto0byhardware.

• Ifthepatterndataiscorrectbeforethecounteroverflows,theFlashmemorywriteoperationwillbeenabledandtheFPWENbitwillautomaticallybeclearedto0byhardware.TheCFWENbitwillalsobesetto1byhardwaretoindicatethattheFlashmemorywriteoperationissuccessfullyenabled.

• OncetheFlashmemorywriteoperation isenabled, theusercanchangetheFlashROMdatathroughtheFlashcontrolregister.

• TodisabletheFlashmermoywriteoperation,theusercancleartheCFWENbitto0.

Flash MemoryWrite F�nction

Enable Proced�re

Set FMOD [�:0] =110 & FWPEN=1→Select FWEN mode & Start Flash write

Hardware activate a co�nter

Wrtie the followin� pattern to Flash Data re�istersFD1L= 00h � FD1H = 04hFD�L= 0Dh � FD�H = 09hFD3L= C3h � FD3H = 40h

Is pattern iscorrect ?

Is co�nteroverflow ?

FWPEN=0 ?

yes

no

no

yes

S�ccess

END

no

yes

Failed

FWPEN=0&

CFWEN=0

CFWEN = 1

Flash Memory Write Function Enable Procedure

Rev. 1.40 36 ��st �� 01� Rev. 1.40 3� ��st �� 01�


WriteFlash Memory

Flash MemoryWrite F�nction

Enable Proced�re

Set FWT=1

FWT=0 ?

yes

no

Set Pa�e Erase address: F�RH/F�RLSet FMOD [�:0]=001 & FWT=1→ Select “Pa�e Erase mode”

& Initiate write operation

FWT=0 ?

yes

no

END

Write Finish ?

yes

no

Clear CFWEN=0

Set FMOD [�:0]=000→ Select “Write Flash Mode”

Set Pa�e Erase address: F�RH/F�RLWrite data to data re�ister: FD0L/FD0H

Pa�e datawrite finish ?

yes

no

Write Flash Memory Procedure

Rev. 1.40 36 ��st �� 01� Rev. 1.40 3� ��st �� 01�


ERASE PAGE FARH FARL[7:6] Note0 0000 0000 00

F�RL [5:0]: don’t care

1 0000 0000 01� 0000 0000 103 0000 0000 114 0000 0001 005 0000 0001 016 0000 0001 10� 0000 0001 11� 0000 0010 009 0000 0010 01::

::

::

�5� 0011 1111 00�53 0011 1111 01�54 0011 1111 10�55 0011 1111 11

::

::

::

50� 0111 1111 00509 0111 1111 01510 0111 1111 10511 0111 1111 11

Note: Thereare256IAPerasepagesintheHT66F60Adevicewhilethereare512IAPerasepagesintheHT66F70Adevice.

Rev. 1.40 3� ��st �� 01� Rev. 1.40 39 ��st �� 01�


ReadFlash Memory

Clear FWEN bit

END

Read Finish ?

yes

no

Set FMOD [�:0]=011& FRDEN=1

Set Flash �ddress re�istersF�H=xxh� F�L=xxh

FRD=0 ?

yes

no

Read data val�e: FD0L=xxh� FD0H=xxh

Set FRD=1

Read Flash Memory Procedure

Note:WhentheFWTorFRDbitissetto1,theMCUisstopped.

Rev. 1.40 3� ��st �� 01� Rev. 1.40 39 ��st �� 01�


Data MemoryTheDataMemoryisan8-bitwideRAMinternalmemoryandis the locationwhere temporaryinformationisstored.

Dividedintotwotypes,thefirstofDataMemoryisanareaofRAMwherespecialfunctionregistersare located.Theseregistershavefixed locationsandarenecessary forcorrectoperationof thedevice.Manyof theseregisterscanbereadfromandwritten todirectlyunderprogramcontrol,however, someremainprotected fromusermanipulation.ThesecondareaofDataMemory isreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

StructureTheDataMemory isdivided intoseveralsections,allofwhichare implemented in8-bitwideMemory.EachoftheDataMemorysectionsiscategorizedintotwotypes,theSpecialPurposeDataMemoryandtheGeneralPurposeDataMemory.

Thestartaddressof theSpecialPurposeDataMemoryforalldevices is theaddress00Hwhilethestartaddressof theGeneralPurposeDataMemoryis theaddress80H.Thespecialpurposeregisterswhichareaddressedfrom00Hto3FHinDataMemoryarecommontoallsectionsandareaccessibleinallsections.However,thespecialpurposeregisterslocatedinthesection1canonlybeaccessedwiththeaddressfrom40HtoFFH.

Device Capacity Sections

HT66F60� General P�rpose: 10�4×�

0: �0H~FFH1: �0H~FFH

::

�: �0H~FFH

HT66F�0� General P�rpose: �04�×�

0: �0H~FFH1: �0H~FFH

::

15: �0H~FFH

Rev. 1.40 40 ��st �� 01� Rev. 1.40 41 ��st �� 01�


Special P�rposeData Memory

General P�rposeData Memory

00H

�FH�0H

FFH

Section 0

40H in section 1

Section 0Section 1

Section �

Section N

�FH in section 1

N=� for HT66F60�; N=15 for HT66F�0�

Data Memory Structure

General Purpose Data MemoryAllmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.Byusingthebitoperationinstructions individualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.

Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue“00H”.

Rev. 1.40 40 ��st �� 01� Rev. 1.40 41 ��st �� 01�


00H I�R0

01H MP0

0�H I�R1

03H MP1L

04H

05H �CC

06H PCL

0�H TBLP

0�H TBLH

09H TBHP

0�H ST�TUS

0BH

SMOD

0CH

LVDC

0DH

INTEG

0EH

WDTC

0FH

TBC0

10H

INTC0

11H

INTC1

1�H

19H

P�PU

1�H

P�WU

1BH

1�H

1DH

1CH

1FH

P�

P�C

1EH

HT66F60� Special P�rpose Data Memory

BP

13H

14H

MFI0

15H

MFI1

16H

1�H

MFI�

Section 0~�

SMOD�

LVRC

Un�sed

PBPU

PB

PBC

PCPU

PC

PCC

PDPU

PD

PDC

PEPU

PE

PEC

PFPU

PF

PFC

PGPU

PG

PGC

PHPU

PH

PHC

�0H

�1H

��H

�9H

��H

�BH

��H

�DH

�CH

�FH

�EH

�3H

�4H

�5H

�6H

��H

30H

31H

3�H

39H

3�H

3BH

3�H

3DH

3CH

3FH

3EH

33H

34H

35H

36H

3�H

TM4C0

TM4C1

TM4DL

TM4DH

TM4�L

TM4�H

40H EEC

41H EE�

4�H EED

43H

TM�C0

4�H

TM�C1

4�H

TM1C�

49H

TM�DL

4�H

TM�DH

4BH

TM��L

4CH

TM��H

4DH

TM1BL

4EH

TM1BH

4FH

50H

51H

5�H

5�H

53H

54H

55H

56H

5�H

Section 0� �~� Section 1

Un�sed

TM1C0

TM1C1

TM1DL

TM1DH

TM1�L

TM1�H

TM�RP

60H

61H

MP1H

I�R�

MP�L

MP�H

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

INTC�

INTC3

MFI3

MFI4

SMOD1

44H

45H

46H

FC0

FC1

FC�

IFS0

IFS1

IFS�

IFS3

IFS4

IFS5

59H

5�H

5BH

5CH

5DH

5EH

5FH

TM3C0

TM3C1

TM3DL

TM3DH

TM3�L

TM3�H

TM0C0

TM0C1

TM0DL

TM0DH

TM0�L

TM0�H

6�H

63H

64H

65H

66H

6�H

6�H

69H

PSC0

TBC1

PSC1

�DCR0

�DCR1

6�H

6BH

6DH

6CH

6EH

6FH

�DRL

�DRH

SIMC0

SIMC1

SIMD

SIMC�/SIM�

CP1C

CP0C

I�CTOC

SPI�C0

SPI�C1

SPI�D

�0H

�1H

��H

�3H

�4H

�5H

�6H

��H

��H

�9H

��H

�BH

�DH

�CH

�EH

�FH

F�RL

F�RH

FD0L

FD0H

FD1L

FD1H

FD�L

FD�H

FD3L

FD3H

TBC�

SCOMC

TM4RP

TM5C0

TM5C1

TM5DL

TM5DH

TM5�L

TM5�H

TM5RP

P�S0

P�S1

P�S�

P�S3

PBS�

PBS3

PCS0

PCS1

PCS�

PCS3

PDS0

PDS1

PDS�

PDS3

PES0

PES1

PES�

PES3

PFS0

PGS0

PGS1

PGS�

PGS3

PHS0

PHS1

PHS�

: Un�sed� read as 00H

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

00H I�R0

01H MP0

0�H I�R1

03H MP1L

04H

05H �CC

06H PCL

0�H TBLP

0�H TBLH

09H TBHP

0�H ST�TUS

0BH

SMOD

0CH

LVDC

0DH

INTEG

0EH

WDTC

0FH

TBC0

10H

INTC0

11H

INTC1

1�H

19H

P�PU

1�H

P�WU

1BH

1�H

1DH

1CH

1FH

P�

P�C

1EH

HT66F�0� Special P�rpose Data Memory

BP

13H

14H

MFI0

15H

MFI1

16H

1�H

MFI�

Section 0~15

SMOD�

LVRC

Un�sed

PBPU

PB

PBC

PCPU

PC

PCC

PDPU

PD

PDC

PEPU

PE

PEC

PFPU

PF

PFC

PGPU

PG

PGC

PHPU

PH

PHC

�0H

�1H

��H

�9H

��H

�BH

��H

�DH

�CH

�FH

�EH

�3H

�4H

�5H

�6H

��H

30H

31H

3�H

39H

3�H

3BH

3�H

3DH

3CH

3FH

3EH

33H

34H

35H

36H

3�H

TM4C0

TM4C1

TM4DL

TM4DH

TM4�L

TM4�H

40H EEC

41H EE�

4�H EED

43H

TM�C0

4�H

TM�C1

4�H

TM1C�

49H

TM�DL

4�H

TM�DH

4BH

TM��L

4CH

TM��H

4DH

TM1BL

4EH

TM1BH

4FH

50H

51H

5�H

5�H

53H

54H

55H

56H

5�H

Section 0� �~15 Section 1

Un�sed

TM1C0

TM1C1

TM1DL

TM1DH

TM1�L

TM1�H

TM�RP

60H

61H

MP1H

I�R�

MP�L

MP�H

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

INTC�

INTC3

MFI3

MFI4

SMOD1

44H

45H

46H

FC0

FC1

FC�

IFS0

IFS1

IFS�

IFS3

IFS4

IFS5

59H

5�H

5BH

5CH

5DH

5EH

5FH

TM3C0

TM3C1

TM3DL

TM3DH

TM3�L

TM3�H

TM0C0

TM0C1

TM0DL

TM0DH

TM0�L

TM0�H

6�H

63H

64H

65H

66H

6�H

6�H

69H

PSC0

TBC1

PSC1

�DCR0

�DCR1

6�H

6BH

6DH

6CH

6EH

6FH

�DRL

�DRH

SIMC0

SIMC1

SIMD

SIMC�/SIM�

CP1C

CP0C

I�CTOC

SPI�C0

SPI�C1

SPI�D

�0H

�1H

��H

�3H

�4H

�5H

�6H

��H

��H

�9H

��H

�BH

�DH

�CH

�EH

�FH

F�RL

F�RH

FD0L

FD0H

FD1L

FD1H

FD�L

FD�H

FD3L

FD3H

TBC�

SCOMC

TM4RP

TM5C0

TM5C1

TM5DL

TM5DH

TM5�L

TM5�H

TM5RP

P�S0

P�S1

P�S�

P�S3

PBS�

PBS3

PCS0

PCS1

PCS�

PCS3

PDS0

PDS1

PDS�

PDS3

PES0

PES1

PES�

PES3

PFS0

PGS0

PGS1

PGS�

PGS3

PHS0

PHS1

PHS�

: Un�sed� read as 00H

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

Un�sed

HT66F60A Special Purpose Data Memory HT66F70A Special Purpose Data Memory

Rev. 1.40 4� ��st �� 01� Rev. 1.40 43 ��st �� 01�


Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection,howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0,IAR1andIAR2,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.Themethodof indirectaddressing forRAMdatamanipulationuses these IndirectAddressingRegistersandMemoryPointers, incontrast todirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0,IAR1andIAR2registerswillresult innoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0,MP1L/MP1HorMP2L/MP2H.Actingasapair, IAR0andMP0cantogetheraccessdataonlyfromSection0while theIAR1register togetherwithMP1L/MP1HregisterpairandIAR2registertogetherwithMP2L/MP2HregisterpaircanaccessdatafromanyDataMemorysection.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1FiveMemoryPointers,knownasMP0,MP1L,MP1H,MP2LandMP2H,areprovided.TheseMemoryPointersarephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister, IAR0,areusedtoaccessdatafromSection0,whileMP1L/MP1HtogetherwithIAR1andMP2L/MP2HtogetherwithIAR2areusedtoaccessdatafromalldatasectionsaccordingtothecorrespondingMP1HorMP2Hregister.DirectAddressingcanbeusedinalldatasectionsusingthecorrespondinginstructionwhichcanaddressallavailabledatamemoryspace.

Indirect Addressing Program Exampledata .section dataadres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 codeorg 00hstart: mov a,04h ; setup size of block mov block,a mova,offsetadres1 ;AccumulatorloadedwithfirstRAMaddress movmp0,a ;setupmemorypointerwithfirstRAMaddressloop: clrIAR0 ;clearthedataataddressdefinedbyMP0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificRAMaddresses.

Rev. 1.40 4� ��st �� 01� Rev. 1.40 43 ��st �� 01�


Bank Pointer – BPDependinguponwhichdeviceisused,theProgramMemoryisdividedintoseveralbanks.SelectingtherequiredProgramMemoryareaisachievedusingtheBankPointer.

TheDataMemoryis initialised toBank0afterareset,exceptforaWDTtime-outreset in thePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.DirectlyaddressingtheDataMemorywillalways result inBank0beingaccessed irrespectiveof thevalueof theBankPointer.Accessingdatafrombanksother thanBank0mustbeimplementedusingIndirectaddressing.

AsboththeProgramMemoryandDataMemorysharethesameBankPointerRegister,caremustbetakenduringprogramming.

DeviceBit

7 6 5 4 3 2 1 0HT66F60� — — — — — — — BP0HT66F�0� — — — — — — BP1 BP0

BP Register List

BP Register – HT66F60A

Bit 7 6 5 4 3 2 1 0Name — — — — — — — BP0R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas"0"Bit0 BP0:Programmemorybankpoint

0:Bank01:Bank1

BP Register – HT66F70A

Bit 7 6 5 4 3 2 1 0Name — — — — — — BP1 BP0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 BP1~BP0:Programmemorybankpoint

00:Bank001:Bank110:Bank211:Bank3

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuserdefinedregisterandanother, it isnecessary todo thisbypassingthedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Rev. 1.40 44 ��st �� 01� Rev. 1.40 45 ��st �� 01�


Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointerandindicates thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Status Register – STATUSThis8-bit registercontains thezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),SCflag,CZflag,powerdownflag(PDF),andwatchdog time-out flag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe"CLRWDT"or"HALT"instruction.ThePDFflagisaffectedonlybyexecutingthe"HALT"or"CLRWDT"instructionorduringasystempower-up.

TheZ,OV,AC,C,SCandCZflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.• OV isset ifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDF isclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.

• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.

• SCistheresultofthe“XOR”operationwhichisperformedbytheOVflagandtheMSBofthecurrentinstructionoperationresult.

• CZistheoperationalresultofdifferentflagsfordifferentinstuctions.Refertoregisterdefinitionsformoredetails.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

Rev. 1.40 44 ��st �� 01� Rev. 1.40 45 ��st �� 01�


STATUS Register

Bit 7 6 5 4 3 2 1 0Name SC CZ TO PDF OV Z �C CR/W R R R R R/W R/W R/W R/WPOR x x 0 0 x x x x

“x”: �nknownBit7 SC:Theresultofthe“XOR”operationwhichisperformedbytheOVflagandthe

MSBoftheinstructionoperationresult.Bit6 CZ:Thetheoperationalresultofdifferentflagsfordifferentinstuctions.

ForSUB/SUBM/LSUB/LSUBMinstructions, theCZflag isequal to theZflag.ForSBC/SBCM/LSBC/LSBCMinstructions,theCZflagisthe“AND”operationresultwhichisperformedbythepreviousoperationCZflagandcurrentoperationzeroflag.Forotherinstructions,theCZflagwilllnotbeaffected.

Bit5 TO:WatchdogTime-Outflag0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

Rev. 1.40 46 ��st �� 01� Rev. 1.40 4� ��st �� 01�


EEPROM Data MemoryThesedevicescontainanareaof internalEEPROMDataMemory.EEPROM,whichstandsforElectricallyErasableProgrammableReadOnlyMemory, isby itsnatureanon-volatile formof re-programmablememory,withdata retentionevenwhen itspowersupply is removed.Byincorporating thiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproductidentificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithin theproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

Device Capacity AddressHT66F60�

1��×� 00H~�FHHT66F�0�

EEPROM Data Memory StructureTheEEPROMDataMemorycapacityis128×8bitsforthisseriesofdevices.UnliketheProgramMemoryandRAMDataMemory,theEEPROMDataMemoryisnotdirectlymappedintomemoryspaceandisthereforenotdirectlyaddressableinthesamewayastheothertypesofmemory.ReadandWriteoperationstotheEEPROMarecarriedoutinsinglebyteoperationsusinganaddressanddataregisterinSection0andasinglecontrolregisterinSection1.

EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinSection0, theycanbedirectlyaccessedinthesamewasasanyotherSpecialFunctionRegister.TheEECregisterhowever,being located inBank1,cannotbeaddresseddirectlyandcanonlybereadfromorwrittentoindirectlyusingtheMP1MemoryPointerandIndirectAddressingRegister, IAR1.Because theEECcontrol register is locatedataddress40HinSection1, theMP1LMemoryPointer lowbytemustfirstbeset tothevalue40HandtheMP1HMemoryPointerhighbytesettothevalue01HbeforeanyoperationsontheEECregisterareexecuted.

EEA Register

Bit 7 6 5 4 3 2 1 0Name — EE�6 EE�5 EE�4 EE�3 EE�� EE�1 EE�0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — x x x x x x x

“x”: �nknownBit7 Unimplemented,readas"0"Bit6~0 EEA6~EEA0:DataEEPROMaddressbit6~bit0

EED Register

Bit 7 6 5 4 3 2 1 0Name EED� EED6 EED5 EED4 EED3 EED� EED1 EED0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

“x”: �nknownBit7~0 EED7~EED0:DataEEPROMdatabit7~bit0

Rev. 1.40 46 ��st �� 01� Rev. 1.40 4� ��st �� 01�


EEC Register

Bit 7 6 5 4 3 2 1 0Name — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3 WREN:DataEEPROMwriteoperationenable

0:Disable1:Enable

ThisistheDataEEPROMWriteOperationEnablebitwhichmustbesethighbeforeDatatEEPROMwriteoperationsarecarriedout.ClearingthisbittozerowillinhibitDataEEPROMwriteoperations.

Bit2 WR:DataEEPROMwritecontrol0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlbitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENbithasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMreadoperationenable0:Disable1:Enable

ThisistheDataEEPROMReadOperationEnablebitwhichmustbesethighbeforeDatatEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:DataEEPROMreadcontrol0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlbitandwhensethighby theapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENbithasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDbitscannotbesetto“1”atthesametimeinoneinstruction.TheWRandRDbitscannotbesetto“1”atthesametime.

Reading Data from the EEPROMToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.

Rev. 1.40 4� ��st �� 01� Rev. 1.40 49 ��st �� 01�


Writing Data to the EEPROMTheEEPROMaddressofthedatatobewrittenmustfirstbeplacedintheEEAregisterandthedataplacedintheEEDregister.TowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethightoenablethewritefunction.Afterthis,theWRbitintheEECregistermustbe immediatelysethighto initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbefore implementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.NotethatsettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallycleared tozeroby themicrocontroller, informing theuser that thedatahasbeenwritten to theEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispowered-on theWriteEnablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheMemoryPointerpairs,MP1L/MP1HandMP2L/MP2H,willberesettozero,whichmeansthatDataMemorySection0willbeselected.AstheEEPROMcontrolregister is located inSection1, thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuring that theWriteEnablebit in thecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbitintherelevantinterruptregister.HoweverastheEEPROMiscontainedwithinaMulti-functionInterrupt,theassociatedmulti-functioninterruptenablebitmustalsobeset.WhenanEEPROMwritecycleends, theDEFrequest flagand itsassociatedmulti-functioninterruptrequestflagwillbothbeset.Iftheglobal,EEPROMandMulti-function interruptsareenabledandthestackisnotfull,a jumpto theassociatedMulti-functionInterruptvectorwilltakeplace.WhentheinterruptisservicedonlytheMulti-functioninterruptflagwillbeautomaticallyreset, theEEPROMinterruptflagmustbemanuallyresetbytheapplicationprogram.MoredetailscanbeobtainedintheInterruptsection.

Programming ConsiderationsCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.ProtectioncanbeenhancedbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheMemoryPointerhighbyte,MP1HorMP2H,couldbenormallyclearedtozeroasthiswouldinhibitaccess toDataMemorySection1where theEEPROMcontrol registerexist.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.

WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.Theglobal interruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.

Rev. 1.40 4� ��st �� 01� Rev. 1.40 49 ��st �� 01�


Programming Examples

Reading Data from the EEPROM – Polling MothodMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,040H ;setupmemorypointerMP1LMOV MP1L,A ;MP1pointstoEECregisterMOV A,01H ;setupmemorypointerMP1HMOV MP1H,ASET IAR1.1 ;setRDENbit,enablereadoperationsSET IAR1.0 ;startReadCycle-setRDbitBACK:SZ IAR1.0 ;checkforreadcycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR MP1HMOV A,EED ;movereaddatatoregisterMOV READ_DATA,A

Writing Data to the EEPROM – Polling MothodCLR EMIMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,EEPROM_DATA ;userdefineddataMOV EED,AMOV A,040H ;setupmemorypointerMP1LMOV MP1L,A ;MP1pointstoEECregisterMOV A,01H ;setupmemorypointerMP1HMOV MP1H,ASET IAR1.3 ;setWRENbit,enablewriteoperationsSET IAR1.2 ;StartWriteCycle-setWRbit-executedimmediately ;aftersetWRENbitSET EMIBACK:SZ IAR1.2 ;checkforwritecycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR MP1H

Rev. 1.40 50 ��st �� 01� Rev. 1.40 51 ��st �� 01�


OscillatorVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughacombinationofconfigurationoptionsandregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfor theWatchdogTimerandTimeBaseInterrupts.Externaloscillators requiringsomeexternalcomponentsaswellas fully integrated internaloscillators, requiringnoexternalcomponents,areprovided to formawide rangeof both fast and slow systemoscillators.All oscillatoroptionsareselected throughtheconfigurationoptions.Thehigherfrequencyoscillatorsprovidehigherperformancebutcarrywith it thedisadvantageofhigherpowerrequirements,while theoppositeisofcoursetruefor thelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock, thesedeviceshavetheflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Frequency PinsExternal Crystal HXT 400kHz~16MHz OSC1/OSC�External RC ERC 400kHz~16MHz OSC1Internal Hi�h Speed RC HIRC �MHz —External Low Speed Crystal LXT 3�.�6�kHz XT1/XT�Internal Low Speed RC LIRC 3�kHz —

Oscillator Types

System Clock ConfigurationsTherearefivemethodsofgeneratingthesystemclock, threehighspeedoscillatorsandtwolowspeedoscillators.Thehighspeedoscillatorsareistheexternalcrystal/ceramicoscillator,externalRCnetworkoscillatorandtheinternal8MHzRCoscillator.Thetwolowspeedoscillatorsaretheinternal32kHzRCoscillatorandtheexternal32.768kHzcrystaloscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

Theactual sourceclockused foreachof thehighspeedand lowspeedoscillators ischosenviaconfigurationoptions.Thefrequencyof theslowspeedorhighspeedsystemclock isalsodeterminedusing theHLCLKbitandCKS2~CKS0bits in theSMODregister.Note that twooscillatorselectionsmustbemadenamelyonehighspeedandonelowspeedsystemoscillators.Itisnotpossibletochooseano-oscillatorselectionforeitherthehighorlowspeedoscillator.

Rev. 1.40 50 ��st �� 01� Rev. 1.40 51 ��st �� 01�


HXT

HIRC

PrescalerfH

LIRC

LXT

Hi�h Speed Oscillation (HOSC)

Low Speed Oscillation (LOSC)

fH/�

fH/16

fH/64

fH/�

fH/4

fH/3�

Hi�h Speed OscillationConfi��ration Option

Low Speed OscillationConfi��ration Option

CKS[�:0]� HLCLK

fSYS

Fast Wake-�p from SLEEP Mode or IDLE Mode Control (for HXT only)

fSYS/4

fSUB

fTB

WDT

Time Base

CLKS0[1:0]

ERC

fSUB

fSUB

fSYS

fH

Prescaler

fP

CLKS1[1:0]

Prescaler Peripheral Clock O�tp�t (PCK)

TB� [�:0]

TB0 [�:0] TB1 [�:0]

fSYS/4fSUB

fSYS

fH

External Crystal/Ceramic Oscillator – HXTTheExternalCrystal/CeramicSystemOscillator isoneof thehighfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Formostcrystaloscillatorconfigurations, thesimpleconnectionofacrystalacrossOSC1andOSC2willcreatethenecessaryphaseshiftandfeedbackforoscillation,withoutrequiringexternalcapacitors.However,forsomecrystaltypesandfrequencies,toensureoscillation,itmaybenecessarytoaddtwosmallvaluecapacitors,C1andC2.Usingaceramicresonatorwillusuallyrequiretwosmallvaluecapacitors,C1andC2,tobeconnectedasshownforoscillationtooccur.ThevaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturer'sspecification.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk,itisimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwith interconnectinglinesarealllocatedasclosetotheMCUaspossible.

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Crystal/Resonator Oscillator – HXT

Rev. 1.40 5� ��st �� 01� Rev. 1.40 53 ��st �� 01�


Crystal Oscillator C1 and C2 Values

Crystal Frequency C1 C21�MHz 0pF 0pF�MHz 0pF 0pF4MHz 0pF 0pF1MHz 100pF 100pF

Note: C1 and C� val�es are for ��idance only.

Crystal Recommended Capacitor Values

External RC Oscillator – ERCUsingtheERCoscillatoronlyrequiresthataresistor,withavaluebetween56kΩand2.4MΩ,isconnectedbetweenOSC1andVDD,andacapacitor isconnectedbetweenOSC1andground,providinga lowcostoscillatorconfiguration.It isonly theexternalresistor thatdetermines theoscillationfrequency;theexternalcapacitorhasnoinfluenceoverthefrequencyandisconnectedforstabilitypurposesonly.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internal frequencycompensationcircuitsareused toensure that the influenceof thepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresistance/frequencyreferencepoint,itcanbenotedthatwithanexternal120kΩresistorconnectedandwitha5Vvoltagepowersupplyandtemperatureof25°Cdegrees, theoscillatorwillhaveafrequencyof8MHzwithinatoleranceof2%.HereonlytheOSC1pinisused,whichissharedwithI/OpinPB1,leavingpinPB2freeforuseasanormalI/Opin.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk,itisimportanttolocatethecapacitorandresistorasclosetotheMCUaspossible.

� � � ��

� � �

� � � �

External RC Oscillator – ERC

Internal High Speed RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.The internalRCoscillator has a fixed frequency of 8MHz.Device trimming during themanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethat theinfluenceof thepowersupplyvoltage, temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25°Cdegrees,thefixedoscillationfrequencyof8MHzwillhaveatolerancewithin2%.Notethatifthisinternalsystemclockoptionisselected,asitrequiresnoexternalpinsforitsoperation,I/OpinsPB1andPB2arefreeforuseasnormalI/Opins.

Rev. 1.40 5� ��st �� 01� Rev. 1.40 53 ��st �� 01�


External 32.768kHz Crystal Oscillator – LXTTheExternal32.768kHzCrystalSystemOscillatorisoneofthelowfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Thisclocksourcehasafixedfrequencyof32.768kHzandrequiresa32.768kHzcrystaltobeconnectedbetweenpinsXT1andXT2.Theexternalresistorandcapacitorcomponentsconnectedtothe32.768kHzcrystalarenecessarytoprovideoscillation.Forapplicationswhereprecise frequenciesareessential, thesecomponentsmayberequired toprovidefrequencycompensationduetodifferentcrystalmanufacturingtolerances.Duringpower-upthereisatimedelayassociatedwiththeLXToscillatorwaitingforittostart-up.

WhenthemicrocontrollerenterstheSLEEPorIDLEMode,thesystemclockisswitchedofftostopmicrocontrolleractivityand toconservepower.However, inmanymicrocontrollerapplicationsitmaybenecessary tokeep the internal timersoperationalevenwhenthemicrocontroller is intheSLEEPorIDLEMode.Todothis,anotherclock, independentof thesystemclock,mustbeprovided.

However,forsomecrystals,toensureoscillationandaccuratefrequencygeneration,itisnecessarytoaddtwosmallvalueexternalcapacitors,C1andC2.TheexactvaluesofC1andC2shouldbeselected inconsultationwith thecrystalor resonatormanufacturer’sspecification.Theexternalparallelfeedbackresistor,Rp,isrequired.

SomeconfigurationoptionsdetermineiftheXT1/XT2pinsareusedfortheLXToscillatororasI/Opins.

• IftheLXToscillatorisnotusedforanyclocksource,theXT1/XT2pinscanbeusedasnormalI/Opins.

• IftheLXToscillatorisusedforanyclocksource,the32.768kHzcrystalshouldbeconnectedtotheXT1/XT2pins.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk,itisimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwith interconnectinglinesarealllocatedasclosetotheMCUaspossible.

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� � � � � � � � � � ��

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External LXT Oscillator

LXT Oscillator C1 and C2 Values

Crystal Frequency C1 C23�.�6�kHz 10pF 10pF

Note: 1. C1 and C� val�es are for ��idance only.�. RP=5MΩ~10MΩ is recommended.

32.768kHz Crystal Recommended Capacitor Values

Rev. 1.40 54 ��st �� 01� Rev. 1.40 55 ��st �� 01�


LXT Oscillator Low Power FunctionTheLXToscillatorcanfunctioninoneoftwomodes,theQuickStartModeandtheLowPowerMode.ThemodeselectionisexecutedusingtheLXTLPbitintheSMOD2register.

• SMOD2 Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — — LXTLPR/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas"0"Bit0 LXPLP:LXTLowPowerControl

0:QuickStartmode1:LowPowermode

AfterpowerontheLXTLPbitwillbeautomaticallyclearedtozeroensuringthattheLXToscillatoris in theQuickStartoperatingmode.IntheQuickStartModetheLXToscillatorwillpowerupandstabilisequickly.However,after theLXToscillatorhas fullypoweredup itcanbeplacedintotheLow-powermodebysettingtheLXTLPbithigh.Theoscillatorwillcontinuetorunbutwithreducedcurrentconsumption,asthehighercurrentconsumptionisonlyrequiredduringtheLXToscillatorstart-up.Inpowersensitiveapplications,suchasbatteryapplications,wherepowerconsumptionmustbekepttoaminimum,itisthereforerecommendedthattheapplicationprogramsetstheLXTLPbithighabout2secondsafterpower-on.

Itshouldbenotedthat,nomatterwhatconditiontheLXTLPbit issetto, theLXToscillatorwillalwaysfunctionnormally, theonlydifference is that itwill takemore time tostartup if in theLow-powermode.

Internal Low Speed Oscillator – LIRCTheInternal32kHzSystemOscillator isoneof the lowfrequencyoscillatorchoices,which isselectedviaconfigurationoption.It isafullyintegratedRCoscillatorwithatypicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor its implementation.Device trimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25°Cdegrees,thefixedoscillationfrequencyof32kHzwillhaveatolerancewithin3%.

Supplementary OscillatorsThelowspeedoscillators,inadditiontoprovidingasystemclocksourcearealsousedtoprovideaclocksourcetotwootherdevicesfunctions.ThesearetheWatchdogTimerandtheTimeBaseInterrupts.

Rev. 1.40 54 ��st �� 01� Rev. 1.40 55 ��st �� 01�


Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcourseviceversa,lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthesedeviceswithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.

System ClockThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingconfigurationoptionsandregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequency,fH,orlowfrequency,fSUB,source,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromanHXT,ERCorHIRCoscillator,selectedviaaconfigurationoption.Thelowspeedsystemclocksourcecanbesourcedfromtheclock,fSUB.IffSUB isselectedthenitcanbesourcedbyeithertheLXTorLIRCoscillators,selectedviaaconfigurationoption.Theotherchoice,which isadividedversionof thehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

ThefSUBclockisusedtoprovideasubstituteclockforthemicrocontrollerjustafterawake-uphasoccurredtoenablefasterwake-uptimes.ThefSUBclockisalsousedtoprovidetheclocksourcefortimebaseandwatchdogtimerfunctions.

HXT

HIRC

PrescalerfH

LIRC

LXT

Hi�h Speed Oscillation (HOSC)

Low Speed Oscillation (LOSC)

fH/�

fH/16

fH/64

fH/�

fH/4

fH/3�

Hi�h Speed OscillationConfi��ration Option

Low Speed OscillationConfi��ration Option

CKS[�:0]� HLCLK

fSYS

Fast Wake-�p from SLEEP Mode or IDLE Mode Control (for HXT only)

fSYS/4

fSUB

fTP

WDT

Time Base

CLKS0[1:0]

ERC

fSUB

fSUB

fSYS

fHPrescaler

System Clock Configurations

Note:WhenthesystemclocksourcefSYSisswitchedtofSUBfromfH,thehighspeedoscillationwillstoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.

Rev. 1.40 56 ��st �� 01� Rev. 1.40 5� ��st �� 01�


System Operation ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingfourmodes,theSLEEP0,SLEEP1, IDLE0andIDLE1Modeareusedwhen themicrocontrollerCPUisswitchedoff toconservepower.

Operating ModeDescription

CPU fSYS fSUB

NORM�L Mode On fH~fH/64 OnSLOW Mode On fSUB OnIDLE0 Mode Off Off OnIDLE1 Mode Off On OnSLEEP0 Mode Off Off OffSLEEP1 Mode Off Off On

NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbyoneofthehighspeedoscillators.Thismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromoneofthehighspeedoscillators,eithertheHXT,ERCorHIRCoscillators.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbits in theSMODregister.Althoughahighspeedoscillator isused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.Theclocksourceusedwillbefromoneofthelowspeedoscillators,eithertheLXTortheLIRC.Runningthemicrocontrollerinthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.

SLEEP0 ModeTheSLEEP0ModeisenteredwhenanHALTinstruction isexecutedandtheIDLENbit in theSMODregister is low.IntheSLEEP0modetheCPUwillbestoppedandthefSUBclockwillbestoppedtoo,andtheWatchdogTimerfunctionisdisabled.Inthismode,theLVDENismustsetto“0”.IftheLVDENissetto“1”,itwon’tentertheSLEEP0Mode.

SLEEP1 ModeTheSLEEP1ModeisenteredwhenanHALTinstruction isexecutedandtheIDLENbit in theSMODregister is low. In theSLEEP1mode theCPUwillbestopped.However the fSUBwillcontinuetooperateiftheLVDENis“1”ortheWatchdogTimerfunctionisenabled.

IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheSMOD1registerislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchastheWatchdogTimerandTMs.IntheIDLE0Mode,thesystemoscillatorwillbestoppedwhilethefSUBclockwillbeon.

Rev. 1.40 56 ��st �� 01� Rev. 1.40 5� ��st �� 01�


IDLE1 ModeTheIDLE1ModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheSMOD1registerishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimerandTMs.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModethefSUBclockwillalsobeon.

Control RegisterAregisterpair,SMODandSMOD1, isusedforoverallcontrolof the internalclockswithinthedevice.

SMOD Register

Bit 7 6 5 4 3 2 1 0Name CKS� CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLKR/W R/W R/W R/W R/W R R R/W R/WPOR 0 0 0 0 0 0 1 1

Bit7~5 CKS2~CKS0:ThesystemclockselectionwhenHLCLKis"0"000:fSUB(fLXTorfLIRC)001:fSUB(fLXTorfLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedas thesystemclocksource.Inadditiontothesystemclocksource,whichcanbeeithertheLXTortheLIRC,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

Bit4 FSTEN:FastWake-upControl(onlyforHXT)0:Disable1:Enable

This is theFastWake-upControlbitwhichdetermines if the fSUBclocksource isinitiallyusedafterthedevicewakesup.Whenthebitishigh,thefSUBclocksourcecanbeusedasatemporarysystemclocktoprovideafasterwakeuptimeasthefSUBclockisavailable.

Bit3 LTO:Lowspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillator isstableafterpoweronresetorawake-uphasoccurred.TheflagwillbelowwhenintheSLEEP0Modebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter1024clockcycles if theLXToscillator isusedor1~2clockcyclesistheLIRCoscillatorisused.

Rev. 1.40 5� ��st �� 01� Rev. 1.40 59 ��st �� 01�


Bit2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter1024clockcyclesiftheHXToscillatorisusedor15~16clockcyclesiftheERCorHIRCoscillatorisused.

bit1 IDLEN:IDLEModecontrol0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

bit0 HLCLK:systemclockselection0:fH/2~fH/64orfSUB

1:fH

Thisbit isused toselect if the fHclockor the fH/2~fH/64or fSUBclock isusedasthesystemclock.Whenthebit ishigh thefHclockwillbeselectedandif lowthefH/2~fH/64or fSUBclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

Rev. 1.40 5� ��st �� 01� Rev. 1.40 59 ��st �� 01�


SMOD1 Register

Bit 7 6 5 4 3 2 1 0Name FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — x 0 0

“x”: �nknownBit7 FSYSON:fSYSControlinIDLEMode

0:Disable1:Enable

Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

0:Notoccurred1:Occurred

Thisbit isset to1whenaspecificLowVoltageResetsituationoccurs.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit1 LRF:LVRControlregistersoftwareresetflag0:Notoccurred1:Occurred

Thisbitissetto1iftheLVRCregistercontainsanynondefinedLVRvoltageregistervalues.Thisineffectactslikeasoftware-resetfunction.Thisbitcanonlybeclearedto0bytheapplicationprogram.

bit0 WRF:WDTControlregistersoftwareresetflag0:Notoccurred1:Occurred

Thisbit isset to1by theWDTControlregistersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.

Rev. 1.40 60 ��st �� 01� Rev. 1.40 61 ��st �� 01�


Fast Wake-upTominimisepowerconsumptionthedevicecanentertheSLEEPorIDLE0Mode,wherethesystemclocksourcetothedevicewillbestopped.Howeverwhenthedeviceiswokenupagain,itcantakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabilizeandallownormaloperationtoresume.ToensurethedeviceisupandrunningasfastaspossibleaFastWake-upfunctionisprovided,whichallowsfSUB,namelyeithertheLXTorLIRCoscillator,toactasatemporaryclocktofirstdrivethesystemuntil theoriginalsystemoscillatorhasstabilised.AstheclocksourcefortheFastWake-upfunctionisfSUB, theFastWake-upfunctionisonlyavailableintheSLEEP1andIDLE0modes.WhenthedeviceiswokenupfromtheSLEEP0mode,theFastWake-upfunctionhasnoeffectbecausethefSUBclockisstopped.TheFastWake-upenable/disablefunctioniscontrolledusingtheFSTENbitintheSMOD1register.

If theHXToscillator isselectedas theNORMALModesystemclockand if theFastWake-upfunctionisenabled,thenitwilltakeonetotwotSUBclockcyclesoftheLXTorLIRCoscillatorforthesystemtowake-up.Thesystemwill theninitiallyrununder thefSUBclocksourceuntil1024HXTclockcycleshaveelapsed,atwhichpointtheHTOflagwillswitchhighandthesystemwillswitchovertooperatingfromtheHXToscillator.

IftheERC/HIRCorLIRCoscillatorisusedasthesystemoscillator, thenitwill take15~16clockcyclesoftheERC/HIRCoscillatoror1~2clockcyclesoftheLIRCosrillatorrespectivelytowakeupthesystemfromtheSLEEPorIDLE0Mode.TheFastWake-upbit,FSTENwillhavenoeffectinthesecases.

SystemOscillator

FSTENBit

Wake-up Time(SLEEP0 Mode)

Wake-up Time(SLEEP1 Mode)

Wake-up Time(IDLE0 Mode)

Wake-up Time(IDLE1 Mode)

HXT

0 10�4 HXT cycles 10�4 HXT cycles 1~� HXT cycles

1 10�4 HXT cycles1~� fSUB cycles(System r�ns with fSUB first for 1024 HXT cycles and then switches over to r�n with the HXT clock )

1~� HXT cycles

ERC x 15~16 ERC cycles 15~16 ERC cycles 1~� ERC cyclesHIRC x 15~16 HIRC cycles 15~16 HIRC cycles 1~� HIRC cyclesLIRC x 1~� LIRC cycles 1~� LIRC cycles 1~� LIRC cyclesLXT x 10�4 LXT cycles 10�4 LXT cycles 1~� LXT cycles

Wake-up Times

NotethatiftheWatchdogTimerisdisabled,whichmeansthatthefSUBclockderivedfromtheLXTorLIRCoscillator isoff, thentherewillbenoFastWake-upfunctionavailablewhenthedevicewakesupfromtheSLEEP0Mode.

Rev. 1.40 60 ��st �� 01� Rev. 1.40 61 ��st �� 01�


Operating Mode SwitchingThedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionoftheIDLENbitintheSMODregisterandFSYSONintheSMOD1register.

WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfSUB.IftheclockisfromthefSUB,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchastheTMs.Theaccompanyingflowchartshowswhathappenswhenthedevicemovesbetweenthevariousoperatingmodes.

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Rev. 1.40 6� ��st �� 01� Rev. 1.40 63 ��st �� 01�


NORMAL Mode to SLOW Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower,thesystemclockcanswitchtorunintheSLOWModebysettheHLCLKbitto“0”andsettheCKS2~CKS0bitsto“000”or“001”intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLXTor theLIRCoscillatorsandthereforerequires theseoscillatorstobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

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Rev. 1.40 6� ��st �� 01� Rev. 1.40 63 ��st �� 01�


SLOW Mode to NORMAL Mode SwitchingInSLOWModethesystemuseseither theLXTorLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,wherethehighspeedsystemoscillatorisused,theHLCLKbitshouldbeset to“1”orHLCLKbit is“0”,butCKS2~CKS0isset to“010”,“011”,“100”,“101”,“110”or“111”.Asacertainamountof timewillberequiredfor thehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.Theamountoftimerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.

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Rev. 1.40 64 ��st �� 01� Rev. 1.40 65 ��st �� 01�


Entering the SLEEP0 ModeThereisonlyonewayforthedevicetoentertheSLEEP0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTandLVDbothoff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandthefSUBclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandstoppedastheWDTisdisabled.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Entering the SLEEP1 ModeThereisonlyonewayforthedevicetoentertheSLEEP1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTorLVDon.When this instruction isexecutedunder theconditionsdescribedabove, thefollowingwilloccur:

• The systemclockwill be stoppedand the applicationprogramwill stopat the “HALT”instruction,buttheWDTorLVDwillremainwiththeclocksourcecomingfromthefSUBclock.


• TheWDTwillbeclearedandresumecountingastheWDTisenabledanditsclocksourceisderivedfromthefSUBclock.



Entering the IDLE0 ModeThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinSMOD1registerequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• The systemclockwill be stoppedand the applicationprogramwill stopat the “HALT”instruction,butthefSUBclockwillbeon.


• TheWDTwillbeclearedandresumecountingastheWDTclocksourceisderivedfromthefSUBclock.



Rev. 1.40 64 ��st �� 01� Rev. 1.40 65 ��st �� 01�


Entering the IDLE1 ModeThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinSMOD1registerequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandfSUBclockwillbeonandtheapplicationprogramwillstopatthe“HALT”instruction.


• TheWDTwillbeclearedandresumecountingastheWDTclocksourceisderivedfromthefSUBclock.



Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthesedevicestoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode, thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesigner if thepowerconsumptionis tobeminimised.SpecialattentionmustbemadetotheI/Opinsonthesedevices.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbondedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.Alsonote thatadditionalstandbycurrentwillalsoberequiredif theconfigurationoptionshaveenabledtheLXTorLIRCoscillator.

In theIDLE1Mode thesystemoscillator ison, if thesystemoscillator is fromthehighspeedsystemoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Rev. 1.40 66 ��st �� 01� Rev. 1.40 6� ��st �� 01�


Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• Anexternalreset

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

Ifthesystemiswokenupbyanexternalreset, thesedeviceswillexperienceafullsystemreset,however, if thesedevicesarewokenupbyaWDToverflow,aWatchdogTimer resetwillbeinitiated.Althoughbothofthesewake-upmethodswillinitiatearesetoperation,theactualsourceofthewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe“HALT”instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwoke-upthesedeviceswillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterrupt isenabledandthestack isnotfull, inwhichcase theregular interruptresponse takesplace. IfaninterruptrequestflagissethighbeforeenteringtheSLEEPorIDLEMode,thewake-upfunctionoftherelatedinterruptwillbedisabled.

Programming ConsiderationsTheHXTandLXToscillatorsbothusethesameSSTcounter.Forexample,ifthesystemiswokenupfromtheSLEEP0ModeandboththeHXTandLXToscillatorsneedtostart-upfromanoffstate.TheLXToscillatorusestheSSTcounterafterHXToscillatorhasfinisheditsSSTperiod.

• IfthedeviceiswokenupfromtheSLEEP0ModetotheNORMALMode,thehighspeedsystemoscillatorneedsanSSTperiod.Thedevicewillexecutefirst instructionafterHTOis"1".Atthistime,theLXToscillatormaynotbestableiffSUBisfromLXToscillator.Thesamesituationoccursinthepower-onstate.TheLXToscillator isnotreadyyetwhenthefirst instructionisexecuted.

• If thedeviceiswokenupfromtheSLEEP1ModetoNORMALMode,andthesystemclocksourceisfromHXToscillatorandFSTENis“1”,thesystemclockcanbeswitchedtotheLXTorLIRCoscillatorafterwakeup.

• Thereareperipheralfunctions,suchasWDTandTMs,forwhichthefSYSisused.IfthesystemclocksourceisswitchedfromfHtofSUB,theclocksourcetotheperipheralfunctionsmentionedabovewillchangeaccordingly.

• Theon/offconditionoffSUBdependsuponwhethertheWDTisenabledordisabledastheWDTclocksourceisselectedfromfSUB.

Rev. 1.40 66 ��st �� 01� Rev. 1.40 6� ��st �� 01�


Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbythefSUBclock.ThefSUBclockcanbesourcedfromeithertheLXTorLIRCoscillatorselectedbyaconfigurationoption.TheLIRCinternaloscillatorhasanapproximatefrequencyof32kHzandthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.TheLXToscillatorissuppliedbyanexternal32.768kHzcrystal.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to218togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.

Watchdog Timer Control RegisterAsingle register,WDTC,controls the required timeoutperiodaswell as theenable/disableoperation.ThisregistercontrolstheoveralloperationoftheWatchdogTimer.

WDTC Register

Bit 7 6 5 4 3 2 1 0Name WE4 WE3 WE� WE1 WE0 WS� WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit7~3 WE4~WE0:WDTfunctionenablecontrol10101:Disabled01010:EnabledOtherValues:ResetMCU

Ifthesebitsarechangedduetoadverseenvironmentalconditions,themicrocontrollerwillbereset.Theresetoperationwillbeactivatedafter2~3LIRCclockcyclesandtheWRFbitintheSMOD1registerwillbesetto1.

Bit2~0 WS2~WS0:SelectWDTTimeoutPeriod000:28/fSUB

001:210/fSUB

010:212/fSUB

011:214/fSUB

100:215/fSUB

101:216/fSUB

110:217/fSUB

111:218/fSUB

These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.

Rev. 1.40 6� ��st �� 01� Rev. 1.40 69 ��st �� 01�


SMOD1 Register



DescribedelsewhereBit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

DescribedelsewhereBit1 LRF:LVRControlregistersoftwareresetflag

Describedelsewherebit0 WRF:WDTControlregistersoftwareresetflag


Thisbit isset to1by theWDTControlregistersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.

Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.WithregardtotheWatchdogTimerenable/disablefunction,therearefivebits,WE4~WE0,intheWDTCregistertooffertheenable/disablecontrolandresetcontroloftheWatchdogTimer.TheWDTfunctionwillbedisabledwhentheWE4~WE0bitsareset toavalueof10101BwhiletheWDTfunctionwillbeenablediftheWE4~WE0bitsareequalto01010B.IftheWE4~WE0bitsaresettoanyothervalues,other than01010Band10101B,itwillreset thedeviceafter2~3fSUBclockcycles.Afterpoweronthesebitswillhaveavalueof01010B.

WDT Function Control WE4~WE0 Bits WDT Function

�pplication Pro�ram Enabled10101B Disable01010B Enable

�ny other val�e Reset MCU

Watchdog Timer Enable/Disable Control

Rev. 1.40 6� ��st �� 01� Rev. 1.40 69 ��st �� 01�


Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101BwrittenintotheWE4~WE0field,thesecondisusingtheWatchdogTimersoftwareclearinstructionandthethirdisviaaHALTinstruction.

ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle“CLRWDT”instructiontocleartheWDTcontents.

Themaximumtimeoutperiod iswhenthe218divisionratio isselected.Asanexample,witha32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8secondforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.

“CLR WDT”Instr�ction

�-sta�e Divider WDT Prescaler

WE4~WE0 bitsWDTC Re�ister Reset MCU

LXT fSUB fS/��

�-to-1 MUX

CLR

WS�~WS0(fS/�� ~ fS/�1�)

WDT Time-o�t(��/fS ~ �1�/fS)

LIRC

MUX

Low Speed Oscillator Confi��ration option

Watchdog Timer

Rev. 1.40 �0 ��st �� 01� Rev. 1.40 �1 ��st �� 01�


Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Inadditiontothepower-onreset,situationsmayarisewhereit isnecessarytoforcefullyapplyaresetconditionwhenthe isrunning.Oneexampleof this iswhereafterpowerhasbeenappliedandtheisalreadyrunning,theRESlineisforcefullypulledlow.Insuchacase,knownasanormaloperationreset,someof the registersremainunchangedallowing the toproceedwithnormaloperationaftertheresetlineisallowedtoreturnhigh.

Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresult indifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset,similartotheRESresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsThereare fiveways inwhichamicrocontroller resetcanoccur, througheventsoccurringbothinternallyandexternally:

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

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Note:tRSTDispower-ondelay,typicaltime=50ms

Power-on Reset Timing Chart

Rev. 1.40 �0 ��st �� 01� Rev. 1.40 �1 ��st �� 01�


RES PinAstheresetpin issharedwithPB.0, the reset functionmustbeselectedusingaconfigurationoption.AlthoughthemicrocontrollerhasaninternalRCresetfunction, if theVDDpowersupplyrise timeisnotfastenoughordoesnotstabilisequicklyatpower-on, the internalresetfunctionmaybeincapableofprovidingproperresetoperation.For thisreasonit isrecommendedthatanexternalRCnetworkisconnectedtotheRESpin,whoseadditionaltimedelaywillensurethattheRESpinremainslowforanextendedperiodtoallowthepowersupplytostabilise.Duringthistimedelay,normaloperationofthemicrocontrollerwillbeinhibited.AftertheRESlinereachesacertainvoltagevalue,theresetdelaytimetRSTDisinvokedtoprovideanextradelaytimeafterwhichthemicrocontrollerwillbeginnormaloperation.TheabbreviationSSTinthefiguresstandsforSystemStart-upTimer.

FormostapplicationsaresistorconnectedbetweenVDDandtheRESpinandacapacitorconnectedbetweenVSSandtheRESpinwillprovideasuitableexternalresetcircuit.AnywiringconnectedtotheRESpinshouldbekeptasshortaspossibletominimiseanystraynoiseinterference.

ForapplicationsthatoperatewithinanenvironmentwheremorenoiseispresenttheEnhancedResetCircuitshownisrecommended.

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Note:*ItisrecommendedthatthiscomponentisaddedforaddedESDprotection.

**It isrecommendedthatthiscomponentisaddedinenvironmentswherepowerlinenoiseissignificant.

Extern RES Circuit

MoreinformationregardingexternalresetcircuitsislocatedinApplicationNoteHA0075EontheHoltekwebsite.

PullingtheRESPinlowusingexternalhardwarewillalsoexecuteadevicereset.Inthiscase,asinthecaseofotherresets,theProgramCounterwillresettozeroandprogramexecutioninitiatedfromthispoint.

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Note: tRSTDispower-ondelay,typicaltime=16.7ms

RES Reset Timing Chart

Rev. 1.40 �� st �� 01� Rev. 1.40 �3 ��st �� 01�


Low Voltage Reset – LVRThemicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.TheLVRfunctionisalwaysenabledwithaspecificLVRvoltage,VLVR.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbitintheSMOD1registerwillalsobesetto1.ForavalidLVRsignal,alowsupplyvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistforatimegreaterthanthatspecifiedbytLVRintheA.C.characteristics.Ifthelowsupplyvoltagestatedoesnotexceedthisvalue,theLVRwillignorethelowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRvaluecanbeselectedbytheLVSbitsintheLVRCregister. If theLVS7~LVS0bitshaveanyothervalue,whichmayperhapsoccurduetoadverseenvironmentalconditionssuchasnoise, theLVRwillresetthedeviceafter2~3fSUBclockcycles.Whenthishappens,theLRFbitintheSMOD1registerwillbesetto1.Afterpowerontheregisterwillhavethevalueof01010101B.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceentersthepowerdownmode.

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Note:tRSTDispower-ondelay,typicaltime=50ms

Low Voltage Reset Timing Chart

• LVRC Register

Bit 7 6 5 4 3 2 1 0Name LVS� LVS6 LVS5 LVS4 LVS3 LVS� LVS1 LVS0R/W R/W R/W R/W R/W R/w R/w R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 LVS7~LVS0:LVRvoltageselect01010101:2.1V00110011:2.55V10011001:3.15V10101010:3.8VAnyothervalues:GeneratesMCUreset–registerisresettoPORvalue

Whenanactuallowvoltageconditionoccurs,asspecifiedbyoneofthefourdefinedLVRvoltagevaluesabove,anMCUresetwillbegenerated.Theresetoperationwillbeactivatedafter2~3fSUBclockcycles. In thissituation theregistercontentswillremainthesameaftersucharesetoccurs.Anyregistervalue,otherthanthefourdefinedregistervaluesabove,willalsoresultinthegenerationofanMCUreset.Theresetoperationwillbeactivatedafter2~3fSUBclockcycles.HoweverinthissituationtheregistercontentswillberesettothePORvalue.

Rev. 1.40 �� st �� 01� Rev. 1.40 �3 ��st �� 01�


• SMOD1 Register



DescribedelsewhereBit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag


Thisbitissetto1whenaspecificLowVoltageResetsituationconditionoccurs.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit1 LRF:LVRControlregistersoftwareresetflag0:Notoccurred1:Occurred

Thisbitissetto1iftheLVRCregistercontainsanynondefinedLVRvoltageregistervalues.Thisineffectactslikeasoftware-resetfunction.Thisbitcanonlybeclearedto0bytheapplicationprogram.

bit0 WRF:WDTControlregistersoftwareresetflagDescribedelsewhere

Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperation is thesameasahardwareRESpinresetexceptthattheWatchdogtime-outflagTOwillbesetto“1”.

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WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto“0”andtheTOflagwillbesetto“1”.RefertotheA.C.CharacteristicsfortSSTdetails.

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Note:ThetSSTis15~16clockcyclesifthesystemclocksourceisprovidedbyERCorHIRC.ThetSSTis1024clockforHXTorLXT.ThetSSTis1~2clockforLIRC.

WDT Time-out Reset during SLEEP or IDLE Timing Chart

Rev. 1.40 �4 ��st �� 01� Rev. 1.40 �5 ��st �� 01�


Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF RESET Conditions0 0 Power-on reset� � RES or LVR reset d�rin� NORM�L or SLOW Mode operation1 � WDT time-o�t reset d�rin� NORM�L or SLOW Mode operation1 1 WDT time-o�t reset d�rin� IDLE or SLEEP Mode operation

“�” stands for �nchan�edThefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETPro�ram Co�nter Reset to zeroInterr�pts �ll interr�pts will be disabledWDT� Time Base Clear after reset� WDT be�ins co�ntin�Timer Mod�les Timer Mod�les will be t�rned offInp�t/O�tp�t Ports I/O ports will be set�p as inp�tsStack Pointer Stack Pointer will point to the top of the stack

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectsthemicrocontrollerinternalregisters.

Register Reset Status Table

RegisterH

T66F60A

HT66F70A

Power-on Reset RES or LVR Reset WDT Time-out(Normal Operation)

WDT Time-out(HALT)

I�R0 ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �MP0 ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �I�R1 ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �MP1L ● ● 0 0 0 0 0 0 0 0 � � � � � � � � � � � � � � � � � � � � � � � �MP1H ● ● 0 0 0 0 0 0 0 0 � � � � � � � � � � � � � � � � � � � � � � � �I�R� ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �MP�L ● ● 0 0 0 0 0 0 0 0 � � � � � � � � � � � � � � � � � � � � � � � �MP�H ● ● 0 0 0 0 0 0 0 0 � � � � � � � � � � � � � � � � � � � � � � � ��CC ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �PCL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TBLP ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �TBLH ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �TBHP ● - - x x x x x x - - � � � � � � - - � � � � � � - - � � � � � �TBHP ● - x x x x x x x - � � � � � � � - � � � � � � � - � � � � � � �

ST�TUS ● ● x x 0 0 x x x x � � � � � � � � � � 1 � � � � � � � 11 � � � �BP ● - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - �BP ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �

Rev. 1.40 �4 ��st �� 01� Rev. 1.40 �5 ��st �� 01�


Register

HT66F60A

HT66F70A


WDT Time-out(HALT)

P�WU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �P�PU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �

P� ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �P�C ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �

PBPU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PB ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �

PBC ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PCPU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �

PC ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PCC ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �

PDPU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PD ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �

PDC ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PEPU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �

PE ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PEC ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �

PFPU ● ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - � � � � � � �PF ● ● - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - � � � � � � �

PFC ● ● - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - � � � � � � �PGPU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �

PG ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PGC ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �

PHPU ● ● - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - � � � � � �PH ● ● - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - � � � � � �

PHC ● ● - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - � � � � � �INTEG ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �INTC0 ● ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - � � � � � � �INTC1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �INTC� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �INTC3 ● ● - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - � � � - � � �MFI0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �MFI1 ● ● - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - � � � - � � �MFI� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �MFI3 ● ● - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - � � � - � � �MFI4 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �

SMOD ● ● 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 � � � � � � � �SMOD1 ● ● 0 - - - - x 0 0 0 - - - - 1 � � 0 - - - - � � � � - - - - � � �SMOD� ● ● - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - �LVRC ● ● 0 1 0 1 0 1 0 1 � � � � � � � � 0 1 0 1 0 1 0 1 � � � � � � � �LVDC ● ● - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - � � - � � �WDTC ● ● 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 � � � � � � � �EE� ● ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - � � � � � � �EED ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �

CP0C ● ● - 0 0 0 - - - 1 - 0 0 0 - - - 1 - 0 0 0 - - - 1 - � � � - - - �CP1C ● ● - 0 0 0 - - - 1 - 0 0 0 - - - 1 - 0 0 0 - - - 1 - � � � - - - �

Rev. 1.40 �6 ��st �� 01� Rev. 1.40 �� st �� 01�


Register

HT66F60A

HT66F70A


WDT Time-out(HALT)

TM1C0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM1C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM1C� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM1DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM1DH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM1�L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM1�H ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM1BL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM1BH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM�C0 ● ● 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - � � � � � - - -TM�C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM�DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM�DH ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM��L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM��H ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM�RP ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM3C0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM3C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM3DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM3DH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM3�L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM3�H ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM0C0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TMnC1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM0DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM0DH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM0�L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM0�H ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �PSC0 ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TBC0 ● ● 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 � - - - - � � �TBC1 ● ● 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 � - - - - � � �PSC1 ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �

�DCR0 ● ● 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 � � � � � � � ��DCR1 ● ● - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - � � � - � � ��DRL

(�DRFS=0) ● ● x x x x - - - - x x x x - - - - x x x x - - - - � � � � - - - -

�DRL(�DRFS=1) ● ● x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � �

�DRH(�DRFS=0) ● ● x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � �

�DRH(�DRFS=1) ● ● - - - - x x x x - - - - x x x x - - - - x x x x - - - - � � � �

SIMC0 ● ● 1 1 1 - 0 0 0 - 1 1 1 - 0 0 0 - 1 1 1 - 0 0 0 - � � � - � � � -SIMC1 ● ● 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 � � � � � � � �SIMD ● ● x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � �

Rev. 1.40 �6 ��st �� 01� Rev. 1.40 �� st �� 01�


Register

HT66F60A

HT66F70A


WDT Time-out(HALT)

SIMC�/SIM� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �

I�CTOC ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �SPI�C0 ● ● 1 1 1 - - - 0 - 1 1 1 - - - 0 - 1 1 1 - - - 0 - � � � - - - � -SPI�C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �SPI�D ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �F�RL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �F�RH ● - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - � � � � � �F�RH ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - � � � � � � �FD0L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �FD0H ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �FD1L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �FD1H ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �FD�L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �FD�H ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �FD3L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �FD3H ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TBC� ● ● 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 � - - - - � � �

SCOMC ● ● 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - � � � � - - - -EEC ● ● - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - � � � �FC0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �FC1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �FC� ● ● - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - �IFS0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �IFS1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �IFS� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �IFS3 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �IFS4 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �IFS5 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �

TM4C0 ● ● 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - � � � � � - - -TM4C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM4DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM4DH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM4�L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM4�H ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM4RP ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM5C0 ● ● 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - � � � � � - - -TM5C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM5DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM5DH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM5�L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM5�H ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM5RP ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �P�S0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �P�S1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �

Rev. 1.40 �� st �� 01� Rev. 1.40 �9 ��st �� 01�


Register

HT66F60A

HT66F70A


WDT Time-out(HALT)

P�S� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �P�S3 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PBS� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PBS3 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PCS0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PCS1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PCS� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PCS3 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PDS0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PDS1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PDS� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PDS3 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PES0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PES1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PES� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PES3 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PFS0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PGS0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PGS1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PGS� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PGS3 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PHS0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PHS1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PHS� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �

Note:“-”notimplement“u”means“unchanged”“x”means“unknown”

Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thesedevicesprovidebidirectional input/output lineslabeledwithportnamesPA~PHTheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

Rev. 1.40 �� st �� 01� Rev. 1.40 �9 ��st �� 01�


I/O Port Register List

Register Name

Bit

7 6 5 4 3 2 1 0P�WU P�WU� P�WU6 P�WU5 P�WU4 P�WU3 P�WU� P�WU1 P�WU0P�PU P�PU� P�PU6 P�PU5 P�PU4 P�PU3 P�PU� P�PU1 P�PU0

P� P�� P�6 P�5 P�4 P�3 P�� P�1 P�0P�C P�C� P�C6 P�C5 P�C4 P�C3 P�C� P�C1 P�C0

PBPU PBPU� PBPU6 PBPU5 PBPU4 PBPU3 PBPU� PBPU1 PBPU0PB PB� PB6 PB5 PB4 PB3 PB� PB1 PB0

PBC PBC� PBC6 PBC5 PBC4 PBC3 PBC� PBC1 PBC0PCPU PCPU� PCPU6 PCPU5 PCPU4 PCPU3 PCPU� PCPU1 PCPU0

PC PC� PC6 PC5 PC4 PC3 PC� PC1 PC0PCC PCC� PCC6 PCC5 PCC4 PCC3 PCC� PCC1 PCC0

PDPU PDPU� PDPU6 PDPU5 PDPU4 PDPU3 PDPU� PDPU1 PDPU0PD PD� PD6 PD5 PD4 PD3 PD� PD1 PD0

PDC PDC� PDC6 PDC5 PDC4 PDC3 PDC� PDC1 PDC0PEPU PEPU� PEPU6 PEPU5 PEPU4 PEPU3 PEPU� PEPU1 PEPU0

PE PE� PE6 PE5 PE4 PE3 PE� PE1 PE0PEC PEC� PEC6 PEC5 PEC4 PEC3 PEC� PEC1 PEC0

PFPU — PFPU6 PFPU5 PFPU4 PFPU3 PFPU� PFPU1 PFPU0PF — PF6 PF5 PF4 PF3 PF� PF1 PF0

PFC — PFC6 PFC5 PFC4 PFC3 PFC� PFC1 PFC0PGPU PGPU� PGPU6 PGPU5 PGPU4 PGPU3 PGPU� PGPU1 PGPU0

PG PG� PG6 PG5 PG4 PG3 PG� PG1 PG0PGC PGC� PGC6 PGC5 PGC4 PGC3 PGC� PGC1 PGC0

PHPU — — PHPU5 PHPU4 PHPU3 PHPU� PHPU1 PHPU0PH — — PH5 PH4 PH3 PH� PH1 PH0

PHC — — PHC5 PHC4 PHC3 PHC� PHC1 PHC0

“—”:Unimplemented,readas“0”PAWUn:PAwake-upfunctioncontrol

0:Disable1:Enable

PAn/PBn/PCn/PDn/PEn/PFn/PGn/PHn:I/ODatabit0:data01:data1

PACn/PBCn/PCCn/PDCn/PECn/PFCn/PGCn/PHCn:I/Otypeselection0:Output1:input

PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn/PGPUn/PHPUn:Pull-highfunctioncontrol0:Disable1:Enable

Rev. 1.40 �0 ��st �� 01� Rev. 1.40 �1 ��st �� 01�


Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregistersPAPU~PHPU,andare implementedusingweakPMOStransistors.

Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

PAWU Register

Bit 7 6 5 4 3 2 1 0Name P�WU� P�WU6 P�WU5 P�WU4 P�WU3 P�WU� P�WU1 P�WU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 PAWU:PortAbit7~bit0Wake-upControl0:Disable1:Enable

I/O Port Control RegistersEachPorthas itsowncontrol register,knownasPAC~PHC,whichcontrols the input/outputconfiguration.With thiscontrolregister,eachI/Opinwithorwithoutpull-highresistorscanbereconfigureddynamicallyunder softwarecontrol.For the I/Opin to functionasan input, thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.

However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forthesepins,thechosenfunctionofthemulti-functionI/Opinsisselectedbyaseriesofregitersviatheapplicationprogramcontrol.

Pin-shared Function Selection RegisterThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.Thedevice includesPort“x”outputfunctionslsectionregister“n”,labeledasPxSn,andinputfunctionselectionregister“i”, labeledasIFSi,whichcan

Rev. 1.40 �0 ��st �� 01� Rev. 1.40 �1 ��st �� 01�


selectthefunctionsofthepin-sharedfunctionpins.

When thepin-shared input function isselected tobeused, thecorresponding inputandoutputfunctionsselectionshouldbeproperlymanaged.Forexample, if the I2CSDAline isused, thecorrespondingoutputpin-shared function shouldbeconfiguredas theSDI/SDAfunctionbyconfiguring thePxSnregisterand theSDAsignal intputshouldbeproperlyselectedusing theIFSiregister.However,iftheexternalinterruptfunctionisselectedtobeused,therelevantoutputpin-sharedfunctionshouldbeselectedasanI/Ofunctionandtheinterruptinputsignalshouldbeselected.

Register Name

Bit

7 6 5 4 3 2 1 0P�S0 P�1S3 P�1S� P�1S1 P�1S0 D3 D� D1 D0P�S1 P�3S3 P�3S� P�3S1 P�3S0 D3 D� D1 D0P�S� P�5S3 P�5S� P�5S1 P�5S0 P�4S3 P�4S� P�4S1 P�4S0P�S3 P��S3 P��S� P��S1 P��S0 P�6S3 P�6S� P�6S1 P�6S0PBS� PB5S3 PB5S� PB5S1 PB5S0 D3 D� D1 D0PBS3 PB�S3 PB�S� PB�S1 PB�S0 PB6S3 PB6S� PB6S1 PB6S0PCS0 PC1S3 PC1S� PC1S1 PC1S0 PC0S3 PC0S� PC0S1 PC0S0PCS1 PC3S3 PC3S� PC3S1 PC3S0 PC�S3 PC�S� PC�S1 PC�S0PCS� PC5S3 PC5S� PC5S1 PC5S0 PC4S3 PC4S� PC4S1 PC4S0PCS3 PC�S3 PC�S� PC�S1 PC�S0 PC6S3 PC6S� PC6S1 PC6S0PDS0 PD1S3 PD1S� PD1S1 PD1S0 PD0S3 PD0S� PD0S1 PD0S0PDS1 PD3S3 PD3S� PD3S1 PD3S0 PD�S3 PD�S� PD�S1 PD�S0PDS� PD5S3 PD5S� PD5S1 PD5S0 PD4S3 PD4S� PD4S1 PD4S0PDS3 PD�S3 PD�S� PD�S1 PD�S0 PD6S3 PD6S� PD6S1 PD6S0PES0 PE1S3 PE1S� PE1S1 PE1S0 PE0S3 PE0S� PE0S1 PE0S0PES1 PE3S3 PE3S� PE3S1 PE3S0 D3 D� D1 D0PES� PE5S3 PE5S� PE5S1 PE5S0 PE4S3 PE4S� PE4S1 PE4S0PES3 PE�S3 PD�S� PE�S1 PE�S0 PE6S3 PE6S� PE6S1 PE6S0PFS0 PF1S3 PF1S� PF1S1 PF1S0 PF0S3 PF0S� PF0S1 PF0S0PGS0 PG1S3 PG1S� PG1S1 PG1S0 PG0S3 PG0S� PG0S1 PG0S0PGS1 PG3S3 PG3S� PG3S1 PG3S0 D3 D� D1 D0PGS� D� D6 D5 D4 PG4S3 PG4S� PG4S1 PG4S0PGS3 PG�S3 PG�S� PG�S1 PG�S0 PG6S3 PG6S� PG6S1 PG6S0PHS0 PH1S3 PH1S� PH1S1 PH1S0 PH0S3 PH0S� PH0S1 PH0S0PHS1 PH3S3 PH3S� PH3S1 PH3S0 PH�S3 PH�S� PH�S1 PH�S0PHS� PH5S3 PH5S� PH5S1 PH5S0 D3 D� D1 D0IFS0 PINTBS1 PINTBS0 INT�S1 INT�S0 INT1S1 INT1S0 INT0S1 INT0S0IFS1 TCK3S1 TCK3S0 TCK�S1 TCK�S0 TCK1S1 TCK1S0 TCK0S1 TCK0S0IFS� TP�IS1 TP�IS0 TP1IBS1 TP1IBS0 TP1I�S1 TP1I�S0 D1 D0IFS3 D� D6 TP5IS1 TP5IS0 TP4IS1 TP4IS0 D1 D0IFS4 D� D6 SDIS1 SDIS0 SCKS1 SCKS0 SCSBS1 SCSBS0IFS5 D� D6 SDI�S1 SDI�S0 SCK�S1 SCK�S0 SCS�BS1 SCS�BS0

Rev. 1.40 �� st �� 01� Rev. 1.40 �3 ��st �� 01�


• PAS0

Bit 7 6 5 4 3 2 1 0Name P�1S3 P�1S� P�1S1 P�1S0 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PA1S3~PA1S0:PortA1FunctionSelection0000:I/O0001:TP1A0011:AN1Others:Reserved

Bit3~0 Reservedbits,canbereadandwritten

• PAS1

Bit 7 6 5 4 3 2 1 0Name P�3S3 P�3S� P�3S1 P�3S0 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PA3S3~PA3S0:PortA3FunctionSelection0000:I/O0011:AN30111:C0N1111:AN3andC0NOthers:Reserved


• PAS2

Bit 7 6 5 4 3 2 1 0Name P�5S3 P�5S� P�5S1 P�5S0 P�4S3 P�4S� P�4S1 P�4S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PA5S3~PA5S0:PortA5FunctionSelection0000:I/O0001:SDO0010:C1X0011:AN5Others:Reserved

Bit3~0 PA4S3~PA4S0:PortA4FunctionSelection0000:I/O0011:AN4Others:Reserved

Rev. 1.40 �� st �� 01� Rev. 1.40 �3 ��st �� 01�


• PAS3

Bit 7 6 5 4 3 2 1 0Name P��S3 P��S� P��S1 P��S0 P�6S3 P�6S� P�6S1 P�6S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PA7S3~PA7S0:PortA7FunctionSelection0000:I/O0010:SCK/SCL0011:AN7Others:Reserved

Bit3~0 PA6S3~PA6S0:PortA6FunctionSelection0000:I/O0010:SDI/SDA0011:AN6Others:Reserved

• PBS2

Bit 7 6 5 4 3 2 1 0Name PB5S3 PB5S� PB5S1 PB5S0 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PB5S3~PB5S0:PortB5FunctionSelection0000:I/O0001:SCSOthers:Reserved


• PBS3

Bit 7 6 5 4 3 2 1 0Name PB�S3 PB�S� PB�S1 PB�S0 PB6S3 PB6S� PB6S1 PB6S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PB7S3~PB7S0:PortB7FunctionSelection0000:I/O0010:SDI/SDAOthers:Reserved

Bit3~0 PB6S3~PB6S0:PortB6FunctionSelection0000:I/O0001:SDOOthers:Reserved

Rev. 1.40 �4 ��st �� 01� Rev. 1.40 �5 ��st �� 01�


• PCS0

Bit 7 6 5 4 3 2 1 0Name PC1S3 PC1S� PC1S1 PC1S0 PC0S3 PC0S� PC0S1 PC0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PC1S3~PC1S0:PortC1FunctionSelection0000:I/O0001:TP1B0010:TP1BB0011:SCOM1Others:Reserved

Bit3~0 PC0S3~PC0S0:PortC0FunctionSelection0000:I/O0001:TP1B0010:TP1BB0011:SCOM0Others:Reserved

• PCS1

Bit 7 6 5 4 3 2 1 0Name PC3S3 PC3S� PC3S1 PC3S0 PC�S3 PC�S� PC�S1 PC�S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PC3S3~PC3S0:PortC3FunctionSelection0000:I/O0001:TP20010:C1X0100:TP1BOthers:Reserved

Bit3~0 PC2S3~PC2S0:PortC2FunctionSelection0000:I/O0001:PCK0010:C0XOthers:Reserved

• PCS2

Bit 7 6 5 4 3 2 1 0Name PC5S3 PC5S� PC5S1 PC5S0 PC4S3 PC4S� PC4S1 PC4S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PC5S3~PC5S0:PortC5FunctionSelection0000:I/O0001:PCK0010:TP00100:TP1B0101:TP0B0110:TP1BBOthers:Reserved

Bit3~0 PC4S3~PC4S0:PortC4FunctionSelection0000:I/O0001:TP20010:TP2BOthers:Reserved

Rev. 1.40 �4 ��st �� 01� Rev. 1.40 �5 ��st �� 01�


• PCS3

Bit 7 6 5 4 3 2 1 0Name PC�S3 PC�S� PC�S1 PC�S0 PC6S3 PC6S� PC6S1 PC6S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PC7S3~PC7S0:PortC7FunctionSelection0000:I/O0001:TP1A0011:SCOM3Others:Reserved

Bit3~0 PC6S3~PC6S0:PortC6FunctionSelection0000:I/O0001:TP00010:TP0B0011:SCOM2Others:Reserved

• PDS0

Bit 7 6 5 4 3 2 1 0Name PD1S3 PD1S� PD1S1 PD1S0 PD0S3 PD0S� PD0S1 PD0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PD1S3~PD1S0:PortD1FunctionSelection0000:I/O0001:TP20010:SCK/SCL0100:SDO0101:TP2BOthers:Reserved

Bit3~0 PD0S3~PD0S0:PortD0FunctionSelection0000:I/O0001:TP30010:SCS0100:TP3BOthers:Reserved

• PDS1

Bit 7 6 5 4 3 2 1 0Name PD3S3 PD3S� PD3S1 PD3S0 PD�S3 PD�S� PD�S1 PD�S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PD3S3~PD3S0:PortD3FunctionSelection0000:I/O0001:TP30010:SCK/SCL0100:SDO0101:TP3BOthers:Reserved

Bit3~0 PD2S3~PD2S0:PortD2FunctionSelection0000:I/O0010:SDI/SDAOthers:Reserved

Rev. 1.40 �6 ��st �� 01� Rev. 1.40 �� st �� 01�


• PDS2

Bit 7 6 5 4 3 2 1 0Name PD5S3 PD5S� PD5S1 PD5S0 PD4S3 PD4S� PD4S1 PD4S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PD5S3~PD5S0:PortD5FunctionSelection0000:I/O0001:TP00010:TP0BOthers:Reserved

Bit3~0 PD4S3~PD4S0:PortD4FunctionSelection0000:I/O0001:TP20010:TP2BOthers:Reserved

• PDS3

Bit 7 6 5 4 3 2 1 0Name PD�S3 PD�S� PD�S1 PD�S0 PD6S3 PD6S� PD6S1 PD6S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PD7S3~PD7S0:PortD7FunctionSelection0000:I/O0001:SCSOthers:Reserved

Bit3~0 PD6S3~PD6S0:PortD6FunctionSelection0000:I/O0010:SCK/SCLOthers:Reserved

• PES0

Bit 7 6 5 4 3 2 1 0Name PE1S3 PE1S� PE1S1 PE1S0 PE0S3 PE0S� PE0S1 PE0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PE1S3~PE1S0:PortE1FunctionSelection0000:I/O0001:SCKAOthers:Reserved

Bit3~0 PE0S3~PE0S0:PortE0FunctionSelection0000:I/O0001:SCSAOthers:Reserved

Rev. 1.40 �6 ��st �� 01� Rev. 1.40 �� st �� 01�


• PES1

Bit 7 6 5 4 3 2 1 0Name PE3S3 PE3S� PE3S1 PE3S0 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PE3S3~PE3S0:PortE3FunctionSelection0000:I/O0001:SDOAOthers:Reserved

Bit3~0 Reservedbits,canbereadandwritten.

• PES2

Bit 7 6 5 4 3 2 1 0Name PE5S3 PE5S� PE5S1 PE5S0 PE4S3 PE4S� PE4S1 PE4S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PE5S3~PE5S0:PortE5FunctionSelection0000:I/O0001:TP30010:TP3BOthers:Reserved

Bit3~0 PE4S3~PE4S0:PortE4FunctionSelection0000:I/O0001:TP1B0010:TP1BBOthers:Reserved

• PES3

Bit 7 6 5 4 3 2 1 0Name PE�S3 PE�S� PE�S1 PE�S0 PE6S3 PE6S� PE6S1 PE6S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PE7S3~PE7S0:PortE7FunctionSelection0000:I/O0011:AN9Others:Reserved

Bit3~0 PE6S3~PE6S0:PortE6FunctionSelection0000:I/O0011:AN8Others:Reserved

Rev. 1.40 �� st �� 01� Rev. 1.40 �9 ��st �� 01�


• PFS0

Bit 7 6 5 4 3 2 1 0Name PF1S3 PF1S� PF1S1 PF1S0 PF0S3 PF0S� PF0S1 PF0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PF1S3~PF1S0:PortF1FunctionSelection0000:I/O0011:AN110111:C1P1111:AN11andC1POthers:Reserved

Bit3~0 PF0S3~PF0S0:PortF0FunctionSelection0000:I/O0011:AN100111:C1N1111:AN10andC1NOthers:Reserved

• PGS0

Bit 7 6 5 4 3 2 1 0Name PG1S3 PG1S� PG1S1 PG1S0 PG0S3 PG0S� PG0S1 PG0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PG1S3~PG1S0:PortG1FunctionSelection0000:I/O0001:C1XOthers:Reserved

Bit3~0 PG0S3~PG0S0:PortG0FunctionSelection0000:I/O0001:C0XOthers:Reserved

• PGS1

Bit 7 6 5 4 3 2 1 0Name PG3S3 PG3S� PG3S1 PG3S0 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PG3S3~PG3S0:PortG3FunctionSelection0000:I/O0001:TP40010:TP4BOthers:Reserved


Rev. 1.40 �� st �� 01� Rev. 1.40 �9 ��st �� 01�


• PGS2

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 PG4S3 PG4S� PG4S1 PG4S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 Reservedbits,canbereadandwritten.Bit3~0 PG4S3~PG4S0:PortG4FunctionSelection

0000:I/O0001:TP40010:TP4BOthers:Reserved

• PGS3

Bit 7 6 5 4 3 2 1 0Name PG�S3 PG�S� PG�S1 PG�S0 PG6S3 PG6S� PG6S1 PG6S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0



• PHS0

Bit 7 6 5 4 3 2 1 0Name PH1S3 PH1S� PH1S1 PH1S0 PH0S3 PH0S� PH0S1 PH0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PH1S3~PH1S0:PortH1FunctionSelection0000:I/O0011:AN20111:C0P1111:AN2andC0POthers:Reserved

Bit3~0 PH0S3~PH0S0:PortH0FunctionSelection0000:I/O0001:TP00010:C0X0011:AN0/VREF0100:TP0BOthers:Reserved

Rev. 1.40 90 ��st �� 01� Rev. 1.40 91 ��st �� 01�


• PHS1

Bit 7 6 5 4 3 2 1 0Name PH3S3 PH3S� PH3S1 PH3S0 PH�S3 PH�S� PH�S1 PH�S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PH3S3~PH3S0:PortH3FunctionSelection0000:I/O0001:SCKAOthers:Reserved

Bit3~0 PH2S3~PH2S0:PortH2FunctionSelection0000:I/O0001:SCSAOthers:Reserved

• PHS2

Bit 7 6 5 4 3 2 1 0Name PH5S3 PH5S� PH5S1 PH5S0 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~4 PH5S3~PH5S0:PortH5FunctionSelection0000:I/O0001:SDOAOthers:Reserved


• IFS0

Bit 7 6 5 4 3 2 1 0Name PINTBS1 PINTBS0 INT�S1 INT�S0 INT1S1 INT1S0 INT0S1 INT0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PINTBS1~PINTBS0:PINTinputsourcepinselection00:PC3Others:PC4

Bit5~4 INT2S1~INT2S0:INT2inputsourcepinselection00:PC4Others:PE2

Bit3~2 INT1S1~INT1S0:INT1inputsourcepinselection00:PA401:PC510:PE111:PE7

Bit1~0 INT0S1~INT0S0:INT0inputsourcepinselection00:PA301:PC410:PE011:PE6

Rev. 1.40 90 ��st �� 01� Rev. 1.40 91 ��st �� 01�


• IFS1

Bit 7 6 5 4 3 2 1 0Name TCK3S1 TCK3S0 TCK�S1 TCK�S0 TCK1S1 TCK1S0 TCK0S1 TCK0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 TCK3S1~TCK3S0:TCK3inputsourcepinselection00:PC4Others:PE3

Bit5~4 TCK2S1~TCK2S0:TCK2inputsourcepinselection00:PC2Others:PD0

Bit3~2 TCK1S1~TCK1S0:TCK1inputsourcepinselection00:PA4Others:PD3

Bit1~0 TCK0S1~TCK0S0:TCK0inputsourcepinselection00:PH1Others:PD2

• IFS2

Bit 7 6 5 4 3 2 1 0Name TP�IS1 TP�IS0 TP1IBS1 TP1IBS0 TP1I�S1 TP1I�S0 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 TP2IS1~TP2IS0:TP2Iinputsourcepinselection00:PC301:PC410:PD111:PD4

Bit5~4 TP1IBS1~TP1IBS0:TP1IBinputsourcepinselection00:PC001:PC110:PC511:PE4

Bit3~2 TP1IAS1~TP1IAS0:TP1IAinputsourcepinselection00:PA1Others:PC7


• IFS3

Bit 7 6 5 4 3 2 1 0Name D� D6 TP5IS1 TP5IS0 TP4IS1 TP4IS0 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 Reservedbits,canbereadandwritten.Bit5~4 TP5IS1~TP5IS0:TP5Iinputsourcepinselection

00:PG6Others:PG7

Bit3~2 TP4IS1~TP4IS0:TP4Iinputsourcepinselection00:PG3Others:PG4


Rev. 1.40 9� ��st �� 01� Rev. 1.40 93 ��st �� 01�


• IFS4

Bit 7 6 5 4 3 2 1 0Name D� D6 SDIS1 SDIS0 SCKS1 SCKS0 SCSBS1 SCSBS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 Reservedbits,canbereadandwritten.Bit5~4 SDIS1~SDIS0:SDI/SDAinputsourcepinselection

00:PA601:PB7Others:PD2

Bit3~2 SCKS1~SCKS0:SCK/SCLinputsourcepinselection00:PA701:PD310:PD111:PD6

Bit1~0 SCSBS1~SCSBS0:SCSinputsourcepinselection00:PB501:PD0Others:PD7

• IFS5

Bit 7 6 5 4 3 2 1 0Name D� D6 SDI�S1 SDI�S0 SCK�S1 SCK�S0 SCS�BS1 SCS�BS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 Reservedbits,canbereadandwritten.Bit5~4 SDIAS1~SDIAS0:SDIAinputsourcepinselection

00:PE2Others:PH4

Bit3~2 SCKAS1~SCKAS0:SCKAinputsourcepinselection00:PE1Others:PH3

Bit1~0 SCSABS1~SCSABS0:SCSAinputsourcepinselection00:PE0Others:PH2

Rev. 1.40 9� ��st �� 01� Rev. 1.40 93 ��st �� 01�


I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

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Generic Input/Output Structure

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A/D Input/Output Structure

Rev. 1.40 94 ��st �� 01� Rev. 1.40 95 ��st �� 01�


Programming ConsiderationsWithintheuserprogram,oneof thethingsfirst toconsider isport initialisation.Afterareset,allof theI/Odataandportcontrolregisterswillbeset tohigh.ThismeansthatallI/Opinswillbedefaultedtoaninputstate,thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.If theportcontrolregistersarethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregistersarefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbitsintheportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdevicesistheabilitytocontrolandmeasuretime.Toimplement timerelatedfunctionseachdeviceincludesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeing the functionalunit for thegenerationofPWMsignals.Eachof theTMshaseithermultipleinterrupts.TheadditionofinputandoutputpinsforeachTMensuresthatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividualCompactandStandardTMsections.

IntroductionThedevicescontainfromtwotosixTMsdependinguponwhichdeviceisselectedwitheachTMhavingareferencenameofTM0~TM5.EachindividualTMcanbecategorisedasacertaintype,namelyCompactTypeTM,StandardTypeTMorEnhancedTypeTM.Althoughsimilarinnature,thedifferentTMtypesvaryintheirfeaturecomplexity.ThecommonfeaturestoalloftheCompact,StandardandEnhancedTMswillbedescribedinthissection,thedetailedoperationregardingeachoftheTMtypeswillbedescribedinseparatesections.ThemainfeaturesanddifferencesbetweenthethreetypesofTMsaresummarisedintheaccompanyingtable.

TM Function CTM STM ETMTimer/Co�nter √ √ √I/P Capt�re — √ √Compare Match O�tp�t √ √ √PWM Channels 1 1 �Sin�le P�lse O�tp�t — 1 �PWM �li�nment Ed�e Ed�e Ed�e & CentrePWM �dj�stment Period & D�ty D�ty or Period D�ty or Period D�ty or Period

TM Function Summary

Rev. 1.40 94 ��st �� 01� Rev. 1.40 95 ��st �� 01�


EachdeviceintheseriescontainsaspecificnumberofeitherCompactType,StandardTypeandEnhancedTypeTMunitwhichareshowninthetabletogetherwiththeirindividualreferencename,TM0~TM5.

Device TM0 TM1 TM2 TM3 TM4 TM5HT66F60�

10-bit CTM 10-bit ETM 16-bit STM 10-bit CTM 16-bit STM 16-bit STMHT66F�0�

TM Name/Type Reference

TM OperationThedifferent typesofTMofferadiverserangeof functions, fromsimple timingoperations toPWMsignalgeneration.ThekeytounderstandinghowtheTMoperates is tosee it in termsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

TM Clock SourceTheclocksourcewhichdrivesthemaincounterineachTMcanoriginatefromvarioussources.Theselectionof therequiredclocksourceis implementedusingtheTnCK2~TnCK0bits intheTMncontrolregisters.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH,thefSUBclocksourceortheexternalTCKnpin.Notethatsettingthesebitstothevalue101willselectareservedclockinput,ineffectdisconnectingtheTMclocksource.TheTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.

TM InterruptsTheCompact typeTMhas two internal interrupts,one foreachof the internalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.AstheEnhanced typeTMhas three internal comparatorsandcomparatorAorcomparatorBorcomparatorPcomparematchfunctions, itconsequentlyhasthreeinternalinterrupts.WhenaTMinterrupt isgenerateditcanbeusedtoclear thecounterandalso tochangethestateof theTMoutputpin.

Rev. 1.40 96 ��st �� 01� Rev. 1.40 9� ��st �� 01�


TM External PinsEachoftheTMs,irrespectiveofwhattype,hastwoTMinputpins,withthelabelTCKnandTPnIrespectively.TheTMinputpin,TCKn,isessentiallyaclocksourcefortheTMandisselectedusingtheTnCK2~TnCK0bitsintheTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThisexternalTMinputpinissharedwithotherfunctionsbutwillbeconnectedtotheinternalTMifselectedusingtheTnCK2~TnCK0bits.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.TheTCKnpinisalsousedastheexternaltriggerinputpininsinglepulsemodefortheSTMandETM.

TheotherTMinputpin,TPnI,isthecaptureinputwhoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedgesandtheactiveedgetransitiontypeisselectedusingtheTnIO1andTnIO0bitsintheTMnC1register.

TheTMseachhaveoneormoreoutputpinswiththelabelTPnandTPnBrespectively.WhentheTMis intheCompareMatchOutputMode, thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalTPnoutputpin isalso thepinwhere theTMgenerates thePWMoutputwaveform.As theTMoutputpinsarepin-sharedwithotherfunction,theTMoutputfunctionmustfirstbesetupusingregisters.Thecorrespondingselectionbitsinthepin-sharedfunctionregistersdeterminesifitsassociatedpinistobeusedasanexternalTMoutputpinorifitistohaveanotherfunction.ThenumberofoutputpinsforeachTMtypeanddeviceisdifferent,thedetailsareprovidedintheaccompanyingtable.

Device CTM ETM STM Registers

HT66F60�HT66F�0�

TP0� TP0B� TCK0TP3� TP3B� TCK3

TP1�� TP1I�� TCK1TP1B� TP1BB� TP1IB

TP�� TP�B� TP�I� TCK�TP4� TP4B� TP4I� TCK4TP5� TP5B� TP5I� TCK5

IFSi

TM Input/Output Pins

Rev. 1.40 96 ��st �� 01� Rev. 1.40 9� ��st �� 01�


TM Input/Output Pin ControlSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingoneor two registers,with thecorrespondingselectionbits ineachpin-shared functionregistercorrespondingtoaTMinput/outputpin.ConfiguringtheselectionbitscorrectlywillsetupthecorrespondingpinasaTMinput/output.Thedetailsof thepin-sharedfunctionselectionaredescribedinthepin-sharedfunctionsection.

CTM(TMn)

TCKn

TPn

TPnB

CCR o�tp�t

CCR inverted o�tp�t

CTM Function Pin Control Block Diagram (n=0 or 3)

STM(TMn)

TCKn

TPn

TPnB

TPnICCR capt�re inp�t

CCR o�tp�t

CCR inverted o�tp�t

STM Function Pin Control Block Diagram (n=2, 4, 5)

ETM(TM1)

TCK1

TP1A

TP1IA

TP1B

TP1BB

TP1IB

CCR� capt�re inp�t

CCR� o�tp�t

CCRB capt�re inp�t

CCRB o�tp�t

CCRB inverted o�tp�t

ETM Function Pin Control Block Diagram

Rev. 1.40 9� ��st �� 01� Rev. 1.40 99 ��st �� 01�


Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAandCCRBregisters,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.

Data B�s

�-bit B�ffer

TMxDHTMxDL

TMxBHTMxBL

TMx�HTMx�L

TM Co�nter Re�ister (Read only)

TM CCR� Re�ister (Read/Write)

TM CCRB Re�ister (Read/Write)

AstheCCRAandCCRBregistersareimplementedinthewayshowninthefollowingdiagramandaccessingtheseregisterpairsiscarriedoutinaspecificwayasdescribedabove,itisrecommendedtousethe"MOV"instructiontoaccesstheCCRAandCCRBlowbyteregisters,namedTMxALandTMxBL,usingthefollowingaccessprocedures.AccessingtheCCRAorCCRBlowbyteregisterswithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRBorCCRA♦ Step1.WritedatatoLowByteTMxALorTMxBL

– notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighByteTMxAHorTMxBH

– heredata iswrittendirectly to thehighbyteregistersandsimultaneouslydata is latchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRBorCCRA♦ Step1.ReaddatafromtheHighByteTMxDH,TMxAHorTMxBH

– heredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowByteTMxDL,TMxALorTMxBL– thisstepreadsdatafromthe8-bitbuffer.

Rev. 1.40 9� ��st �� 01� Rev. 1.40 99 ��st �� 01�


Compact Type TM – CTMAlthoughthesimplestformofthetwoTMtypes,theCompactTMtypestillcontainsthreeoperatingmodes,whichareCompareMatchOutput,Timer/EventCounterandPWMOutputmodes.TheCompactTMcanalsobecontrolledwithanexternalinputpinandcandrivetwoexternaloutputpins.Thesetwoexternaloutputpinscanbethesamesignalortheinversesignal.

Device TM Type TM Name TM Input Pin TM Output PinHT66F60�HT66F�0� 10-bit CTM TM0� TM3 TCK0� TP0I; TCK3� TP3I TP0� TP0B; TP3� TP3B

� � � �

� � � �

� � � � � �

� � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � �

� � � � � � � � � �

� �

� � � � �

� � � � �

� � � � � � � � � � � � � � � � � � �

� � � �

� � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � ��

� � � � � � � � � � � � � �

� � � � � � � � � � � � � �

� � � � ��

� � � � � ��

� � � �

� � �

� � � � � � � ��

� � � � ��

� � �

� � �

� � �

� � ��

� � � � � ��

� � � � � � � � ��

Compact Type TM Block Diagram (n=0 or 3)

Compact TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.Thesecomparatorswillcompare thevalue in thecounterwithCCRPandCCRAregisters.TheCCRPisthreebitswidewhosevalueiscomparedwiththehighestthreebitsinthecounterwhiletheCCRAisthetenbitsandthereforecompareswithallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theTnONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheCompactTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Rev. 1.40 100 ��st �� 01� Rev. 1.40 101 ��st �� 01�


Compact Type TM Register DescriptionOveralloperationof theCompactTMiscontrolledusingsixregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitCCRAvalue.Theremaining tworegistersarecontrol registerswhichsetup thedifferentoperatingandcontrolmodesaswellasthethreeCCRPbits.

Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0TMnC0 TnP�U TnCK� TnCK1 TnCK0 TnON TnRP� TnRP1 TnRP0TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLRTMnDL D� D6 D5 D4 D3 D� D1 D0TMnDH — — — — — — D9 D�TMn�L D� D6 D5 D4 D3 D� D1 D0TMn�H — — — — — — D9 D�

Compact TM Register List (n=0 or 3)

TMnDL RegisterBit 7 6 5 4 3 2 1 0

Name D� D6 D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 TMnDL:TMnCounterLowByteRegisterbit7~bit0TMn10-bitCounterbit7~bit0

TMnDH RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D�R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TMnDH:TMnCounterHighByteRegisterbit1~bit0

TMn10-bitCounterbit9~bit8

TMnAL RegisterBit 7 6 5 4 3 2 1 0

Name D� D6 D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 TMnAL:TMnCCRALowByteRegisterbit7~bit0TMn10-bitCCRAbit7~bit0

TMnAH RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D�R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TMnAH:TMnCCRAHighByteRegisterbit1~bit0

TMn10-bitCCRAbit9~bit8

Rev. 1.40 100 ��st �� 01� Rev. 1.40 101 ��st �� 01�


TMnC0 Register

Bit 7 6 5 4 3 2 1 0Name TnP�U TnCK� TnCK1 TnCK0 TnON TnRP� TnRP1 TnRP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 TnPAU:TMnCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 TnCK2~TnCK0:SelectTM0Counterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:Reserved110:TCK0risingedgeclock111:TCK0fallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheTM.SelectingtheReservedclockinputwilleffectivelydisabletheinternalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYS isthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 TnON:TMnCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalue.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheTnOCbit,whentheTnONbitchangesfromlowtohigh.

Rev. 1.40 10� ��st �� 01� Rev. 1.40 103 ��st �� 01�


Bit2~0 TnRP2~TnRP0:TMnCCRP3-bitregister,comparedwiththeTMnCounterbit9~bit7ComparatorPMatchPeriod000:1024TMnclocks001:128TMnclocks010:256TMnclocks011:384TMnclocks100:512TMnclocks101:640TMnclocks110:768TMnclocks111:896TMnclocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter'shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theTnCCLRbit isset tozero.SettingtheTnCCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

TMnC1 Register

Bit 7 6 5 4 3 2 1 0Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 TnM1~TnM0:SelectTMnOperatingMode00:CompareMatchOutputMode01:Undefined10:PWMMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheTnM1andTnM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 TnIO1~TnIO0:SelectTPn,TPnBoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Undefined

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.

Rev. 1.40 10� ��st �� 01� Rev. 1.40 103 ��st �� 01�


IntheCompareMatchOutputMode,theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowor totoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheTnOCbit intheTMnC1register.NotethattheoutputlevelrequestedbytheTnIO1andTnIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheTnOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheTnONbitfromlowtohigh.In thePWMMode, theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits. It isnecessarytoonlychangethevaluesof theTnIO1andTnIO0bitsonlyafter theTMnhasbeen switchedoff.UnpredictablePWMoutputswilloccuriftheTnIO1andTnIO0bitsarechangedwhentheTMisrunning.

Bit3 TnOC:TPn,TPnBOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputMode itdetermines the logic levelofheTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesif thePWMsignal isactivehighoractivelow.

Bit2 TnPOL:TPn,TPnBOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTPnorTPnBoutputpin.WhenthebitissethightheTMoutputpinwillbe invertedandnot invertedwhenthebit iszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 TnDPX:TMnPWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 TnCCLR:SelectTMnCounterclearcondition0:TMnComparatorPmatch1:TMnComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theCompactTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheTnCCLRbitisnotusedinthePWMMode.

Rev. 1.40 104 ��st �� 01� Rev. 1.40 105 ��st �� 01�


Compact Type TM Operating ModesTheCompactTypeTMcanoperateinoneofthreeoperatingmodes,CompareMatchOutputMode,PWMModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnM1andTnM0bitsintheTMnC1register.

Compare Match Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1register,shouldbesetto“00”respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothTnAFandTnPFinterruptrequestflagsfortheComparatorAandComparatorPrespectively,willbothbegenerated.

IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,value,howeverheretheTnAFinterruptrequestflagwillnotbegenerated.

As thenameof themodesuggests,afteracomparison ismade, theTMoutputpinwillchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaTnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheTnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theTnIO1andTnIO0bitsintheTMnC1register.TheTMoutputpincanbeselectedusingtheTnIO1andTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theTnONbitchangesfromlowtohigh,issetupusingtheTnOCbit.NotethatiftheTnIO1andTnIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.40 104 ��st �� 01� Rev. 1.40 105 ��st �� 01�


Co�nter Val�e

0x3FF

CCRP

CCR�

TnON

TnP�U

TnPOL

CCRP Int. Fla� TnPF

CCR� Int. Fla� Tn�F

TM O/P Pin

Time

CCRP=0

CCRP > 0

Co�nter overflowCCRP > 0Co�nter cleared by CCRP val�e

Pa�se

Res�me

Stop

Co�nter Restart

TnCCLR = 0; TnM [1:0] = 00

O�tp�t pin set to initial Level Low if TnOC=0

O�tp�t To��le with Tn�F fla�

Note TnIO [1:0] = 10 �ctive Hi�h O�tp�t selectHere TnIO [1:0] = 11

To��le O�tp�t select

O�tp�t not affected by Tn�F fla�. Remains Hi�h �ntil reset by TnON bit

O�tp�t PinReset to Initial val�e

O�tp�t controlled by other pin-shared f�nction

O�tp�t Invertswhen TnPOL is hi�h

Compare Match Output Mode – TnCCLR=0

Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.n=0or3

Rev. 1.40 106 ��st �� 01� Rev. 1.40 10� ��st �� 01�


Co�nter Val�e

0x3FF

CCRP

CCR�

TnON

TnP�U

TnPOL



TM O/P Pin

Time

CCR�=0

CCR� = 0Co�nter overflowCCR� > 0 Co�nter cleared by CCR� val�e

Pa�se

Res�me

Stop Co�nter Restart

TnCCLR = 1; TnM [1:0] = 00

O�tp�t pin set to initial Level Low if TnOC=0


Note TnIO [1:0] = 10 �ctive Hi�h O�tp�t selectHere TnIO [1:0] = 11





O�tp�t Invertswhen TnPOL is hi�h

TnPF not �enerated

No Tn�F fla� �enerated on CCR� overflow

O�tp�t does not chan�e


Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.TheTnPFflagisnotgeneratedwhenTnCCLR=15.n=0or3

Rev. 1.40 106 ��st �� 01� Rev. 1.40 10� ��st �� 01�


Timer/Counter ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignalof fixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.In thePWMmode, theTnCCLRbithasnoeffectonthePWMoperation.Bothof theCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrol thedutycycle.Whichregister isusedtocontroleitherfrequencyordutycycle isdeterminedusing theTnDPXbit in theTMnC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheTnOCbitintheTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

CTM, PWM Mode, Edge-aligned Mode, TnDPX=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPeriod 1�� 56 3�4 51� 640 �6� �96 10�4D�ty CCR�

IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128,

TheCTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

CTM, PWM Mode, Edge-aligned Mode, TnDPX=1

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPeriod CCR�D�ty 1�� 56 3�4 51� 640 �6� �96 10�4

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.

Rev. 1.40 10� ��st �� 01� Rev. 1.40 109 ��st �� 01�


Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

TnPOL



TM O/P Pin(TnOC=1)

Time

Co�nter cleared by CCRP

Pa�se Res�me Co�nter Stop if TnON bit low

Co�nter Reset when TnON ret�rns hi�h

TnDPX = 0; TnM [1:0] = 10

PWM D�ty Cycle set by CCR�

PWM res�mes operation

O�tp�t controlled by other pin-shared f�nction O�tp�t Inverts

when TnPOL = 1PWM Period set by CCRP

TM O/P Pin(TnOC=0)

PWM Mode – TnDPX=0

Note: 1.HereTnDPX=0–CounterclearedbyCCRP2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0or3

Rev. 1.40 10� ��st �� 01� Rev. 1.40 109 ��st �� 01�


Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

TnPOL



TM O/P Pin(TnOC=1)

Time

Co�nter cleared by CCR�



TnDPX = 1; TnM [1:0] = 10

PWM D�ty Cycle set by CCRP



when TnPOL = 1PWM Period set by CCR�

TM O/P Pin(TnOC=0)


Note:1.HereTnDPX=1–CounterclearedbyCCRA2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0or3

Rev. 1.40 110 ��st �� 01� Rev. 1.40 111 ��st �� 01�


Standard Type TM – STMTheStandardTypeTMcontains fiveoperatingmodes,which areCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheStandardTMcanalsobecontrolledwithanexternalinputpinandcandriveoneortwoexternaloutputpins.

Device TM Type TM Name TM Input Pin TM Output Pin

HT66F60�HT66F�0� 16-bit STM TM�� TM4� TM5

TCK�� TP�I;TCK4� TP4I;TCK5� TP5I

TP�� TP�B;TP4� TP4B;TP5� TP5B

� � � �

� � � �

� � � � � �

� � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � �

� � � � � � � � � �

� � � � � � �

� � � � � �

� � � � � � � � � � � � � � � � � �

� � � � � � ��

� � � � � � � � � � � � ��

� � � � � � � � � � � � � �

� � � � � � � � � � � � � �

� � � � ��

� � � � � � �

� ��

� � � � � � � � � �

� � � � � � � � � ��

� � � �

� � �

� � � � � � � ��

� � � � ��

� � �

� � � �

� � � � � � �

� � ��

� � � � � ��

� � � � � � �

��

� � � �

Standard Type TM Block Diagram (n=2, 4 or 5)

Standard TM OperationThesizeofStandardTMis16-bitwide.Atthecoreisa16-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPcomparatoris8-bitwidewhosevalueiscomparedthewithhighest8bits in thecounterwhile theCCRAis thesixteenbitsandthereforecomparesallcounterbits.

Theonlywayofchanging thevalueof the16-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theTnONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Rev. 1.40 110 ��st �� 01� Rev. 1.40 111 ��st �� 01�


Standard Type TM Register DescriptionOveralloperationoftheStandardTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter16-bitvalue,whilearead/writeregisterpairexiststostoretheinternal16-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthethreeoreightCCRPbits.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TMnC0 TnP�U TnCK� TnCK1 TnCK0 TnON — — —TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLRTMnDL D� D6 D5 D4 D3 D� D1 D0TMnDH D15 D14 D13 D1� D11 D10 D9 D�TMn�L D� D6 D5 D4 D3 D� D1 D0TMn�H D15 D14 D13 D1� D11 D10 D9 D�TMnRP D� D6 D5 D4 D3 D� D1 D0

16-bit Standard TM Register List (n=2, 4 or 5)

TMnC0 Register

Bit 7 6 5 4 3 2 1 0Name TnP�U TnCK� TnCK1 TnCK0 TnON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —

Bit7 TnPAU:TMnCounterPauseControl0:Run1:Pause


Bit6~4 TnCK2, TnCK1, TnCK0:SelectTMnCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:Reserved110:TCKnrisingedgeclock111:TCKnfallingedgeclock


Rev. 1.40 11� ��st �� 01� Rev. 1.40 113 ��st �� 01�


Bit3 TnON:TMnCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheTnOCbit,whentheTnONbitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas“0”

TMnC1 Register

Bit 7 6 5 4 3 2 1 0Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 TnM1~TnM0:SelectTMnOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheTnM1andTnM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 TnIO1~TnIO0:SelectTPn,TPnBoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTPnI01:InputcaptureatfallingedgeofTPnI10:Inputcaptureatfalling/risingedgeofTPnI11:Inputcapturedisabled

Timer/counterMode:Unused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.

Rev. 1.40 11� ��st �� 01� Rev. 1.40 113 ��st �� 01�


IntheCompareMatchOutputMode,theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowor totoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheTnOCbit intheTMnC1register.NotethattheoutputlevelrequestedbytheTnIO1andTnIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheTnOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstate,itcanberesettoitsinitiallevelbychangingtheleveloftheTnONbitfromlowtohigh.In thePWMMode, theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.It isnecessarytochangethevaluesoftheTnIO1andTnIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurif theTnIO1andTnIO0bitsarechangedwhentheTMisrunning.

Bit3 TnOC:TPn,TPnBOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode/SinglePulseOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 TnPOL:TPn,TPnBOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTPnorTPnBoutputpin.WhenthebitissethightheTMoutputpinwillbe invertedandnot invertedwhenthebit iszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 TnDPX:TMnPWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 TnCCLR:SelectTMnCounterclearcondition0:TMnComparatorPmatch1:TMnComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheTnCCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.

Rev. 1.40 114 ��st �� 01� Rev. 1.40 115 ��st �� 01�


TMnDL RegisterBit 7 6 5 4 3 2 1 0

Name D� D6 D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 TMnDL:TMnCounterLowByteRegisterbit7~bit0TMn16-bitCounterbit7~bit0

TMnDH RegisterBit 7 6 5 4 3 2 1 0

Name D15 D14 D13 D1� D11 D10 D9 D�R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 TMnDH:TMnCounterHighByteRegisterbit7~bit0TMn16-bitCounterbit15~bit8

TMnAL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 TMnAL:TMnCCRALowByteRegisterbit7~bit0TMn16-bitCCRAbit7~bit0

TMnAH RegisterBit 7 6 5 4 3 2 1 0

Name D15 D14 D13 D1� D11 D10 D9 D�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 TMnAH:TMnCCRAHighByteRegisterbit7~bit0TMn16-bitCCRAbit15~bit8

TMnRP RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 TMnRP:TMnCCRPRegisterbit7~bit0TMnCCRP8-bitregister,comparedwiththeTMnCounterbit15~bit8.ComparatorPMatchPeriod0:65536TMnclocks1~255:256×(1~255)TMnclocks

TheseeightbitsareusedtosetupthevalueontheinternalCCRP8-bitregister,whichare thencomparedwith the internalcounter’shighesteightbits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theTnCCLRbit isset tozero.SettingtheTnCCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighesteightcounterbits, thecomparevaluesexist in256clockcyclemultiples.Clearingalleightbits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Rev. 1.40 114 ��st �� 01� Rev. 1.40 115 ��st �� 01�


Standard Type TM Operating ModesTheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnM1andTnM0bitsintheTMnC1register.

Compare Match Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP, theotheriswhentheCCRPbitsareallzerowhichallowsthecounter tooverflow.HerebothTnAFandTnPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto"0".

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenanTnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheTnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theTnIO1andTnIO0bitsintheTMnC1register.TheTMoutputpincanbeselectedusingtheTnIO1andTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theTnONbitchangesfromlowtohigh,issetupusingtheTnOCbit.NotethatiftheTnIO1andTnIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.40 116 ��st �� 01� Rev. 1.40 11� ��st �� 01�


CCR�

CCRP

0xFFFF

Co�nter overflow

CCR� Int.Fla� Tn�F

CCRP Int.Fla� TnPF

CCRP > 0Co�nter cleared by CCRP val�e

TM O/P Pin

TnON bit

Pa�se Co�nterReset

O�tp�t Pin set to Initial LevelLow if TnOC = 0

O�tp�t To��lewith Tn�F fla�

Here TnIO1� TnIO0 = 11To��le O�tp�t Select

Now TnIO1� TnIO0 = 10 �ctive Hi�h O�tp�t Select

O�tp�t not affected byTn�F fla�. Remains Hi�h�ntil reset by TnON bit

TnCCLR = 0; TnM[1:0] = 00

TnP�U bit

Res�meStop

Time

CCRP > 0

CCRP = 0

TnPOL bit

O�tp�t PinReset to initial val�e

O�tp�t invertswhen TnPOL is hi�h

O�tp�t controlledby other pin-shared f�nction

Co�nter Val�e


Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.n=2,4or5

Rev. 1.40 116 ��st �� 01� Rev. 1.40 11� ��st �� 01�


CCRP

CCR�

0xFFFF

CCR� = 0Co�nter overflows

CCRP Int.Fla� TnPF

CCR� Int.Fla� Tn�F

CCR� > 0 Co�nter cleared by CCR� val�e

TM O/P Pin

TnON bit

Pa�se Co�nterReset

O�tp�t PinReset to initial val�e

O�tp�t Pin set to Initial LevelLow if TnOC = 0

O�tp�t To��lewith Tn�F fla�

Here TnIO1� TnIO0 = 11To��le O�tp�t Select

Now TnIO1� TnIO0 = 10 �ctive Hi�h O�tp�t Select

TnP�U bit

Res�meStop

Time

TnPF not�enerated

No Tn�F fla��enerated on CCR� overflow

O�tp�t doesnot chan�e

CCR� = 0

O�tp�t invertswhen TnPOL is hi�h

TnPOL bit

TnCCLR = 1; TnM[1:0] = 00

O�tp�t controlled byother pin-shared f�nction

O�tp�t not affected byTn�F fla� remains Hi�h�ntil reset by TnON bit

Co�nter Val�e


Note: 1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.ATnPFflagisnotgeneratedwhenTnCCLR=15.n=2,4or5

Rev. 1.40 11� ��st �� 01� Rev. 1.40 119 ��st �� 01�



PWM Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectivelyandalso theTnIO1andTnIO0bitsshouldbeset to10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible. In thePWMmode, theTnCCLRbithasnoeffectas thePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.WhichregisterisusedtocontroleitherfrequencyordutycycleisdeterminedusingtheTnDPXbitintheTMnC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheTnOCbitintheTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0CCRP 1~255 0Period CCRP×�56 65536D�ty CCR�

IffSYS=16MHz,TMclocksourceselectfSYS/4,CCRP=2andCCRA=128,

TheSTMPWMoutputfrequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz,duty=128/(2×256)=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1CCRP 1~255 0Period CCR�D�ty CCRP×�56 65536

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbythe(CCRP×256)exceptwhentheCCRPvalueisequalto0.

Rev. 1.40 11� ��st �� 01� Rev. 1.40 119 ��st �� 01�


Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

TnPOL



TM O/P Pin(TnOC=1)

Time

Co�nter cleared by CCRP



TnDPX = 0; TnM [1:0] = 10

PWM D�ty Cycle set by CCR�



when TnPOL = 1PWM Period set by CCRP

TM O/P Pin(TnOC=0)


Note: 1.HereTnDPX=0,CounterclearedbyCCRP2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=2,4or5

Rev. 1.40 1�0 ��st �� 01� Rev. 1.40 1�1 ��st �� 01�


Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

TnPOL



TM O/P Pin(TnOC=1)

Time

Co�nter cleared by CCR�



TnDPX = 1; TnM [1:0] = 10

PWM D�ty Cycle set by CCRP



when TnPOL = 1PWM Period set by CCR�

TM O/P Pin(TnOC=0)


Note:1.HereTnDPX=1--CounterclearedbyCCRA2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=2,4or5

Rev. 1.40 1�0 ��st �� 01� Rev. 1.40 1�1 ��st �� 01�


Single Pulse ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectivelyandalsotheTnIO1andTnIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheTnONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,theTnONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalTCKnpin,whichwillinturninitiatetheSinglePulseoutput.WhentheTnONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheTnONbit isclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheTnONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaTMinterrupt.Thecountercanonlyberesetback tozerowhentheTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheTnCCLRandTnDPXbitsarenotusedinthisMode.

� � � � � � � � � � � �

� � � � � � � ��

� � � � � � � ��

� ��

� � � � � � � ��

� � � � � � � ��

� � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � �

� � � � � � � � � � � � � �

Single Pulse Generation

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�3 ��st �� 01�


Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

TnPOL



TM O/P Pin(TnOC=1)

Time

Co�nter stopped by CCR�

Pa�seRes�me Co�nter Stops

by software


TnM [1:0] = 10 ; TnIO [1:0] = 11

P�lse Width set by CCR�

O�tp�t Invertswhen TnPOL = 1

No CCRP Interr�pts �enerated

TM O/P Pin(TnOC=0)

TCKn pin

Software Tri��er

Cleared by CCR� match

TCKn pin Tri��er

��to. set by TCKn pin


Software Clear

Software Tri��erSoftware

Tri��er

Single Pulse Mode

Note:1.CounterstoppedbyCCRA2.CCRPisnotused3.ThepulsetriggeredbytheTCKnpinorbysettingtheTnONbithigh4.ATCKnpinactiveedgewillautomaticallysettheTnONbithigh.5.IntheSinglePulseMode,TnIO[1:0]mustbesetto“11”andcannotbechanged.6.n=2,4or5

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�3 ��st �� 01�


Capture Input ModeToselectthismodebitsTnM1andTnM0intheTMnC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheTPnIpin,whoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedges; theactiveedgetransitiontypeisselectedusingtheTnIO1andTnIO0bits intheTMnC1register.ThecounterisstartedwhentheTnONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.

WhentherequirededgetransitionappearsontheTPnIpinthepresentvalueinthecounterwillbelatchedintotheCCRAregistersandaTMinterruptgenerated.IrrespectiveofwhateventsoccurontheTPnIpinthecounterwillcontinuetofreerununtiltheTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccurs thecounterwill resetbacktozero; in thiswaytheCCRPvaluecanbeusedtocontrol themaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.Counting thenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheTnIO1andTnIO0bitscanselecttheactivetriggeredgeontheTPnIpintobearisingedge,fallingedgeorbothedgetypes.IftheTnIO1andTnIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheTPnIpin,howeveritmustbenotedthatthecounterwillcontinuetorun.

TheTnCCLRandTnDPXbitsarenotusedinthisMode.

Rev. 1.40 1�4 ��st �� 01� Rev. 1.40 1�5 ��st �� 01�


Counter Value

YY

CCRP

TnON

TnPAU

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

CCRA Value

Time

Counter cleared by CCRP

PauseResume

Counter Reset

TnM [1:0] = 01

TM capture pin TPnI

XX

Counter Stop

TnIO [1:0] Value

XX YY XX YY

Active edge Active

edgeActive edge

00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disable Capture

Capture Input Mode

Note:1.TnM[1:0]=01andactiveedgesetbytheTnIO[1:0]bits2.ATMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.TnCCLRbitnotused4.Nooutputfunction–TnOCandTnPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.6.n=2,4or5

Rev. 1.40 1�4 ��st �� 01� Rev. 1.40 1�5 ��st �� 01�


Enhanced Type TM – ETMTheEnhancedTypeTMcontains fiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheEnhancedTMcanalsobecontrolledwithanexternalinputpinandcandrivethreeorfourexternaloutputpins.

Device TM Type TM Name. TM Input Pin TM Output PinHT66F60� HT66F�0� 10-bit ETM TM1 TCK1; TP1I�� TP1IB TP1�; TP1B� TP1BB

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Enhanced Type TM Block Diagram (n=1)

Enhanced TM OperationAtitscoreisa10-bitcount-up/count-downcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Thereare three internalcomparatorswith thenames,ComparatorA,ComparatorBandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwiththeCCRA,CCRBandCCRPregisters.TheCCRPcomparatoris3-bitswidewhosevalueiscomparedwith thehighest3-bits in thecounterwhileCCRAandCCRBare10-bitswideand thereforecomparedwithallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theT1ONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheEnhancedTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontroloutputpins.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Rev. 1.40 1�6 ��st �� 01� Rev. 1.40 1�� st �� 01�


Enhanced Type TM Register DescriptionOveralloperationoftheEnhancedTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whiletworead/writeregisterpairsexisttostoretheinternal10-bitCCRAandCCRBvalue.TheremainingthreeregistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthethreeCCRPbits.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TM1C0 T1P�U TnCK� TnCK1 TnCK0 TnON T1RP� T1RP1 T1RP0TM1C1 T1�M1 T1�M0 T1�IO1 T1�IO0 T1�OC T1�POL T1CDN T1CCLRTM1C� T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC T1BPOL T1PWM1 T1PWM0TM1DL D� D6 D5 D4 D3 D� D1 D0TM1DH — — — — — D10 D9 D�TM1�L D� D6 D5 D4 D3 D� D1 D0TM1�H — — — — — — D9 D�TM1BL D� D6 D5 D4 D3 D� D1 D0TM1BH — — — — — — D9 D�

10-bit Enhanced TM Register List

TM1C0 Register

Bit 7 6 5 4 3 2 1 0Name T1P�U T1CK� T1CK1 T1CK0 T1ON T1RP� T1RP1 T1RP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 T1PAU:TM1CounterPauseControl0:Run1:Pause


Bit6~4 T1CK2~T1CK0:SelectTM1Counterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:Reserved110:TCK1risingedgeclock111:TCK1fallingedgeclock


Rev. 1.40 1�6 ��st �� 01� Rev. 1.40 1�� st �� 01�


Bit3 T1ON:TM1CounterOn/OffControl0:Off1:On

Thisbitcontrols theoverallon/offfunctionof theTM.SettingthebithighenablesthecountertorunandclearingthebitdisablestheTM.Clearingthisbittozerowillstop thecounter fromcountingand turnoff theTMwhichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheT1OCbit,whentheT1ONbitchangesfromlowtohigh.

Bit2~0 T1RP2~T1RP0:TM1CCRP3-bitregister,comparedwiththeTM1Counterbit9~bit7ComparatorPMatchPeriod000:1024TM1clocks001:128TM1clocks010:256TM1clocks011:384TM1clocks100:512TM1clocks101:640TM1clocks110:768TM1clocks111:896TM1clocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theT1CCLRbit isset tozero.SettingtheT1CCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�9 ��st �� 01�


TM1C1 Register

Bit 7 6 5 4 3 2 1 0Name T1�M1 T1�M0 T1�IO1 T1�IO0 T1�OC T1�POL T1CDN T1CCLRR/W R/W R/W R/W R/W R/W R/W R R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 T1AM1~T1AM0:SelectTM1CCRAOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremade to theT1AM1andT1AM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 T1AIO1~T1AIO0:SelectTP1AoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTP1IA01:InputcaptureatfallingedgeofTP1IA10:Inputcaptureatfalling/risingedgeofTP1IA11:Inputcapturedisabled


ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode,theT1AIO1andT1AIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowor totoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheT1AOCbitintheTM1C1register.Notethattheoutputlevel requestedbytheT1AIO1andT1AIO0bitsmustbedifferent fromthe initialvaluesetupusingtheT1AOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT1ONbitfromlowtohigh.InthePWMMode,theT1AIO1andT1AIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthese twobits. It isnecessary tochangethevaluesof theT1AIO1andT1AIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheT1AIO1andT1AIO0bitsarechangedwhentheTMisrunning.

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�9 ��st �� 01�


Bit3 T1AOC:TP1AOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh


This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTM isbeingused in theCompareMatchOutputModeor in thePWMMode/SinglePulseOutputMode.Ithasnoeffectif theTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelof theTMoutputpinbeforeacomparematchoccurs. In thePWMModeitdetermines if thePWMsignalisactivehighoractivelow.

Bit2 T1APOL:TP1AOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP1Aoutputpin.WhenthebitissethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 T1CDN:TM1Countupordownflag0:Countup1:Countdown

Bit0 T1CCLR:SelectTM1Counterclearcondition0:TM1ComparatrorPmatch1:TM1ComparatrorAmatch

Thisbit isused to select themethodwhichclears the counter.Remember thattheEnhancedTMcontains threecomparators,ComparatorA,ComparatorBandComparatorP,butonlyComparatorAorComparatorPcanbeselectedtocleartheinternalcounter.WiththeT1CCLRbitsethigh, thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheT1CCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.

Rev. 1.40 130 ��st �� 01� Rev. 1.40 131 ��st �� 01�


TM1C2 Register

Bit 7 6 5 4 3 2 1 0Name T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC T1BPOL T1PWM1 T1PWM0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 T1BM1~T1BM0:SelectTM1CCRBOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremade to theT1BM1andT1BM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 T1BIO1~T1BIO0:SelectTP1B,TP1BBoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTP1IB01:InputcaptureatfallingedgeofTP1IB10:Inputcaptureatfalling/risingedgeofTP1IB11:inputcapturedisabled


ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode, theT1BIO1andT1BIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorB.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorB.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheT1BOCbitintheTM1C2register.Notethattheoutputlevel requestedby theT1BIO1andT1BIO0bitsmustbedifferentfromthe initialvaluesetupusingtheT1BOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT1ONbitfromlowtohigh.InthePWMMode,theT1BIO1andT1BIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytochangethevaluesoftheT1BIO1andT1BIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheT1BIO1andT1BIO0bitsarechangedwhentheTMisrunning.

Rev. 1.40 130 ��st �� 01� Rev. 1.40 131 ��st �� 01�


Bit3 T1BOC:TP1B,TP1BBOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh


This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTM isbeingused in theCompareMatchOutputModeor in thePWMMode/SinglePulseOutputMode.Ithasnoeffectif theTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelof theTMoutputpinbeforeacomparematchoccurs. In thePWMModeitdetermines if thePWMsignalisactivehighoractivelow.

Bit2 T1BPOL:TP1B,TP1BBOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP1B,TP1BBoutputpin.WhenthebitissethightheTMoutputpinwillbe invertedandnot invertedwhenthebit iszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1~0 T1PWM1~T1PWM0:SelectPWMMode00:Edgealigned01:Centrealigned,comparematchoncountup10:Centrealigned,comparematchoncountdown11:Centrealigned,comparematchoncountupordown

TM1DL Register

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 TM1DL:TM1CounterLowByteRegisterbit7~bit0TM110-bitCounterbit7~bit0

TM1DH Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — D9 D�R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM1DH:TM1CounterHighByteRegisterbit1~bit0

TM110-bitCounterbit9~bit8

TM1AL Register


Bit7~0 TM1AL:TM1CCRALowByteRegisterbit7~bit0TM110-bitCCRAbit7~bit0

Rev. 1.40 13� ��st �� 01� Rev. 1.40 133 ��st �� 01�


TM1AH Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — D9 D�R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM1AH:TM1CCRAHighByteRegisterbit1~bit0

TM110-bitCCRAbit9~bit8

TM1BL Register


Bit7~0 TM1BL:TM1CCRBLowByteRegisterbit7~bit0TM110-bitCCRBbit7~bit0

TM1BH Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — D9 D�R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM1BH:TM1CCRBHighByteRegisterbit1~bit0

TM110-bitCCRBbit9~bit8

Enhanced Type TM Operating ModesTheEnhancedTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnAM1andTnAM0bitsintheTMnC1,andtheTnBM1andTnBM0bitsintheTMnC2register.

ETM Operation Mode

CCRA Compare

Match Output Mode

CCRA Timer/Counter Mode

CCRB PWMOutput Mode

CCRB SinglePulse Output

Mode

CCRB InputCapture Mode

CCRB Compare Match O�tp�t Mode √ — — — —CCRB Timer/Co�nter Mode — √ — — —CCRB PWM O�tp�t Mode — — √ — —CCRB Sin�le P�lse O�tp�t Mode — — — √ —CCRB Inp�t Capt�re Mode — — — — √

“√”: permitted; “—”: not permitted

Rev. 1.40 13� ��st �� 01� Rev. 1.40 133 ��st �� 01�


Compare Output ModeToselect thismode,bitsTnAM1,TnAM0andTnBM1,TnBM0intheTMnC1/TMnC2registersshouldbeallclearedtozero.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP, theother iswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HereboththeTnAFandTnPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaTnAForTnBFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorAorComparatorB.TheTnPFinterruptrequest flag,generatedfromacomparematchfromComparatorP,willhavenoeffectontheTMoutputpin.ThewayinwhichtheTMoutputpinchangesstateisdeterminedbytheconditionoftheTnAIO1andTnAIO0bitsintheTMnC1registerforETMCCRA,andtheTnBIO1andTnBIO0bitsintheTMnC2registerforETMCCRB.TheTMoutputpincanbeselectedusingtheTnAIO1,TnAIO0bits(for theTPnApin)andTnBIO1,TnBIO0bits(for theTP1B,TP1BBpins)togohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorAoracomparematchoccursfromComparatorB.TheinitialconditionoftheTMoutputpin,whichissetupaftertheTnONbitchangesfromlowtohigh,issetupusingtheTnAOCorTnBOCbitforTPnAorTP1B,TP1BBoutputpins.NotethatiftheTnAIO1,TnAIO0andTnBIO1,TnBIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.40 134 ��st �� 01� Rev. 1.40 135 ��st �� 01�


Co�nter Val�e

0x3FF

CCRP

CCR�

TnON

TnP�U

Tn�POL



TPn� O/P Pin

Time

CCRP=0

CCRP > 0


Pa�se

Res�me

Stop

Co�nter Restart

TnCCLR = 0; Tn�M [1:0] = 00

O�tp�t pin set to initial Level Low if Tn�OC=0


Note Tn�IO [1:0] = 10 �ctive Hi�h O�tp�t selectHere Tn�IO [1:0] = 11





O�tp�t Invertswhen Tn�POL is hi�h

ETM CCRA Compare Match Output Mode – TnCCLR=0

Note: 1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTPnAoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.n=1

Rev. 1.40 134 ��st �� 01� Rev. 1.40 135 ��st �� 01�


Co�nter Val�e

0x3FF

CCRP

CCRB

TnON

TnP�U

TnBPOL


CCRB Int. Fla� TnBF

TPnB O/P Pin

Time

CCRP=0

CCRP > 0


Pa�se

Res�me

Stop

Co�nter Restart

TnCCLR = 0; TnBM [1:0] = 00

O�tp�t pin set to initial Level Low if TnBOC=0

O�tp�t To��le with TnBF fla�

Note TnBIO [1:0] = 10 �ctive Hi�h O�tp�t selectHere TnBIO [1:0] = 11


O�tp�t not affected by TnBF fla�. Remains Hi�h �ntil reset by TnON bit



O�tp�t Invertswhen TnBPOL is hi�h

ETM CCRB Compare Match Output Mode – TnCCLR=0

Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTPnBoutputpiniscontrolledonlybytheTnBFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.n=1

Rev. 1.40 136 ��st �� 01� Rev. 1.40 13� ��st �� 01�


Co�nter Val�e

0x3FF

CCRP

CCR�

TnON

TnP�U

Tn�POL



TPn� O/P Pin

Time

CCR�=0


Pa�se

Res�me


TnCCLR = 1; Tn�M [1:0] = 00

O�tp�t pin set to initial Level Low if Tn�OC=0


Note Tn�IO [1:0] = 10 �ctive Hi�h O�tp�t selectHere Tn�IO [1:0] = 11






TnPF not �enerated


O�tp�t does not chan�e

ETM CCRA Compare Match Output Mode – TnCCLR=1

Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTPnAoutputpiniscontrolledonlybytheTnAFflag3.TheTPnAoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.TheTnPFflagisnotgeneratedwhenTnCCLR=15.n=1

Rev. 1.40 136 ��st �� 01� Rev. 1.40 13� ��st �� 01�


Co�nter Val�e

0x3FF

CCRB

CCR�

TnON

TnP�U

TnBPOL



TPnB O/P Pin

Time

CCR�=0


Pa�se

Res�me


TnCCLR = 1; TnBM [1:0] = 00

O�tp�t pin set to initial Level Low if TnBOC=0

O�tp�t To��le with TnBF fla�

Note TnBIO [1:0] = 10 �ctive Hi�h O�tp�t selectHere TnBIO [1:0] = 11


O�tp�t not affected by TnBF fla�. Remains Hi�h �ntil reset by TnON bit





ETM CCRB Compare Match Output Mode – TnCCLR=1

Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTPnBoutputpiniscontrolledonlybytheTnBFflag3.TheTPnBoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.TheTnPFflagisnotgeneratedwhenTnCCLR=15.n=1

Rev. 1.40 13� ��st �� 01� Rev. 1.40 139 ��st �� 01�



PWM Output ModeToselect thismode, therequiredbitpairs,TnAM1,TnAM0andTnBM1,TnBM0shouldbesetto10respectivelyandalsotheTnAIO1,TnAIO0andTnBIO1,TnBIO0bitsshouldbeset to10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignalof fixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMmode,theTnCCLRbitisusedtodetermineinwhichwaythePWMperiodiscontrolled.WiththeTnCCLRbitsethigh,thePWMperiodcanbefinelycontrolledusing theCCRAregisters. In thiscase theCCRBregistersareused toset thePWMdutyvalue(forTPnBandTPnBBoutputpins).TheCCRPbitsarenotusedandTPnAoutputpinisnotused.ThePWMoutputcanonlybegeneratedontheTPnBandTPnBBoutputpins.WiththeTnCCLRbitclearedtozero,thePWMperiodissetusingoneoftheeightvaluesofthethreeCCRPbits,inmultiplesof128.NowbothCCRAandCCRBregisterscanbeusedtosetupdifferentdutycyclevaluestoprovidedualPWMoutputsontheirrelativeTPnA,TPnBandTPnBBpins.

TheTnPWM1andTnPWM0bitsdeterminethePWMalignment type,whichcanbeeitheredgeorcentre type. Inedgealignment, the leadingedgeof thePWMsignalswillallbegeneratedconcurrentlywhenthecounter isreset tozero.Withallpowercurrentsswitchingonat thesametime,thismaygiverisetoproblemsinhigherpowerapplications.IncentrealignmentthecentreofthePWMactivesignalswilloccursequentially, thusreducingthelevelofsimultaneouspowerswitchingcurrents.

Interruptflags,oneforeachoftheCCRA,CCRBandCCRP,willbegeneratedwhenacomparematchoccurs fromeither theComparatorA,ComparatorBorComparatorP.TheTnAOCandTnBOCbitsintheTMnC1andTMnC2registerareusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnAIO1,TnAIO0andTnBIO1,TnBIO0bitspairsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnAPOLandTnBPOLbitareusedtoreversethepolarityofthePWMoutputwaveform.

Rev. 1.40 13� ��st �� 01� Rev. 1.40 139 ��st �� 01�


ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPeriod 1�� 56 3�4 51� 640 �6� �96 10�4� D�ty CCR�B D�ty CCRB

IffSYS=12MHz,TMclocksourceselectfSYS/4,CCRP=100b,CCRA=128andCCRB=256,

TheTPnAPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=5.8594kHz,duty=128/512=25%.

TheTPnBorTPnBBPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=5.8594kHz,duty=256/512=50%.

IftheDutyvaluedefinedbyCCRAorCCRBregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1

CCRA 1 2 3 511 512 1021 1022 1023Period 1 � 3 511 51� 10�1 10�� 10�3B D�ty CCRB

ETM, PWM Mode, Center-aligned Mode, TnCCLR=0

CCRA 001b 010b 011b 100b 101b 110b 111b 000bPeriod �56 51� �6� 10�4 1��0 1536 1�9� �046� D�ty (CCR�×�)-1B D�ty (CCRB×�)-1

ETM, PWM Mode, Center-aligned Mode, TnCCLR=1

CCRA 1 2 3 511 512 1021 1022 1023Period � 4 6 10�� 10�4 �04� �044 �046B D�ty (CCRB×�)-1

Rev. 1.40 140 ��st �� 01� Rev. 1.40 141 ��st �� 01�


Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

Tn�POL



TPn� Pin (Tn�OC=1)

Time

Co�nter Cleared by CCRP

Pa�seRes�me Stop Co�nter

Restart

TnCCLR = 0;Tn�M [1:0] = 10� TnBM [1:0] = 10;TnPWM [1:0] = 00




CCRB


TPnB Pin (TnBOC=1)

TPnB Pin (TnBOC=0)

D�ty Cycle set by CCR�

D�ty Cycle set by CCRB

PWM Period set by CCRP



ETM PWM Mode – Edge Aligned

Note:1.HereTnCCLR=0thereforeCCRPclearsthecounteranddeterminesthePWMperiod2.TheinternalPWMfunctioncontinuesrunningevenwhenTnAIO[1:0](orTnBIO[1:0])=00or013.CCRAcontrolstheTPnAPWMdutyandCCRBcontrolstheTPnBPWMduty4.n=1

Rev. 1.40 140 ��st �� 01� Rev. 1.40 141 ��st �� 01�


Counter Value

CCRA

TnON

TnPAU

TnBPOL

CCRB Int. Flag TnBF

Time

Counter Cleared by CCRA

PauseResume Stop Counter

Restart

TnCCLR = 1; TnBM [1:0] = 10;TnPWM [1:0] = 00

Output PinReset to Initial value

Output controlled by other pin-shared function

Output Invertswhen TnBPOL is high

CCRB

CCRA Int. Flag TnAF

TPnB Pin (TnBOC=1)

TPnB Pin (TnBOC=0)

Duty Cycle set by CCRB

PWM Period set by CCRA

ETM PWM Mode – Edge Aligned

Note:1.HereTnCCLR=1thereforeCCRAclearsthecounteranddeterminesthePWMperiod2.TheinternalPWMfunctioncontinuesrunningevenwhenTnBIO[1:0]=00or013.TheCCRAcontrolstheTPnBPWMperiodandCCRBcontrolstheTPnBPWMduty4.HeretheTMpincontrolregistershouldnotenabletheTPnApinasaTMoutputpin5.n=1

Rev. 1.40 14� ��st �� 01� Rev. 1.40 143 ��st �� 01�


Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

Tn�POL



TPn� Pin (Tn�OC=1)

Time

Pa�se

Res�meStop

Co�nter Restart

TnCCLR = 0;Tn�M [1:0] = 10� TnBM [1:0] = 10;TnPWM [1:0] = 11


O�tp�t controlled by Other pin-shared f�nction


CCRB


TPnB Pin (TnBOC=1)

TPnB Pin (TnBOC=0)



PWM Period set by CCRP

ETM PWM Mode – Centre Aligned

Note:1.HereTnCCLR=0thereforeCCRPclearsthecounteranddeterminesthePWMperiod2.TnPWM[1:0]=11thereforethePWMiscentrealigned3.TheinternalPWMfunctioncontinuesrunningevenwhenTnAIO[1:0](orTnBIO[1:0])=00or014.CCRAcontrolstheTPnAPWMdutyandCCRBcontrolstheTPnBPWMduty5.CCRPwillgenerateaninterruptrequestwhenthecounterdecrementstoitszerovalue6.n=1

Rev. 1.40 14� ��st �� 01� Rev. 1.40 143 ��st �� 01�


Co�nter Val�e

CCR�

TnON

TnP�U

TnBPOL



Time

Pa�se

Res�meStop

Co�nter Restart

TnCCLR = 1; TnBM [1:0] = 10;TnPWM [1:0] = 11


O�tp�t controlledby other pin-shared f�nction

CCRB

TPnB Pin (TnBOC=1)

TPnB Pin (TnBOC=0)


PWM Period set by CCR�



ETM PWM Mode – Centre Aligned

Note: 1.HereTnCCLR=1thereforeCCRAclearsthecounteranddeterminesthePWMperiod2.TnPWM[1:0]=11thereforethePWMiscentrealigned3.TheinternalPWMfunctioncontinuesrunningevenwhenTnBIO[1:0]=00or014.CCRAcontrolstheTPnBPWMperiodandCCRBcontrolstheTPnBPWMduty5.CCRPwillgenerateaninterruptrequestwhenthecounterdecrementstoitszerovalue6.n=1

Rev. 1.40 144 ��st �� 01� Rev. 1.40 145 ��st �� 01�


Single Pulse ModeToselectthismode,therequiredbitpairs,TnAM1,TnAM0andTnBM1,TnBM0shouldbesetto10respectivelyandalsothecorrespondingTnAIO1,TnAIO0andTnBIO1,TnBIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.

ThetriggerforthepulseTPnAoutputleadingedgeisalowtohightransitionoftheTnONbit,whichcanbeimplementedusingtheapplicationprogram.ThetriggerforthepulseTPnBoutputleadingedge isacomparematchfromComparatorB,whichcanbe implementedusing theapplicationprogram.However in theSinglePulseMode, theTnONbitcanalsobemade toautomaticallychangefromlowtohighusingtheexternalTCKnpin,whichwillinturninitiatetheSinglePulseoutputofTPnA.WhentheTnONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgeofTPnAwillbegenerated.TheTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgeofTPnAandTPnBorTPnBBwillbegeneratedwhentheTnONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheTnONbitandthusgeneratetheSinglePulseoutputtrailingedgeofTPnAandTPnBorTPnBB.InthiswaytheCCRAvaluecanbeusedtocontrol thepulsewidthofTPnA.The(CCRA-CCRB)valuecanbeusedtocontrolthepulsewidthofTPnBandTPnBB.AcomparematchfromComparatorAandComparatorBwillalsogenerateTMinterrupts.ThecountercanonlyberesetbacktozerowhentheTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheTnCCLRbitisalsonotused.

TnON bit0 à 1

S/W Command SET“TnON”

orTCKn Pin Transition

CCRB Leadin� Ed�e

TnON bit1 à 0

CCR� Trailin� Ed�e

S/W Command CLR“TnON”

orCCR� Compare Match

TPn� O�tp�t Pin

TPnB O�tp�t Pin

P�lse Width = (CCR�-CCRB) Val�e

P�lse Width = CCR� Val�e

Co�nter Val�e

CCRB

CCR�

0 Time

TnON = 1CCRB Compare Match TnON bit1 à 0

S/W Command CLR“TnON”

orCCR� Compare Match

CCRB Trailin� Ed�e

CCR� Leadin� Ed�e

TPnBB O�tp�t Pin

Single Pulse Generation

Rev. 1.40 144 ��st �� 01� Rev. 1.40 145 ��st �� 01�


Co�nter Val�e

CCRB

CCR�

TnON

TnP�U

Tn�POL

CCRB Int. Fla� TnBFCCR� Int. Fla� Tn�F

TPn� Pin(Tn�OC=1)

Time

Co�nter stopped by CCR�

Pa�seRes�me Co�nter Stops

by software


Tn�M [1:0] = 10� TnBM [1:0] = 10;Tn�IO [1:0] = 11� TnBIO [1:0] = 11

P�lse Width set by (CCR�-CCRB) O�tp�t Inverts

when TnBPOL=1

TCKn pin


Cleared by CCR� match

TCKn pin Tri��er

��to. set by TCKn pin


Software Clear

Software Tri��erSoftware

Tri��er

TnBPOL

TPn� Pin(Tn�OC=0)

TPnB Pin(TnBOC=1)

TPnB Pin(TnBOC=0)

P�lse Width set by CCR�

O�tp�t Invertswhen Tn�POL=1

ETM – Single Pulse Mode

Note:1.CounterstoppedbyCCRA2.CCRPisnotused3.ThepulsetriggeredbytheTCKnpinorbysettingtheTnONbithigh4.ATCKnpinactiveedgewillautomaticallysettheTnONbithigh5.IntheSinglePulseMode,TnAIO[1:0]andTnBIO[1:0]mustbesetto“11”andcannotbechanged6.n=1

Rev. 1.40 146 ��st �� 01� Rev. 1.40 14� ��st �� 01�


Capture Input ModeToselectthismodebitsTnAM1,TnAM0andTnBM1,TnBM0intheTMnC1andTMnC2registersshouldbeset to01 respectively.Thismodeenablesexternal signals tocaptureandstore thepresentvalueoftheinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheTPnIAandTPnIBpins,whoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheTnAIO1,TnAIO0andTnBIO1,TnBIO0bitsintheTMnC1andTMnC2registers.Thecounter isstartedwhentheTnONbitchangesfromlowtohighwhichis initiatedusingtheapplicationprogram.

When the requirededge transitionappearson theTPnIAandTPnIBpins, thepresentvalue inthecounterwillbe latched into theCCRAandCCRBregistersandaTMinterruptgenerated.IrrespectiveofwhateventsoccurontheTPnIAandTPnIBpinsthecounterwillcontinuetofreerununtiltheTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.Counting thenumberofoverflow interrupt signals fromtheCCRPcanbeausefulmethod inmeasuringlongpulsewidths.TheTnAIO1,TnAIO0andTnBIO1,TnBIO0bitscanselecttheactivetriggeredgeontheTPnIAandTPnIBpinstobearisingedge,fallingedgeorbothedgetypes.IftheTnAIO1,TnAIO0andTnBIO1,TnBIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheTPnIAandTPnIBpins,howeveritmustbenotedthatthecounterwillcontinuetorun.

AstheTPnIAandTPnIBpinsarepinsharedwithotherfunctions,caremustbetakeniftheTMisintheCaptureInputMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.TheTnCCLR,TnAOC,TnBOC,TnAPOLandTnBPOLbitsarenotusedinthismode.

Rev. 1.40 146 ��st �� 01� Rev. 1.40 14� ��st �� 01�


Counter Value

YY

CCRP

TnON

TnPAU

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

CCRA Value

Time

Counter cleared by CCRP

PauseResume

Counter Reset

TnAM [1:0] = 01

TM capture pin TPnIA

XX

Counter Stop

TnAIO [1:0] Value

XX YY XX YY

Active edge Active

edgeActive edge

00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disable Capture

ETM CCRA Capture Input Mode

Note:1.TnAM[1:0]=01andactiveedgesetbytheTnAIO[1:0]bits2.TheTMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.TnCCLRbitnotused4.Nooutputfunction--TnAOCandTnAPOLbitsnotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero6.n=1

Rev. 1.40 14� ��st �� 01� Rev. 1.40 149 ��st �� 01�


CCRP

Counter overflow

CCRP Int.Flag TnPF

CCRB Int.Flag TnBF

TnON bit

Pause

CounterReset

TnPAU bit

Resume

Stop

YY

XX

CCRBValue XX

TM CapturePin TPnIB

YY

TnBIO1, TnBIO0Value 00 - Rising edge 01 - Falling edge 11 - Disable Capture

Activeedge

Activeedge

XX

10 - Both edges

Activeedges

YY

TnBM1, TnBM0 = 01

Time

CounterValue

ETM CCRB Capture Input Mode

Note:1.TnBM[1:0]=01andactiveedgesetbytheTnBIO[1:0]bits2.TheTMCaptureinputpinactiveedgetransfersthecountervaluetoCCRB3.TnCCLRbitnotused4.Nooutputfunction--TnBOCandTnBPOLbitsnotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero6.n=1

Rev. 1.40 14� ��st �� 01� Rev. 1.40 149 ��st �� 01�


Aanlog to Digital ConverterTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.

A/D OverviewThedevicescontainsamulti-channelanalogtodigitalconverterwhichcandirectly interface toexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoeithera12-bitdigitalvalue.

Part No. Input Channels A/D Channel Select Bits Input PinsHT66F60�HT66F�0� 1� �CS4~�CS0 �N0~�N11

TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.

A/D Converter Register DescriptionOveralloperationoftheA/Dconverteriscontrolledusingfourregisters.AreadonlyregisterpairexiststostoretheADCdata12-bitvalue.TheremainingtworegistersarecontrolregisterswhichsetuptheoperatingandcontrolfunctionoftheA/Dconverter.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0�DRL (�DRFS=0) D3 D� D1 D0 — — — —�DRL (�DRFS=1) D� D6 D5 D4 D3 D� D1 D0�DRH (�DRFS=0) D11 D10 D9 D� D� D6 D5 D4�DRH (�DRFS=1) — — — — D11 D10 D9 D��DCR0 ST�RT EOCB �DOFF �CS4 �CS3 �CS� �CS1 �CS0�DCR1 — VBGEN �DRFS VREFS — �DCK� �DCK1 �DCK0

A/D Converter Register List

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A/D Converter Structure

Rev. 1.40 150 ��st �� 01� Rev. 1.40 151 ��st �� 01�


A/D Converter Data Registers – ADRL, ADRHAsthedevicescontainaninternal12-bitA/Dconverter, itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasADRH,andalowbyteregister,knownasADRL.After theconversionprocess takesplace, these registerscanbedirectly readby themicrocontrollertoobtainthedigitisedconversionvalue.Asonly12bitsofthe16-bitregisterspaceisutilised, theformat inwhichthedata isstorediscontrolledbytheADRFSbit in theADCR0registerasshownintheaccompanyingtable.D0~D11aretheA/Dconversionresultdatabits.Anyunusedbitswillbereadaszero.

ADRFSADRH ADRL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 00 D11 D10 D9 D� D� D6 D5 D4 D3 D� D1 D0 0 0 0 01 0 0 0 0 D11 D10 D9 D� D� D6 D5 D4 D3 D� D1 D0

A/D Data Registers

A/D Converter Control Registers – ADCR0, ADCR1, PAS0~PAS3, PES3, PFS0, PHS0TocontrolthefunctionandoperationoftheA/Dconverter,twocontrolregistersknownasADCR0andADCR1areprovided.These8-bit registersdefinefunctionssuchas theselectionofwhichanalogchannelisconnectedtotheinternalA/Dconverter,thedigitiseddataformat,theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterendofconversionstatus.TheACS4~ACS0bitsintheADCR0registerdefinetheADCinputchannelnumber.Asthedevicecontainsonlyoneactualanalogtodigitalconverterhardwarecircuit,eachoftheindividual12analog inputsmustberouted to theconverter. It is thefunctionof theACS4~ACS0bits todeterminewhichanalogchannelinputpinsorinternal1.25VisactuallyconnectedtotheinternalA/Dconverter.

Thepin-sharedfunctionconntrolregisters,namedPAS0~PAS3,PES3,PFS0andPHS0,containthecorrespondingpin-sharedfunctionselectionbitswhichdeterminewhichpinsonPortA,PortE,PortFandPortHareusedasanaloginputsfortheA/DconverterinputandwhichpinsarenottobeusedastheA/Dconverterinput.ConfiguringthecorrespondingbitwillselecttheA/DinputfunctionoreithertheI/Oorotherpin-sharedfunction.WhenthepinisselectedtobeanA/Dinput,itsoriginalfunctionwhetheritisanI/Oorotherpin-sharedfunctionwillberemoved.Inaddition,anyinternalpull-highresistorsconnectedtothesepinswillbeautomaticallyremovedifthepinisselectedtobeanA/Dinput.

Rev. 1.40 150 ��st �� 01� Rev. 1.40 151 ��st �� 01�


• ADCR0 Register

Bit 7 6 5 4 3 2 1 0Name ST�RT EOCB �DOFF �CS4 �CS3 �CS� �CS1 �CS0R/W R/W R R/W R/W R/W R/W R/W R/WPOR 0 1 1 0 0 0 0 0

Bit7 START:StarttheA/Dconversion0→1→0:Start0→1:ResettheA/DconverterandsetEOCBto“1”

ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.WhenthebitissethightheA/Dconverterwillbereset.

Bit6 EOCB:EndofA/Dconversionflag0:A/Dconversionended1:A/Dconversioninprogress

ThisreadonlyflagisusedtoindicatewhenanA/Dconversionprocesshascompleted.Whentheconversionprocessisrunning,thebitwillbehigh.

Bit5 ADOFF:ADCmodulepoweron/offcontrolbit0:ADCmodulepoweron1:ADCmodulepoweroff

Thisbitcontrols thepowerto theA/Dinternalfunction.ThisbitshouldbeclearedtozerotoenabletheA/Dconverter.IfthebitissethighthentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.AstheA/Dconverterwillconsumealimitedamountofpower,evenwhennotexecutingaconversion,thismaybeanimportantconsiderationinpowersensitivebatterypoweredapplications.Note:1.itisrecommendedtosetADOFF=1beforeenteringIDLE/SLEEPModefor

savingpower.2.ADOFF=1willpowerdowntheADCmodule.

Bit4~0 ACS4~ACS0:SelectA/Dchannel00000:AN000001:AN100010:AN200011:AN300100:AN400101:AN500110:AN600111:AN701000:AN801001:AN901010:AN1001011:AN11011xx:Undefined1xxxx:InternalBandgapvoltage

ThesearetheA/Dchannelselectcontrolbits.AsthereisonlyoneinternalhardwareA/DconvertereachofthetwelveA/Dinputsmustberoutedtotheinternalconverterusingthesebits.IftheACS4bitissethigh,thentheinternalBandgap1.25VwillberoutedtotheA/DConverter.

Rev. 1.40 15� ��st �� 01� Rev. 1.40 153 ��st �� 01�


• ADCR1 Register

Bit 7 6 5 4 3 2 1 0Name — VBGEN �DRFS VREFS — �DCK� �DCK1 �DCK0R/W — R R/W R/W — R/W R/W R/WPOR — 1 1 0 — 0 0 0

Bit7 Unimplemented,readas“0”Bit6 VBGEN:InternalBandgapvoltagecontrol

0:Disable1:Enable

Thisbitcontrols the internalBandgapcircuiton/offfunctionto theA/Dconverter.Whenthebitissethighthebandgapvoltage1.25VcanbeusedbytheA/Dconverter.If1.25VisnotusedbytheA/DconverterandtheLVR/LVDfunctionisdisabledthenthebandgapreferencecircuitwillbeautomaticallyswitchedoff toconservepower.When1.25V is switchedon foruseby theA/Dconverter,a time tBGshouldbeallowedforthebandgapcircuittostabilisebeforeimplementinganA/Dconversion.

Bit5 ADRFS:ADCDataFormatControl0:ADCDataMSBisADRHbit7,LSBisADRLbit41:ADCDataMSBisADRHbit3,LSBisADRLbit0

Thisbitcontrols theformatof the12-bitconvertedA/Dvaluein thetwoA/Ddataregisters.DetailsareprovidedintheA/Ddataregistersection.

Bit4 VREFS:SelectADCreferencevoltage0:InternalADCpower1:VREFpin

ThisbitisusedtoselectthereferencevoltagefortheA/Dconverter.Ifthebitishigh,thentheA/DconverterreferencevoltageissuppliedontheexternalVREFpin.Ifthepinislow,thentheinternalreferenceisusedwhichistakenfromthepowersupplypinVDD.

Bit3 Unimplemented,readas"0"Bit2~0 ADCK2,ADCK1, ADCK0:SelectADCclocksource

000:fSYS

001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:Undefined

ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter.

Rev. 1.40 15� ��st �� 01� Rev. 1.40 153 ��st �� 01�


A/D OperationTheSTARTbit in theADCR0register isused tostartand reset theA/Dconverter.When themicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbe initiated.WhentheSTARTbit isbroughtfromlowtohighbutnot lowagain, theEOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigitalconverter.TheEOCBbit in theADCR0register isused to indicatewhentheanalogtodigitalconversionprocess is complete.Thisbitwillbeautomatically set to “0”by themicrocontroller after aconversioncyclehasended.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andif theinterruptsareenabled,anappropriateinternalinterruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowto theassociatedA/Dinternal interruptaddressforprocessing.If theA/Dinternal interrupt isdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosentobeeither fSYSorasubdividedversionof fSYS.Thedivisionratiovalue isdeterminedby theADCK2~ADCK0bitsintheADCR1register.Although theA/D clock source is determined by the system clocky, fSYS, and by bitsADCK2~ADCK0, therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.AstheminimumvalueofpermissibleA/Dclockperiod,tADCK,is0.5μs,caremustbetakenforsystemclockfrequenciesequaltoorgreaterthan4MHz.Forexample,ifthesystemclockoperatesatafrequencyof4MHz,theADCK2~ADCK0bitsshouldnotbesetto“000”.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.Refertothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod.

fSYS

A/D Clock Period (tADCK)ADCK2, ADCK1, ADCK0

=000 (fSYS)

ADCK2, ADCK1, ADCK0

=001 (fSYS/2)

ADCK2, ADCK1, ADCK0

=010 (fSYS/4)

ADCK2, ADCK1, ADCK0

=011 (fSYS/8)

ADCK2, ADCK1, ADCK0

=100 (fSYS/16)

ADCK2, ADCK1, ADCK0

=101 (fSYS/32)

ADCK2, ADCK1, ADCK0

=110 (fSYS/64)

ADCK2, ADCK1, ADCK0

=111

1MHz 1μs 2μs 4μs 8μs 16μs 32μs 64μs Undefined�MHz 500ns 1μs 2μs 4μs 8μs 16μs 32μs Undefined4MHz �50ns* 500ns 1μs 2μs 4μs 8μs 16μs Undefined�MHz 1�5ns* �50ns* 500ns 1μs 2μs 4μs 8μs Undefined

1�MHz �3ns* 16�ns* 333ns* 66�ns 1.33μs 2.67μs 5.33μs Undefined

A/D Clock Period Examples

Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theADOFFbit in theADCR0register.ThisbitmustbezerotopowerontheA/Dconverter.WhentheADOFFbitisclearedtozerotopowerontheA/Dconverterinternalcircuitryacertaindelay,asindicatedinthetimingdiagram,mustbeallowedbeforeanA/Dconversionisinitiated.EvenifnopinsareselectedforuseasA/Dinputs,iftheADOFFbitiszerothensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheADOFFissethightoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.ThereferencevoltagesupplytotheA/DConvertercanbesuppliedfromeitherthepositivepowersupplypin,VDD,orfromanexternalreferencesourcessuppliedonpinVREF.Thedesiredselectionismadeusing theVREFSandPH0S3~PH0S0bits.As theVREFpin ispin-sharedwithotherfunctions,whentheVREFSbitissethighandthePH0S3~PH0S0bitsaresetto“0011”,theVREFpinfunctionwillbeselectedandtheotherpinfunctionswillbedisabledautomatically.

Rev. 1.40 154 ��st �� 01� Rev. 1.40 155 ��st �� 01�


A/D Input PinsAlloftheA/Danaloginputpinsarepin-sharedwiththeI/OpinsonPortA,PortE,PortFandPortHaswellasotherfunctions.Thecorrespondingselectionbits in thePAS0~PAS3,PES3,PFS0andPHS0registers,determinewhethertheinputpinsaresetupasA/Dconverteranaloginputsorwhethertheyhaveotherfunctions.IfthecorrespondingpinissetuptobeanA/Dconverterinput,theoriginalpinfunctionsdisabled. In thisway,pinscanbechangedunderprogramcontrol tochangetheirfunctionbetweenA/Dinputsandotherfunctions.Allpull-highresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnectedifthepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputinthePAC,PEC,PFCorPHCportcontrolregistertoenabletheA/DinputaswhentherelevantA/DinputfunctionselectionbitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.

TheA/Dconverterhas itsownreferencevoltagepin,VREF,however thereferencevoltagecanalsobesuppliedfromthepowersupplypin,achoicewhichismadethroughtheVREFSbitintheADCR1register.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueofVREF.

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A/D Input Structure

Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsADCK2~ADCK0intheADCR1register.

• Step2EnabletheA/DbyclearingtheADOFFbitintheADCR0registertozero.

• Step3SelectwhichchannelistobeconnectedtotheinternalA/DconverterbycorrectlyprogrammingtheACS4~ACS0bitswhicharealsocontainedintheADCR1andADCR0register.

• Step4SelectwhichpinsaretobeusedasA/Dinputsandconfigurethembycorrectlyprogrammingthecorrespondingpin-sharedfunctionselectionregisters.

• Step5If theinterruptsare tobeused, theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dconverterinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconverterinterruptbit,ADE,mustbothbesethightodothis.

Rev. 1.40 154 ��st �� 01� Rev. 1.40 155 ��st �� 01�


• Step6Theanalog todigitalconversionprocesscannowbe initialisedbysetting theSTARTbit intheADCR0registerfromlowtohighandthenlowagain.Notethat thisbitshouldhavebeenoriginallyclearedtozero.

• Step7Tocheckwhentheanalogtodigitalconversionprocessiscomplete,theEOCBbitintheADCR0registercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregisterADRLandADRHcanbereadtoobtaintheconversionvalue.Asanalternativemethod,iftheinterruptsareenabledandthestackisnotfull,theprogramcanwaitforanA/Dinterrupttooccur.Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheEOCB

bitintheADCR0registerisused,theinterruptenablestepabovecanbeomitted.

Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADCKwheretADCKisequaltotheA/Dclockperiod.

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A/D Conversion Timing

Rev. 1.40 156 ��st �� 01� Rev. 1.40 15� ��st �� 01�


Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,bysettingbitADOFFhigh in theADCR0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.

A/D Transfer FunctionAsthedevicescontaina12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequaltotheVDDorVREFvoltage,thisgivesasinglebitanaloginputvalueofVDDorVREFdividedby4096.

1LSB=(VDDorVREF)÷4096

TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:

A/Dinputvoltage=A/Doutputdigitalvalue×(VDDorVREF)÷4096

Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVDDorVREFlevel.

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Ideal A/D Transfer Function

Rev. 1.40 156 ��st �� 01� Rev. 1.40 15� ��st �� 01�


A/D Programming ExampleThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheEOCBbit intheADCR0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an EOCB polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov ADCR1,a ;selectfSYS/8asA/Dclockandswitchoff1.25Vclr ADOFFmov a,03h ;setupPHS0toconfigurepinAN0mov PHS0,amov a,00hmov ADCR0,a ;enableandconnectAN0channeltoA/Dconverter:start_conversion:clr START ;highpulseonstartbittoinitiateconversionset START ;resetA/Dclr START ;startA/Dpolling_EOC:sz EOCB ;polltheADCR0registerEOCBbittodetectendofA/Dconversionjmp polling_EOC ;continuepolling

mov a,ADRL ;readlowbyteconversionresultvaluemov ADRL_buffer,a ;saveresulttouserdefinedregistermov a,ADRH ;readhighbyteconversionresultvaluemov ADRH_buffer,a ;saveresulttouserdefinedregister::jmp start_conversion ;startnexta/dconversion

Rev. 1.40 15� ��st �� 01� Rev. 1.40 159 ��st �� 01�


Example: using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov ADCR1,a ;selectfSYS/8asA/Dclockandswitchoff1.25Vclr ADOFFmov a,03h ;setupPHS0toconfigurepinAN0mov PHS0,amov a,00hmov ADCR0,a ;enableandconnectAN0channeltoA/DconverterStart_conversion:clr START ;highpulseonSTARTbittoinitiateconversionset START ;resetA/Dclr START ;startA/Dclr ADF ;clearADCinterruptrequestflagset ADE ; enable ADC interruptset EMI ;enableglobalinterrupt:: ; ADC interrupt service routineADC_ISR:mov acc_stack,a ;saveACCtouserdefinedmemorymov a,STATUSmov status_stack,a ;saveSTATUStouserdefinedmemory::mov a,ADRL ;readlowbyteconversionresultvaluemov adrl_buffer,a ;saveresulttouserdefinedregistermov a,ADRH ;readhighbyteconversionresultvaluemov adrh_buffer,a ;saveresulttouserdefinedregister::EXIT_INT_ISR:mov a,status_stackmov STATUS,a ;restoreSTATUSfromuserdefinedmemorymov a,acc_stack ;restoreACCfromuserdefinedmemoryreti

Rev. 1.40 15� ��st �� 01� Rev. 1.40 159 ��st �� 01�


ComparatorsTwoindependentanalogcomparatorsarecontainedwithin thesedevices.Thesefunctionsofferflexibilityviatheirregistercontrolledfeaturessuchaspower-down,polarityselect,hysteresisetc.InsharingtheirpinswithnormalI/OpinsthecomparatorsdonotwastepreciousI/Opinsiftherefunctionsareotherwiseunused.

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Comparator

Comparator OperationThedevicescontain twocomparator functionswhichareused tocompare twoanalogvoltagesandprovideanoutputbasedon theirdifference.Fullcontrolover the twointernalcomparatorsisprovidedvia twocontrol registers,CP0CandCP1C,oneassigned toeachcomparator.Thecomparatoroutputisrecordedviaabitintheirrespectivecontrolregister,butcanalsobetransferredoutontoasharedI/Opin.Additionalcomparator functions include,outputpolarity,hysteresisfunctionsandpowerdowncontrol.

Anypull-high resistorsconnected to the sharedcomparator inputpinswillbeautomaticallydisconnectedwhenthecomparatorisenabled.Asthecomparatorinputsapproachtheirswitchinglevel,somespuriousoutputsignalsmaybegeneratedonthecomparatoroutputdueto theslowrisingor fallingnatureof the inputsignals.Thiscanbeminimisedbyselecting thehysteresisfunctionwillapplyasmallamountofpositivefeedbacktothecomparator.Ideallythecomparatorshouldswitchat thepointwherethepositiveandnegativeinputssignalsareat thesamevoltagelevel,however,unavoidableinputoffsetsintroducesomeuncertaintieshere.Thehysteresisfunction,ifenabled,alsoincreasestheswitchingoffsetvalue.

Rev. 1.40 160 ��st �� 01� Rev. 1.40 161 ��st �� 01�


Comparator RegistersTherearetworegistersforoverallcomparatoroperation,oneforeachcomparator.Ascorrespondingbits in the tworegistershave identical functions, they following register tableapplies tobothregisters.

RegisterName

Bit

7 6 5 4 3 2 1 0CP0C — C0EN C0POL C0OUT — — — C0HYENCP1C — C1EN C1POL C1OUT — — — C1HYEN

Comparator Registers List

CP0C Register

Bit 7 6 5 4 3 2 1 0Name — C0EN C0POL C0OUT — — — C0HYENR/W — R/W R/W R — — — R/WPOR — 0 0 0 — — — 1

Bit7 Unimplemented,readas"0"Bit6 C0EN:ComparatorOn/Offcontrol

0:Off1:On

This is theComparatoron/offcontrolbit. If thebit iszero thecomparatorwillbeswitchedoffandnopowerconsumedevenifanalogvoltagesareappliedtoitsinputs.ForpowersensitiveapplicationsthisbitshouldbeclearedtozeroifthecomparatorisnotusedorbeforethedevicesentertheSLEEPorIDLEmode.

Bit5 C0POL:Comparatoroutputpolarity0:Outputnotinverted1:Outputinverted

Thisisthecomparatorpolaritybit.If thebit iszerothentheC0OUTbitwillreflectthenon-invertedoutputconditionofthecomparator.IfthebitishighthecomparatorC0OUTbitwillbeinverted.

Bit4 C0OUT:ComparatoroutputbitC0POL=00:C0+<C0-1:C0+>C0-

C0POL=10:C0+>C0-1:C0+<C0-

Thisbitstoresthecomparatoroutputbit.ThepolarityofthebitisdeterminedbythevoltagesonthecomparatorinputsandbytheconditionoftheC0POLbit.

Bit3~1 Unimplemented,readas"0"Bit0 C0HYEN:HysteresisControl

0:Off1:On

This is thehysteresis controlbit and if sethighwill applya limitedamountofhysteresistothecomparator,asspecifiedintheComparatorElectricalCharacteristicstable.Thepositive feedback inducedbyhysteresis reduces theeffectofspuriousswitchingnearthecomparatorthreshold.

Rev. 1.40 160 ��st �� 01� Rev. 1.40 161 ��st �� 01�


CP1C RegisterBit 7 6 5 4 3 2 1 0

Name — C1EN C1POL C1OUT — — — C1HYENR/W — R/W R/W R — — — R/WPOR — 0 0 0 — — — 1

Bit7 Unimplemented,readas"0"Bit6 C1EN:ComparatorOn/Offcontrol

0:Off1:On

This is theComparatoron/offcontrolbit. If thebit iszero thecomparatorwillbeswitchedoffandnopowerconsumedevenifanalogvoltagesareappliedtoitsinputs.ForpowersensitiveapplicationsthisbitshouldbeclearedtozeroifthecomparatorisnotusedorbeforethedevicesentertheSLEEPorIDLEmode.

Bit5 C1POL:Comparatoroutputpolarity0:Outputnotinverted1:Outputinverted

Thisisthecomparatorpolaritybit.If thebit iszerothentheC1OUTbitwillreflectthenon-invertedoutputconditionofthecomparator.IfthebitishighthecomparatorC1OUTbitwillbeinverted.

Bit4 C1OUT:ComparatoroutputbitC1POL=00:C1+<C1-1:C1+>C1-

C1POL=10:C1+>C1-1:C1+<C1-

Thisbitstoresthecomparatoroutputbit.ThepolarityofthebitisdeterminedbythevoltagesonthecomparatorinputsandbytheconditionoftheC1POLbit.

Bit3~1 Unimplemented,readas"0"Bit0 C1HYEN:HysteresisControl

0:Off1:On

This is thehysteresis controlbit and if sethighwill applya limitedamountofhysteresistothecomparator,asspecifiedintheComparatorElectricalCharacteristicstable.Thepositive feedback inducedbyhysteresis reduces theeffectofspuriousswitchingnearthecomparatorthreshold.

Rev. 1.40 16� ��st �� 01� Rev. 1.40 163 ��st �� 01�


Comparator InterruptEachalsopossesses itsowninterrupt function.Whenanyoneof thechangesstate, its relevantinterruptflagwillbeset,andif thecorrespondinginterruptenablebit isset, thena jumpto itsrelevantinterruptvectorwillbeexecuted.NotethatitisthechangingstateoftheC0OUTorC1OUTbitandnottheoutputpinwhichgeneratesaninterrupt.If themicrocontroller is intheSLEEPorIDLEModeandtheComparatorisenabled,thenif theexternalinputlinescausetheComparatoroutputtochangestate, theresultinggeneratedinterruptflagwillalsogenerateawake-up.If it isrequiredtodisableawake-upfromoccurring,thentheinterruptflagshouldbefirstsethighbeforeenteringtheSLEEPorIDLEMode.

Programming ConsiderationsIf thecomparator isenabled, itwillremainactivewhenthemicrocontrollerenters theSLEEPorIDLEMode,howeverasitwillconsumeacertainamountofpower,theusermaywishtoconsiderdisablingitbeforetheSLEEPorIDLEModeisentered.

AscomparatorpinsaresharedwithnormalI/OpinstheI/Oregistersforthesepinswillbereadaszero(portcontrolregisteris"1")orreadasportdataregistervalue(portcontrolregisteris"0")ifthecomparatorfunctionisenabled.

Serial Interface Module – SIMThesedevicescontainaSerialInterfaceModule,whichincludesboththefour-lineSPIinterfaceortwo-lineI2Cinterfacetypes, toallowaneasymethodofcommunicationwithexternalperipheralhardware.Havingrelativelysimplecommunicationprotocols, theseserial interface typesallowthemicrocontroller to interface toexternalSPIorI2Cbasedhardwaresuchassensors,FlashorEEPROMmemory,etc.TheSIMinterfacepinsarepin-sharedwithotherI/OpinsandthereforetheSIMinterfacefunctionalpinsmustfirstbeselectedusingthecorrespondingpin-sharedfunctionselectionbits.Asbothinterfacetypessharethesamepinsandregisters, thechoiceofwhethertheSPIorI2CtypeisusedismadeusingtheSIMoperatingmodecontrolbits,namedSIM2~SIM0,intheSIMC0register.Thesepull-highresistorsoftheSIMpin-sharedI/Opinsareselectedusingpull-highcontrolregisterswhentheSIMfunctionisenabledandthecorrespondingpinsareusedasSIMinputpins.

SPI InterfaceTheSPIinterfaceisoftenusedtocommunicatewithexternalperipheraldevicessuchassensors,FlashorEEPROMmemorydevicesetc.OriginallydevelopedbyMotorola, the four lineSPIinterfaceisasynchronousserialdatainterfacethathasarelativelysimplecommunicationprotocolsimplifyingtheprogrammingrequirementswhencommunicatingwithexternalhardwaredevices.

Thecommunicationisfullduplexandoperatesasaslave/mastertype,wherethedevicescanbeeithermasterorslave.AlthoughtheSPIinterfacespecificationcancontrolmultipleslavedevicesfromasinglemaster,butthesedevicesprovidedonlyoneSCSpin.If themasterneedstocontrolmultipleslavedevicesfromasinglemaster,themastercanuseI/Opintoselecttheslavedevices.

Rev. 1.40 16� ��st �� 01� Rev. 1.40 163 ��st �� 01�


SPI Interface OperationTheSPIinterfaceisafullduplexsynchronousserialdatalink.It isafourlineinterfacewithpinnamesSDI,SDO,SCKandSCSPinsSDIandSDOaretheSerialDataInputandSerialDataOutputlines,SCKistheSerialClocklineandSCSistheSlaveSelectline.AstheSPIinterfacepinsarepin-sharedwithnormalI/OpinsandwiththeI2Cfunctionpins, theSPIinterfacepinsmustfirstbeselectedbyconfiguringthepin-sharedfunctionselectionbitsandsettingthecorrectbitsintheSIMC0andSIMC2registers.AfterthedesiredSPIconfigurationhasbeensetitcanbedisabledorenabledusingtheSIMENbit in theSIMC0register.Communicationbetweendevicesconnectedto theSPI interface iscarriedout inaslave/mastermodewithalldata transfer initiationsbeingimplementedbythemaster.TheMasteralsocontrolstheclocksignal.AsthedeviceonlycontainsasingleSCSpinonlyoneslavedevicecanbeutilized.TheSCSpiniscontrolledbysoftware,setCSENbitto1toenableSCSpinfunction,setCSENbitto0theSCSpinwillbefloatingstate.

TheSPIfunctioninthisdeviceoffersthefollowingfeatures:

• Fullduplexsynchronousdatatransfer

• BothMasterandSlavemodes

• LSBfirstorMSBfirstdatatransmissionmodes

• Transmissioncompleteflag

• Risingorfallingactiveclockedge

ThestatusoftheSPIinterfacepinsisdeterminedbyanumberoffactorssuchaswhetherthedeviceis in themasterorslavemodeandupontheconditionofcertaincontrolbitssuchasCSENandSIMEN.

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SPI Master/Slave Connection

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SPI Bolck Diagram

Rev. 1.40 164 ��st �� 01� Rev. 1.40 165 ��st �� 01�


SPI RegistersTherearethreeinternalregisterswhichcontroltheoveralloperationoftheSPIinterface.ThesearetheSIMDdataregisterandtworegistersSIMC0andSIMC2.NotethattheSIMC1registerisonlyusedbytheI2Cinterface.

Register Name

Bit

7 6 5 4 3 2 1 0SIMC0 SIM� SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN —SIMD D� D6 D5 D4 D3 D� D1 D0

SIMC� D� D6 CKPOLB CKEG MLS CSEN WCOL TRF

SIM Registers List

TheSIMDregisterisusedtostorethedatabeingtransmittedandreceived.ThesameregisterisusedbyboththeSPIandI2Cfunctions.BeforethedeviceswritedatatotheSPIbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheSPIbus,thedevicescanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheSPIbusmustbemadeviatheSIMDregister.

SIMD Register

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

“x”: �nknownTherearealsotwocontrolregistersfortheSPIinterface,SIMC0andSIMC2.NotethattheSIMC2registeralsohasthenameSIMAwhichisusedbytheI2Cfunction.TheSIMC1registerisnotusedbytheSPIfunction,onlybytheI2Cfunction.RegisterSIMC0isusedtocontroltheenable/disablefunctionandtoset thedata transmissionclockfrequency.Althoughnotconnectedwith theSPIfunction,theSIMC0registerisalsousedtocontrolthePeripheralClockPrescaler.RegisterSIMC2isusedforothercontrolfunctionssuchasLSB/MSBselection,writecollisionflagetc.

Rev. 1.40 164 ��st �� 01� Rev. 1.40 165 ��st �� 01�


SIMC0 Register

Bit 7 6 5 4 3 2 1 0Name SIM� SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN —R/W R/W R/W R/W — R/W R/W R/W —POR 1 1 1 — 0 0 0 —

Bit7~5 SIM2, SIM1, SIM0: SIMOperatingModeControl000:SPImastermode;SPIclockisfSYS/4001:SPImastermode;SPIclockisfSYS/16010:SPImastermode;SPIclockisfSYS/64011:SPImastermode;SPIclockisfSUB

100:SPImastermode;SPIclockisTM0CCRPmatchfrequency/2101:SPIslavemode110:I2Cslavemode111:NonSIMfunction

ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.AswellasselectingiftheI2CorSPIfunction,theyareusedtocontroltheSPIMaster/SlaveselectionandtheSPIMasterclockfrequency.TheSPIclockisafunctionofthesystemclockbutcanalsobechosentobesourcedfromTM0.IftheSPISlaveModeisselectedthentheclockwillbesuppliedbyanexternalMasterdevices.

Bit4 Unimplemented,readas"0"Bit3~2 SIMDEB1~SIMDEB0:I2CDebounceTimeSelection

00:Nodebounce01:2systemclockdebounce1x:4systemclockdebounce

Bit1 SIMEN:SIMControl0:Disable1:Enable

Thebit is theoverallon/offcontrolfor theSIMinterface.WhentheSIMENbit isclearedtozerotodisabletheSIMinterface,theSDI,SDO,SCKandSCS,orSDAandSCLlineswill losetheirSPIorI2CfunctionandtheSIMoperatingcurrentwillbereducedtoaminimumvalue.WhenthebitishightheSIMinterfaceisenabled.TheSIMconfigurationoptionmusthavefirstenabledtheSIMinterfaceforthisbittobeeffective.IftheSIMisconfiguredtooperateasanSPIinterfaceviatheSIM2~SIM0bits,thecontentsoftheSPIcontrolregisterswillremainattheprevioussettingswhentheSIMENbitchangesfromlowtohighandshouldthereforebefirst initialisedbytheapplicationprogram.IftheSIMisconfiguredtooperateasanI2CinterfaceviatheSIM2~SIM0bitsandtheSIMENbitchangesfromlowtohigh,thecontentsoftheI2CcontrolbitssuchasHTXandTXAKwillremainattheprevioussettingsandshouldthereforebefirst initialisedbytheapplicationprogramwhile therelevantI2CflagssuchasHCF,HAAS,HBB,SRWandRXAKwillbesettotheirdefaultstates.

Bit0 Unimplemented,readas"0"

Rev. 1.40 166 ��st �� 01� Rev. 1.40 16� ��st �� 01�


SIMC2 Register

Bit 7 6 5 4 3 2 1 0Name D� D6 CKPOLB CKEG MLS CSEN WCOL TRFR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 UndefinedbitThisbitcanbereadorwrittenbytheapplicationprogram.

Bit5 CKPOLB:Determinesthebaseconditionoftheclockline0:TheSCKlinewillbehighwhentheclockisinactive1:TheSCKlinewillbelowwhentheclockisinactive

TheCKPOLBbitdeterminesthebaseconditionoftheclockline, if thebit ishigh,thentheSCKlinewillbelowwhentheclockisinactive.WhentheCKPOLBbitislow,thentheSCKlinewillbehighwhentheclockisinactive.

Bit4 CKEG:DeterminesSPISCKactiveclockedgetypeCKPOLB=00:SCKishighbaselevelanddatacaptureatSCKrisingedge1:SCKishighbaselevelanddatacaptureatSCKfallingedge

CKPOLB=10:SCKislowbaselevelanddatacaptureatSCKfallingedge1:SCKislowbaselevelanddatacaptureatSCKrisingedge

TheCKEGandCKPOLBbitsareusedtosetupthewaythattheclocksignaloutputsandinputsdataontheSPIbus.Thesetwobitsmustbeconfiguredbeforedatatransferisexecutedotherwiseanerroneousclockedgemaybegenerated.TheCKPOLBbitdeterminesthebaseconditionoftheclockline, if thebit ishigh,thentheSCKlinewillbelowwhentheclockisinactive.WhentheCKPOLBbitislow,thentheSCKlinewillbehighwhentheclockis inactive.TheCKEGbitdeterminesactiveclockedgetypewhichdependsupontheconditionofCKPOLBbit.

Bit3 MLS:SPIDatashiftorder0:LSB1:MSB

Thisisthedatashiftselectbitandisusedtoselecthowthedataistransferred,eitherMSBorLSBfirst.SettingthebithighwillselectMSBfirstandlowforLSBfirst.

Bit2 CSEN:SPISCSpinControl0:Disable1:Enable

TheCSENbitisusedasanenable/disablefortheSCSpin.Ifthisbitislow,thentheSCSpinwillbedisabledandplacedintoI/Opinortheotherfunctions.If thebit ishightheSCSpinwillbeenabledandusedasaselectpin.

Bit1 WCOL:SPIWriteCollisionflag0:Nocollision1:Collision

TheWCOLflagisusedtodetectifadatacollisionhasoccurred.IfthisbitishighitmeansthatdatahasbeenattemptedtobewrittentotheSIMDregisterduringadatatransferoperation.Thiswritingoperationwillbeignoredifdataisbeingtransferred.Thebitcanbeclearedbytheapplicationprogram.

Bit0 TRF:SPITransmit/ReceiveCompleteflag0:Dataisbeingtransferred1:SPIdatatransmissioniscompleted

TheTRFbitistheTransmit/ReceiveCompleteflagandisset“1”automaticallywhenanSPIdatatransmissioniscompleted,butmustsetto“0”bytheapplicationprogram.Itcanbeusedtogenerateaninterrupt.

Rev. 1.40 166 ��st �� 01� Rev. 1.40 16� ��st �� 01�


SPI CommunicationAftertheSPIinterfaceisenabledbysettingtheSIMENbithigh,thenintheMasterMode,whendataiswrittentotheSIMDregister, transmission/receptionwillbeginsimultaneously.Whenthedata transfer iscomplete, theTRFflagwillbesetautomatically,butmustbeclearedusing theapplicationprogram.IntheSlaveMode,whentheclocksignalfromthemasterhasbeenreceived,anydataintheSIMDregisterwillbetransmittedandanydataontheSDIpinwillbeshiftedintotheSIMDregister.ThemastershouldoutputanSCSsignal toenable theslavedevicesbeforeaclocksignalisprovided.TheslavedatatobetransferredshouldbewellpreparedattheappropriatemomentrelativetotheSCSsignaldependingupontheconfigurationsoftheCKPOLBbitandCKEGbit.TheaccompanyingtimingdiagramshowstherelationshipbetweentheslavedataandSCSsignalforvariousconfigurationsoftheCKPOLBandCKEGbits.

TheSPIwillcontinuetofunctionevenintheIDLEMode.

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SPI Master Mode Timing

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SPI Slave Mode Timing – CKEG=0

Rev. 1.40 16� ��st �� 01� Rev. 1.40 169 ��st �� 01�


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SPI Slave Mode Timing – CKEG=1

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SPI Transfer Control Flowchart

Rev. 1.40 16� ��st �� 01� Rev. 1.40 169 ��st �� 01�


I2C InterfaceThe I2C interface isused to communicatewith externalperipheraldevices suchas sensors,EEPROMmemoryetc.OriginallydevelopedbyPhilips,it isatwolinelowspeedserialinterfaceforsynchronousserialdatatransfer.Theadvantageofonlytwolinesforcommunication,relativelysimplecommunicationprotocolandtheabilitytoaccommodatemultipledevicesonthesamebushasmadeitanextremelypopularinterfacetypeformanyapplications.

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I2C Master Slave Bus Connection

I2C Interface OperationTheI2Cserialinterfaceisatwolineinterface,aserialdataline,SDA,andserialclockline,SCL.Asmanydevicesmaybeconnectedtogetheronthesamebus,theiroutputsarebothopendraintypes.Forthisreasonitisnecessarythatexternalpull-highresistorsareconnectedtotheseoutputs.Notethatnochipselectlineexists,aseachdeviceontheI2CbusisidentifiedbyauniqueaddresswhichwillbetransmittedandreceivedontheI2Cbus.

WhentwodevicescommunicatewitheachotheronthebidirectionalI2Cbus,oneisknownasthemasterdeviceandoneas theslavedevice.Bothmasterandslavecantransmitandreceivedata,however, it isthemasterdevicethathasoverallcontrolofthebus.Forthesedevices,whichonlyoperateinslavemode,therearetwomethodsoftransferringdataontheI2Cbus,theslavetransmitmodeandtheslavereceivemode.

TheSIMDEB1andSIMDEB0bitsdetermine thedebounce timeof theI2Cinterface.Thisusesthesystemclockto ineffectaddadebouncetimeto theexternalclocktoreducethepossibilityofglitchesontheclocklinecausingerroneousoperation.Thedebouncetime, ifselected,canbechosen tobeeither2or4systemclocks.Toachieve therequiredI2Cdata transferspeed, thereexistsarelationshipbetweenthesystemclock,fSYS,andtheI2Cdebouncetime.ForeithertheI2CStandardorFastmodeoperation,usersmusttakecareoftheselectedsystemclockfrequencyandtheconfigureddebouncetimetomatchthecriterionshowninthefollowingtable.

I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz)No debo�nce fSYS > �MHz fSYS > 5MHz� system clock debo�nce fSYS > 4MHz fSYS > 10MHz4 system clock debo�nce fSYS > �MHz fSYS > �0MHz

I2C Minimum fSYS Frequency

Rev. 1.40 1�0 ��st �� 01� Rev. 1.40 1�1 ��st �� 01�


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I2C RegistersTherearethreecontrolregistersassociatedwiththeI2Cbus,SIMC0,SIMC1andSIMA,andonedataregister,SIMD.TheSIMDregister,whichisshownintheaboveSPIsection,isusedtostorethedatabeingtransmittedandreceivedontheI2Cbus.BeforethemicrocontrollerwritesdatatotheI2Cbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheI2Cbus,themicrocontrollercanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheI2CbusmustbemadeviatheSIMDregister.

NotethattheSIMAregisteralsohasthenameSIMC2whichisusedbytheSPIfunction.BitSIMENandbitsSIM2~SIM0inregisterSIMC0areusedbytheI2Cinterface.

Register Name

Bit

7 6 5 4 3 2 1 0SIMC0 SIM� SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN —SIMC1 HCF H�NS HBB HTX TX�K SRW I�MWU RX�KSIMD D� D6 D5 D4 D3 D� D1 D0SIM� IIC�6 IIC�5 IIC�4 IIC�3 IIC�� IIC�1 IIC�0 D0

I2C Registers List

Rev. 1.40 1�0 ��st �� 01� Rev. 1.40 1�1 ��st �� 01�


SIMC0 Register

Bit 7 6 5 4 3 2 1 0Name SIM� SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN —R/W R/W R/W R/W — R/W R/W R/W —POR 1 1 1 — 0 0 0 —

Bit7~5 SIM2, SIM1, SIM0: SIMOperatingModeControl000:SPImastermode;SPIclockisfSYS/4001:SPImastermode;SPIclockisfSYS/16010:SPImastermode;SPIclockisfSYS/64011:SPImastermode;SPIclockisfSUB

100:SPImastermode;SPIclockisTM0CCRPmatchfrequency/2101:SPIslavemode110:I2Cslavemode111:Unusedmode

ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.AswellasselectingiftheI2CorSPIfunction,theyareusedtocontroltheSPIMaster/SlaveselectionandtheSPIMasterclockfrequency.TheSPIclockisafunctionofthesystemclockbutcanalsobechosentobesourcedfromtheTM0.IftheSPISlaveModeisselectedthentheclockwillbesuppliedbyanexternalMasterdevice.

Bit4 Unimplemented,readas"0"Bit3~2 SIMDEB1~SIMDEB0:I2CDebounceTimeSelection

00:Nodebounce01:2systemclockdebounce1x:4systemclockdebounce

Bit1 SIMEN:SIMControl0:Disable1:Enable

Thebit is theoverallon/offcontrolfor theSIMinterface.WhentheSIMENbit isclearedtozerotodisabletheSIMinterface, theSDI,SDO,SCKandSCS,orSDAandSCLlineswillbeinafloatingconditionandtheSIMoperatingcurrentwillbereducedtoaminimumvalue.WhenthebitishightheSIMinterfaceisenabled.TheSIMconfigurationoptionmusthavefirstenabledtheSIMinterfaceforthisbittobeeffective.IftheSIMisconfiguredtooperateasanSPIinterfaceviaSIM2~SIM0bits,thecontentsoftheSPIcontrolregisterswillremainattheprevioussettingswhentheSIMENbitchangesfromlowtohighandshouldthereforebefirst initialisedbytheapplicationprogram.If theSIMisconfiguredtooperateasanI2CinterfaceviatheSIM2~SIM0bitsandtheSIMENbitchangesfromlowtohigh,thecontentsoftheI2CcontrolbitssuchasHTXandTXAKwillremainattheprevioussettingsandshouldthereforebefirst initialisedbytheapplicationprogramwhile therelevantI2CflagssuchasHCF,HAAS,HBB,SRWandRXAKwillbesettotheirdefaultstates.

Bit0 Unimplemented,readas"0"

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�3 ��st �� 01�


SIMC1 Register

Bit 7 6 5 4 3 2 1 0Name HCF H��S HBB HTX TX�K SRW I�MWU RX�KR/W R R R R/W R/W R R/W RPOR 1 0 0 0 0 0 0 1

Bit7 HCF:I2CBusdatatransfercompletionflag0:Dataisbeingtransferred1:Completionofan8-bitdatatransfer

TheHCFflag is thedata transfer flag.This flagwillbezerowhendata isbeingtransferred.Uponcompletionofan8-bitdata transfer theflagwillgohighandaninterruptwillbegenerated.

Bit6 HAAS:I2CBusaddressmatchflag0:Notaddressmatch1:Addressmatch

TheHAASflagistheaddressmatchflag.Thisflagisusedtodetermineiftheslavedeviceaddressisthesameasthemastertransmitaddress.Iftheaddressesmatchthenthisbitwillbehigh,ifthereisnomatchthentheflagwillbelow.

Bit5 HBB:I2CBusbusyflag0:I2CBusisnotbusy1:I2CBusisbusy

TheHBBflagis theI2Cbusyflag.Thisflagwillbe“1”whentheI2Cbus isbusywhichwilloccurwhenaSTARTsignalisdetected.Theflagwillbesetto“0”whenthebusisfreewhichwilloccurwhenaSTOPsignalisdetected.

Bit4 HTX:SelectI2Cslavedeviceistransmitterorreceiver0:Slavedeviceisthereceiver1:Slavedeviceisthetransmitter

Bit3 TXAK:I2CBustransmitacknowledgeflag0:Slavesendacknowledgeflag1:Slavedonotsendacknowledgeflag

TheTXAKbitisthetransmitacknowledgeflag.Aftertheslavedevicereceiptof8-bitsofdata,thisbitwillbetransmittedtothebusonthe9thclockfromtheslavedevice.TheslavedevicemustalwayssetTXAKbitto“0”beforefurtherdataisreceived.

Bit2 SRW:I2CSlaveRead/Writeflag0:Slavedeviceshouldbeinreceivemode1:Slavedeviceshouldbeintransmitmode

TheSRWflag is the I2CSlaveRead/Write flag.This flagdetermineswhetherthemasterdevicewishes to transmitor receivedata fromthe I2Cbus.When thetransmittedaddressandslaveaddressismatch,thatiswhentheHAASflagissethigh,theslavedevicewillchecktheSRWflagtodeterminewhetheritshouldbeintransmitmodeorreceivemode.IftheSRWflagishigh,themasterisrequestingtoreaddatafromthebus,so theslavedeviceshouldbe in transmitmode.WhentheSRWflagiszero,themasterwillwritedatatothebus,thereforetheslavedeviceshouldbeinreceivemodetoreadthisdata.

Bit1 IAMWU:I2CAddressMatchWake-upControl0:Disable1:Enable-mustbeclearedbytheapplicationprogramafterwake-up

Thisbitshouldbesetto1toenabletheI2CaddressmatchwakeupfromtheSLEEPorIDLEMode.IftheIAMWUbithasbeensetbeforeenteringeithertheSLEEPorIDLEmodetoenabletheI2Caddressmatchwakeup,thenthisbitmustbeclearedbytheapplicationprogramafterwake-uptoensurecorrectiondeviceoperation.

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�3 ��st �� 01�


Bit0 RXAK:I2CBusReceiveacknowledgeflag0:Slavereceiveacknowledgeflag1:Slavedoesnotreceiveacknowledgeflag

TheRXAKflag is thereceiveracknowledgeflag.WhentheRXAKflag is“0”, itmeansthataacknowledgesignalhasbeenreceivedatthe9thclock,after8bitsofdatahavebeentransmitted.Whentheslavedeviceinthetransmitmode,theslavedevicecheckstheRXAKflagtodetermineifthemasterreceiverwishestoreceivethenextbyte.Theslavetransmitterwill thereforecontinuesendingoutdatauntil theRXAKflagis“1”.Whenthisoccurs,theslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.

TheSIMDregisterisusedtostorethedatabeingtransmittedandreceived.ThesameregisterisusedbyboththeSPIandI2Cfunctions.BeforethedeviceswritedatatotheSPIbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheSPIbus,thedevicescanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheSPIbusmustbemadeviatheSIMDregister.

SIMD Register

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x X x x x x x x

“x”: �nknown

SIMA Register

Bit 7 6 5 4 3 2 1 0Name IIC�6 IIC�5 IIC�4 IIC�3 IIC�� IIC�1 IIC�0 —R/W R/W R/W R/W R/W R/W R/W R/W —POR x X x x x x x —

“x”: �nknownBit7~1 IICA6~IICA0:I2Cslaveaddress

IICA6~IICA0istheI2Cslaveaddressbit6~bit0TheSIMAregister isalsousedbytheSPI interfacebuthas thenameSIMC2.TheSIMAregister is the locationwhere the7-bitslaveaddressof theslavedevice isstored.Bits7~1of theSIMAregisterdefine thedeviceslaveaddress.Bit0 isnotdefined.Whenamasterdevice,whichisconnectedtotheI2Cbus,sendsoutanaddress,whichmatchestheslaveaddressintheSIMAregister,theslavedevicewillbeselected.NotethattheSIMAregisteristhesameregisteraddressasSIMC2whichisusedbytheSPIinterface.

Bit0 UndefinedbitThisbitcanbereadorwrittenbyusersoftwareprogram.

Rev. 1.40 1�4 ��st �� 01� Rev. 1.40 1�5 ��st �� 01�


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I2C Block Diagram

I2C Bus CommunicationCommunicationontheI2Cbusrequiresfourseparatesteps,aSTARTsignal,aslavedeviceaddresstransmission,adatatransmissionandfinallyaSTOPsignal.WhenaSTARTsignal isplacedontheI2Cbus,alldevicesonthebuswillreceivethissignalandbenotifiedoftheimminentarrivalofdataonthebus.ThefirstsevenbitsofthedatawillbetheslaveaddresswiththefirstbitbeingtheMSB.Iftheaddressoftheslavedevicematchesthatofthetransmittedaddress,theHAASbitintheSIMC1registerwillbesetandanI2Cinterruptwillbegenerated.Afterenteringtheinterruptserviceroutine,theslavedevicemustfirstchecktheconditionoftheHAASbittodeterminewhethertheinterruptsourceoriginatesfromanaddressmatchorfromthecompletionofan8-bitdatatransfer.Duringadatatransfer,notethatafterthe7-bitslaveaddresshasbeentransmitted,thefollowingbit,whichisthe8thbit,istheread/writebitwhosevaluewillbeplacedintheSRWbit.Thisbitwillbecheckedbytheslavedevicetodeterminewhethertogointotransmitorreceivemode.BeforeanytransferofdatatoorfromtheI2Cbus,themicrocontrollermustinitialisethebus,thefollowingarestepstoachievethis:

• Step1SettheSIM2~SIM0andSIMENbitsintheSIMC0registerto“1”toenabletheI2Cbus.

• Step2WritetheslaveaddressofthedevicetotheI2CbusaddressregisterSIMA.

• Step3Set theSIMEandSIMMuti-Function interruptenablebitof the interruptcontrol register toenabletheSIMinterruptandMulti-functioninterrupt.

Rev. 1.40 1�4 ��st �� 01� Rev. 1.40 1�5 ��st �� 01�


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I2C Bus Initialisation Flow Chart

I2C Bus Start SignalTheSTARTsignalcanonlybegeneratedbythemasterdeviceconnectedtotheI2Cbusandnotbytheslavedevice.ThisSTARTsignalwillbedetectedbyalldevicesconnectedtotheI2Cbus.Whendetected, this indicates that theI2Cbus isbusyandtherefore theHBBbitwillbeset.ASTARTconditionoccurswhenahigh to lowtransitionon theSDAline takesplacewhentheSCLlineremainshigh.

Slave AddressThetransmissionofaSTARTsignalbythemasterwillbedetectedbyalldevicesontheI2Cbus.Todeterminewhichslavedevicethemasterwishestocommunicatewith,theaddressoftheslavedevicewillbesentoutimmediatelyfollowingtheSTARTsignal.Allslavedevices,afterreceivingthis7-bitaddressdata,willcompareitwiththeirown7-bitslaveaddress.Iftheaddresssentoutbythemastermatchestheinternaladdressofthemicrocontrollerslavedevice,thenaninternalI2Cbusinterruptsignalwillbegenerated.Thenextbitfollowingtheaddress,whichisthe8thbit,definestheread/writestatusandwillbesavedtotheSRWbitoftheSIMC1register.Theslavedevicewillthentransmitanacknowledgebit,whichisalowlevel,asthe9thbit.TheslavedevicewillalsosetthestatusflagHAASwhentheaddressesmatch.

Asan I2Cbus interrupt cancome from two sources,when theprogramenters the interruptsubroutine,theHAASbitshouldbeexaminedtoseewhethertheinterruptsourcehascomefromamatchingslaveaddressorfromthecompletionofadatabytetransfer.Whenaslaveaddressismatched,thedevicesmustbeplacedineitherthetransmitmodeandthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheSIMDregistertoreleasetheSCLline.

Rev. 1.40 1�6 ��st �� 01� Rev. 1.40 1�� st �� 01�


I2C Bus Read/Write SignalTheSRWbitintheSIMC1registerdefineswhethertheslavedevicewishestoreaddatafromtheI2CbusorwritedatatotheI2Cbus.Theslavedeviceshouldexaminethisbittodetermineifitistobeatransmitterorareceiver.IftheSRWflagis“1”thenthisindicatesthatthemasterdevicewishestoreaddatafromtheI2Cbus,thereforetheslavedevicemustbesetuptosenddatatotheI2Cbusasatransmitter.IftheSRWflagis“0”thenthisindicatesthatthemasterwishestosenddatatotheI2Cbus,thereforetheslavedevicemustbesetuptoreaddatafromtheI2Cbusasareceiver.

I2C Bus Slave Address Acknowledge SignalAfter themasterhas transmitted a calling address, any slavedeviceon the I2Cbus,whoseown internaladdressmatches thecallingaddress,mustgenerateanacknowledgesignal.Theacknowledgesignalwillinformthemasterthataslavedevicehasaccepteditscallingaddress.IfnoacknowledgesignalisreceivedbythemasterthenaSTOPsignalmustbetransmittedbythemastertoendthecommunication.WhentheHAASflagishigh,theaddresseshavematchedandtheslavedevicemustchecktheSRWflagtodetermineifitistobeatransmitterorareceiver.IftheSRWflagishigh,theslavedeviceshouldbesetuptobeatransmittersotheHTXbitintheSIMC1registershouldbesetto“1”.IftheSRWflagislow,thenthemicrocontrollerslavedeviceshouldbesetupasareceiverandtheHTXbitintheSIMC1registershouldbesetto“0”.

I2C Bus Data and Acknowledge SignalThe transmitteddata is8-bitswideand is transmittedafter theslavedevicehasacknowledgedreceiptofitsslaveaddress.TheorderofserialbittransmissionistheMSBfirstandtheLSBlast.Afterreceiptof8-bitsofdata,thereceivermusttransmitanacknowledgesignal,level“0”,beforeitcanreceivethenextdatabyte.Iftheslavetransmitterdoesnotreceiveanacknowledgebitsignalfromthemasterreceiver, thentheslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.ThecorrespondingdatawillbestoredintheSIMDregister.Ifsetupasatransmitter,theslavedevicemustfirstwritethedatatobetransmittedintotheSIMDregister.Ifsetupasareceiver,theslavedevicemustreadthetransmitteddatafromtheSIMDregister.

Whentheslavereceiver receives thedatabyte, itmustgenerateanacknowledgebit,knownasTXAK,onthe9thclock.Theslavedevice,whichissetupasatransmitterwillchecktheRXAKbitintheSIMC1registertodetermineifit istosendanotherdatabyte,ifnotthenitwillreleasetheSDAlineandawaitthereceiptofaSTOPsignalfromthemaster.

Rev. 1.40 1�6 ��st �� 01� Rev. 1.40 1�� st �� 01�


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Note:*Whenaslaveaddressismatched,thedevicesmustbeplacedineitherthetransmitmodeandthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheSIMDregistertoreleasetheSCLline.

I2C Communication Timing Diagram

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I2C Bus ISR flow Chart

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�9 ��st �� 01�


I2C Time-out ControlInordertoreducetheI2Clockupproblemduetoreceptionoferroneousclocksources,atime-outfunctionisprovided.IftheclocksourceconnectedtotheI2Cbusisnotreceivedforawhile,thentheI2Ccircuitryandregisterswillberesetafteracertaintime-outperiod.Thetime-outcounterstartstocountonanI2Cbus“START”&“addressmatch”condition,andisclearedbyanSCLfallingedge.Before thenextSCLfallingedgearrives, if the timeelapsedisgreater than the time-outperiodspecifiedbytheI2CTOCregister,thenatime-outconditionwilloccur.Thetime-outfunctionwillstopwhenanI2C“STOP”conditionoccurs.

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I2C Time-out

WhenanI2Ctime-outcounteroverflowoccurs,thecounterwillstopandtheI2CTOENbitwillbeclearedtozeroandtheI2CTFbitwillbesethightoindicatethatatime-outconditionhasoccurred.Thetime-outconditionwillalsogenerateaninterruptwhichusestheI2Cinterrruptvector.WhenanI2Ctime-outoccurs,theI2Cinternalcircuitrywillberesetandtheregisterswillberesetintothefollowingcondition:

Register After I2C Time-outSIMD� SIM�� SIMC0 No chan�eSIMC1 Reset to POR condition

I2C Registers after Time-out

TheI2CTOFflagcanbeclearedbytheapplicationprogram.Thereare64time-outperiodselectionswhichcanbeselectedusing theI2CTOSbits in theI2CTOCregister.The time-outduration iscalculatedbytheformula:((1~64)×(32/fSUB)).Thisgivesa time-outperiodwhichrangesfromabout1msto64ms.

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�9 ��st �� 01�


I2CTOC Register

Bit 7 6 5 4 3 2 1 0Name I�CTOEN I�CTOF I�CTOS5 I�CTOS4 I�CTOS3 I�CTOS� I�CTOS1 I�CTOS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 I2CTOEN:I2CTime-outControl0:Disable1:Enable

Bit6 I2CTOF:I2CTime-outflag0:Notime-outoccurred1:Time-outoccurred

Bit5~0 I2CTOS5~I2CTOS0:I2CTime-outTimeSelectionI2CTime-outclocksourceisfSUB/32I2CTime-outtimeisgivenby:(I2CTOS[5:0]+1)×(32/fSUB)

Peripheral Clock OutputThePeripheralClockOutputallowsthedevice tosupplyexternalhardwarewithaclocksignalsynchronisedtothemicrocontrollerclock.

Peripheral Clock OperationAstheperipheralclockoutputpin,PCK,issharedwithI/Oline,therequiredpinfunctionischosenusing therelevantpin-sharedfunctionselectionbit.ThePeripheralClockfunction iscontrolledusingtheTB2ENbit intheTBC2register.TheclocksourceforthePeripheralClockOutputcanoriginatefromthesystemclockfSYS,theinstructionclock,thehighspeedoscillatorclockfHorthefSUBclockwhichcanbeselectedbytheCLKS11andCLKS10bitsinthePSC1register.TheTB2ENbitintheTBC2registeristheoverallon/offcontrol,settingTB2ENbitto1enablesthePeripheralClockwhilesettingTB2ENbitto0disablesit.TherequireddivisionratiooftheperipheralclockisselectedusingtheTB22,TB21andTB20bitsintheTBC2register.Iftheperipheralclocksourceisswitchedoffwhenthedeviceentersthepowerdownmode,thiswilldisablethePeripheralClockoutput.

fSYS/4

fP

CLKS1[1:0 ]

fSUB

fSYS

fHPrescaler

TB�EN TB�[�:0 ]

fP/�0 ~ fP/��

PCK

Peripheral Clock Output

Rev. 1.40 1�0 ��st �� 01� Rev. 1.40 1�1 ��st �� 01�


Peripheral Clock RegistersTherearetwointernalregisterswhichcontroltheoveralloperationofthePeripheralClockOutput.ThesearethePSC1andTBC2registers.

NameBit

7 6 5 4 3 2 1 0PSC1 — — — — — — CLKS11 CLKS10TBC� TB�EN — — — — TB�� TB�1 TB�0

PCK Register List

PSC1 Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — CLKS11 CLKS10R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 CLKS11,CLKS10:PeripheralClockSourceselection

00:fSYS

01:fSYS/410:fSUB

11:fH

TBC2 Register

Bit 7 6 5 4 3 2 1 0Name TB�EN — — — — TB�� TB�1 TB�0R/W R/W — — — — R/W R/W R/WPOR 0 — — — — 0 0 0

Bit7 TB2EN:PeripheralClockFunctionenablecontrol0:Disable1:Enable

Bit6~3 Unimplemented,readas“0”Bit1~0 TB22,TB21, TB20: PeripheralClockoutputdivisionselection

000:fP

001:fP/2010:fP/4011:fP/8100:fP/16101:fP/32110:fP/64111:fP/128

Rev. 1.40 1�0 ��st �� 01� Rev. 1.40 1�1 ��st �� 01�


Serial Interface – SPIAThedevicecontainsanindependentSPIfunction.ItisimportantnottoconfusethisindependentSPIfunctionwiththeadditionalonecontainedwithinthecombinedSIMfunction,whichisdescribedinanothersectionof thisdatasheet.This independentSPIfunctionwillcarry thenameSPIAtodistinguishitfromtheotheroneintheSIM.

ThisSPIAinterfaceisoftenusedtocommunicatewithexternalperipheraldevicessuchassensors,FlashorEEPROMmemorydevices,etc.OriginallydevelopedbyMotorola, the four lineSPIinterfaceisasynchronousserialdatainterfacethathasarelativelysimplecommunicationprotocolsimplifyingtheprogrammingrequirementswhencommunicatingwithexternalhardwaredevices.

Thecommunication isfullduplexandoperatesasaslave/master type,where thedevicecanbeeithermasterorslave.AlthoughtheSPIAinterfacespecificationcancontrolmultipleslavedevicesfromasinglemaster, thisdevice isprovidedonlyoneSCSApin. If themasterneeds tocontrolmultipleslavedevicesfromasinglemaster,themastercanuseI/Opinstoselecttheslavedevices.

SPIA Interface OperationTheSPIAinterfaceisafullduplexsynchronousserialdatalink.ItisafourlineinterfacewithpinnamesSDIA,SDOA,SCKAandSCSA.PinsSDIAandSDOAaretheSerialDataInputandSerialDataOutput lines,SCKAistheSerialClocklineandSCSAistheSlaveSelect line.AstheSPIAinterfacepinsarepin-sharedwithotherfunctions, theSPIAinterfacepinsmustfirstbeselectedbyconfiguring thecorrespondingselectionbits in thepin-shared functionselection registers.TheSPIAinterfacefunctionisdisabledorenabledusingtheSPIAENbit intheSPIAC0register.CommunicationbetweendevicesconnectedtotheSPIAinterfaceiscarriedout inaslave/mastermodewithalldatatransferinitiationsbeingimplementedbythemaster.Themasteralsocontrolstheclock/signal.AsthedeviceonlycontainsasingleSCSApinonlyoneslavedevicecanbeutilised.

TheSCSApiniscontrolledbytheapplicationprogram,setthetheSACSENbitto“1”toenabletheSCSApinfunctionandcleartheSACSENbitto“0”toplacetheSCSApinintoanI/Ofunction.

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SPIA Master/Slave Connection

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�3 ��st �� 01�


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SPIA Block Diagram

TheSPIASerialInterfacefunctionincludesthefollowingfeatures:

• Full-duplexsynchronousdatatransfer

• BothMasterandSlavemode

• LSBfirstorMSBfirstdatatransmissionmodes

• Transmissioncompleteflag

• Risingorfallingactiveclockedge

Thestatusof theSPIAinterfacepins isdeterminedbyanumberoffactorssuchaswhether thedeviceisinthemasterorslavemodeandupontheconditionofcertaincontrolbitssuchasSACSENandSPIAEN.

SPIA registersTherearethreeregisterswhichcontrol theoveralloperationoftheSPIAinterface.ThesearetheSPIADdataregistersandtwocontrolregistersSPIAC0andSPIAC1.

RegisterName

Bit

7 6 5 4 3 2 1 0SPI�C0 S�SPI� S�SPI1 S�SPI0 — — — SPI�EN —SPI�C1 — — S�CKPOL S�CKEG S�MLS S�CSEN S�WCOL S�TRFSPI�D D� D6 D5 D4 D3 D� D1 D0

SPIA Registers List

TheSPIADregister isused tostore thedatabeing transmittedandreceived.Before thedevicewritesdatatothisSPIAbus,theactualdatatobetransmittedmustbeplacedintheSPIADregister.AfterthedataisreceivedfromtheSPIAbus,thedevicecanreaditfromtheSPIADregister.AnytransmissionorreceptionofdatafromtheSPIAbusmustbemadeviatheSPIADregisters.

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�3 ��st �� 01�


SPIAD Register

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR × × × × × × × ×

“×” �nknownTherearealsotwocontrolregistersfortheSPIAinterface,SPIAC0andSPIAC1.RegisterSPIAC0isused tocontrol theenable/disablefunctionand toset thedata transmissionclockfrequency.RegisterSPIAC1isusedforothercontrolfunctionssuchasLSB/MSBselection,writecollisionflag,etc.

SPIAC0 Register

Bit 7 6 5 4 3 2 1 0Name S�SPI� S�SPI1 S�SPI0 — — — SPI�EN —R/W R/W R/W R/W — — — R/W —POR 1 1 1 — — — 0 —

Bit7~5 SASPI2~SASPI0:SPIAMaster/SlaveClockSelect000:SPIAmaster,fSYS/4001:SPIAmaster,fSYS/16010:SPIAmaster,fSYS/64011:SPIAmaster,fSUB

100:SPIAmaster,TP0CCRPmatchfrequency/2(PFD)101:SPIAslave110:Reserved111:Reserved

Bit4~2 Unimplemented,readas“0”Bit1 SPIAEN:SPIAenableordisable

0:Disable1:Enable

Thebit is theoverallon/offcontrol for theSPIAinterface.WhentheSPIAENbitisclearedtozerotodisabletheSPIAinterface, theSDIA,SDOA,SCKAandSCSAlineswilllosetheirSPIfunctionandtheSPIAoperatingcurrentwillbereducedtoaminimumvalue.Whenthebitishigh,theSPIAinterfaceisenabled.

Bit0 Unimplemented,readas“0”

Rev. 1.40 1�4 ��st �� 01� Rev. 1.40 1�5 ��st �� 01�


SPIAC1 Register

Bit 7 6 5 4 3 2 1 0Name — — S�CKPOL S�CKEG S�MLS S�CSEN S�WCOL S�TRFR/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas“0”Bit5 SACKPOL:Determinesthebaseconditionoftheclockline

0:SCKAlinewillbehighwhentheclockisinactive1:SCKAlinewillbelowwhentheclockisinactive

TheSACKPOLbitdeterminesthebaseconditionoftheclockline,ifthebitishigh,thentheSCKAlinewillbelowwhentheclockisinactive.WhentheSACKPOLbitislow,thentheSCKAlinewillbehighwhentheclockisinactive.

Bit4 SACKEG:DeterminestheSPIASCKAactiveclockedgetypeSACKPOL=0:0:SCKAhashighbaselevelwithdatacaptureonSCKArisingedge1:SCKAhashighbaselevelwithdatacaptureonSCKAfallingedge

SACKPOL=1:0:SCKAhaslowbaselevelwithdatacaptureonSCKAfallingedge1:SCKAhaslowbaselevelwithdatacaptureonSCKArisingedge

TheSACKEGandSACKPOLbitsareused tosetup thewaythat theclocksignaloutputsandinputsdataontheSPIAbus.Thesetwobitsmustbeconfiguredbeforeadatatransfer isexecutedotherwiseanerroneousclockedgemaybegenerated.TheSACKPOLbitdeterminesthebaseconditionoftheclockline,ifthebitishigh,thentheSCKAlinewillbe lowwhentheclock is inactive.WhentheSACKPOLbit islow,thentheSCKAlinewillbehighwhentheclockis inactive.TheSACKEGbitdeterminesactiveclockedgetypewhichdependsupontheconditionoftheSACKPOLbit.

Bit3 SAMLS:datashiftorder0:TheLSBofdataistransmittedfirst1:TheMSBofdataistransmittedfirst

Bit2 SACSEN:SPIASCSApinControl0:Disable1:Enable

TheSACSENbitisusedasanenable/disablefortheSCSApin.Ifthisbitislow,thentheSCSApinfunctionwillbedisabledandusedasanI/Ofunction.IfthebitishightheSCSApinwillbeenabledandusedasaselectpin.

Bit1 SAWCOL:SPIAWriteCollisionflag0:Collisionfree1:Collisiondetected

TheSAWCOLflagisusedtodetectifadatacollisionhasoccurred.IfthisbitishighitmeansthatdatahasbeenattemptedtobewrittentotheSPIADregisterduringadatatransferoperation.Thiswritingoperationwillbeignoredifdataisbeingtransferred.Thebitcanbeclearedbytheapplicationprogram.

Bit0 SATRF:SPIATransmit/ReceiveCompleteflag0:Dataisbeingtransferred1:SPIAdatatransmissioniscompleted

TheSATRFbitistheTransmit/ReceiveCompleteflagandissetto“1”automaticallywhenanSPIAdata transmission is completed, butmust cleared to “0”by theapplicationprogram.Itcanbeusedtogenerateaninterrupt.

Rev. 1.40 1�4 ��st �� 01� Rev. 1.40 1�5 ��st �� 01�


SPIA CommunicationAftertheSPIAinterfaceisenabledbysettingtheSPIAENbithigh,thenintheMasterMode,whendataiswrittentotheSPIADregister, transmission/receptionwillbeginsimultaneously.Whenthedatatransferiscomplete, theSATRFflagwillbesetautomatically,butmustbeclearedusingtheapplicationprogram.IntheSlaveMode,whentheclocksignalfromthemasterhasbeenreceived,anydataintheSPIADregisterwillbetransmittedandanydataontheSDIApinwillbeshiftedintotheSPIADregisters.

ThemastershouldoutputaSCSAsignaltoenabletheslavedevicebeforeaclocksignalisprovided.Theslavedata tobe transferredshouldbewellpreparedat theappropriatemoment relative totheSCSAsignaldependingupontheconfigurationsof theSACKPOLbitandSACKEGbit.TheaccompanyingtimingdiagramshowstherelationshipbetweentheslavedataandSCSAsignalforvariousconfigurationsoftheSACKPOLandSACKEGbits.

TheSPIAwillcontinuetofunctionevenintheIDLEMode.

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SPIA Transfer Control Flowchart

Rev. 1.40 1�6 ��st �� 01� Rev. 1.40 1�� st �� 01�


D �/D 0 D 6/D 1 D 5/D � D 4/D 3 D 3/D 4 D �/D 5 D 1/D 6 D 0/D �


SPI� master mode

SDI� Data capt�re


(SDO� not chan�e �ntil first SCK� ed�e )

SPI� slave mode ( S�CKEG = 0)



(SDO� chan�e as soon as writin� occ�r ; SDO� = floatin� if =1)

SPI�EN =1� S�CSEN= 0 ( external p�ll-hi�h )

Write to SPI�D

Note :For SPI� slave mode � if SPI�EN=1 and S�CSEN =0 � SPI� is always enabled and i�nore the

SCK� (S�CKPOL=1� S�CKEG=0)

SDO� ( =0)

SCK� (S�CKPOL=1)

SCK� (S�CKPOL =0 )

SDO�

SCK� ( =0� =0 )

SCK� ( =1� =1)

SCK� ( =0� = )1

SDO� ( =1)

Write to SPI�D

Write to SPI�D

SPI� slave mode (S�CKEG =1)

SCS�

S�CKPOL S�CKEG

S�CKPOL S�CKEG

S�CKPOL S�CKEG

S�CKEG

S�CKEG

SPI�EN=1� S�CSEN= 1

SCS�

SCS�


SCK� (S�CKPOL=1

SCK� (S�CKPOL=0

SDO�

SCS�

)

)

SCS� level.

SPIA Master/Slave ModeTiming Diagram

Rev. 1.40 1�6 ��st �� 01� Rev. 1.40 1�� st �� 01�


SPIA Bus Enable/DisableToenable theSPIAbus,setSACSEN=1andSCSA=0, thenwait fordata tobewritten into theSPIAD(TXRXbuffer)register.For theMasterMode,afterdatahasbeenwrittento theSPIAD(TXRXbuffer)register,thentransmissionorreceptionwillstartautomatically.WhenallthedatahasbeentransferredtheSATRFbitshouldbeset.FortheSlaveMode,whenclockpulsesarereceivedonSCKA,dataintheTXRXbufferwillbeshiftedoutordataonSDIAwillbeshiftedin.

ToDisable theSPIAbusSCKA,SDIA,SDOA,SCSAwillbecomeI/Opinsorotherpin-sharedfunctions.

SPIA OperationAllcommunicationiscarriedoutusingthe4-lineinterfaceforeitherMasterorSlaveMode.

TheSACSENbitintheSPIAC1registercontrolstheoverallfunctionoftheSPIAinterface.SettingthisbithighwillenabletheSPIAinterfacebyallowingtheSCSAlinetobeactive,whichcanthenbeusedtocontroltheSPIAinterface.IftheSACSENbitislow,theSPIAinterfacewillbedisabledandtheSCSAlinewillbeanI/Opinorotherpin-sharedfunctionsandcanthereforenotbeusedforcontroloftheSPIAinterface.IftheSACSENbitandtheSPIAENbitintheSPIAC0registeraresethigh,thiswillplacetheSDIAlineinafloatingconditionandtheSDOAlinehigh.IfinMasterModetheSCKAlinewillbeeitherhighorlowdependingupontheclockpolarityselectionbitSACKPOLintheSPIAC1register.IfinSlaveModetheSCKAlinewillbeinafloatingcondition.IfSPIAENislowthenthebuswillbedisabledandSCSA,SDIA,SDOAandSCKApinswillallbecomeI/Opinsorotherpin-sharedfunctions.IntheMasterModetheMasterwillalwaysgeneratetheclocksignal.TheclockanddatatransmissionwillbeinitiatedafterdatahasbeenwrittenintotheSPIADregister.IntheSlaveMode,theclocksignalwillbereceivedfromanexternalmasterdeviceforbothdatatransmissionandreception.ThefollowingsequencesshowtheordertobefollowedfordatatransferinbothMasterandSlaveMode.

Master Mode:• Step1SelecttheclocksourceandMastermodeusingtheSASPI2~SASPI0bitsintheSPIAC0controlregister

• Step2SetuptheSACSENbitandsetuptheSAMLSbit tochooseif thedataisMSBorLSBshiftedfirst,thismustbesameastheSlavedevice.

• Step3SetuptheSPIAENbitintheSPIAC0controlregistertoenabletheSPIAinterface.

• Step4Forwriteoperations:writethedatatotheSPIADregister,whichwillactuallyplacethedataintotheTXRXbuffer.ThenusetheSCKAandSCSAlinestooutputthedata.Afterthisgotostep5.Forreadoperations:thedatatransferredinontheSDIAlinewillbestoredintheTXRXbufferuntilallthedatahasbeenreceivedatwhichpointitwillbelatchedintotheSPIADregister.

• Step5ChecktheSAWCOLbitifsethighthenacollisionerrorhasoccurredsoreturntostep4.Ifequaltozerothengotothefollowingstep.

• Step6ChecktheSATRFbitorwaitforaSPIAserialbusinterrupt.

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�9 ��st �� 01�


• Step7ReaddatafromtheSPIADregister.

• Step8ClearSATRF.

• Step9Gotostep4.

Slave Mode:• Step1SelecttheSPISlavemodeusingtheSASPI2~SASPI0bitsintheSPIAC0controlregister

• Step2SetuptheSACSENbitandsetuptheSAMLSbit tochooseif thedataisMSBorLSBshiftedfirst,thissettingmustbethesamewiththeMasterdevice.

• Step3SetuptheSPIAENbitintheSPIAC0controlregistertoenabletheSPIAinterface.

• Step4Forwriteoperations:writethedatatotheSPIADregister,whichwillactuallyplacethedataintotheTXRXbuffer.ThenwaitforthemasterclockSCKAandSCSAsignal.Afterthis,gotostep5.Forreadoperations:thedatatransferredinontheSDIAlinewillbestoredintheTXRXbufferuntilallthedatahasbeenreceivedatwhichpointitwillbelatchedintotheSPIADregister.

• Step5ChecktheSAWCOLbitifsethighthenacollisionerrorhasoccurredsoreturntostep4.Ifequaltozerothengotothefollowingstep.

• Step6ChecktheSATRFbitorwaitforaSPIAserialbusinterrupt.

• Step7ReaddatafromtheSPIADregister.

• Step8ClearSATRF.

• Step9Gotostep4.

Error DetectionTheSAWCOLbitintheSPIAC1registerisprovidedtoindicateerrorsduringdatatransfer.ThebitissetbytheSPIAserialInterfacebutmustbeclearedbytheapplicationprogram.ThisbitindicatesadatacollisionhasoccurredwhichhappensifawritetotheSPIADregistertakesplaceduringadatatransferoperationandwillpreventthewriteoperationfromcontinuing.

Rev. 1.40 1�� st �� 01� Rev. 1.40 1�9 ��st �� 01�


InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thesedevicescontainseveralexternalinterruptandinternalinterruptsfunctions.TheexternalinterruptsaregeneratedbytheactionoftheexternalINT0~INT3andPINTpins,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchastheTMs,Comparators,TimeBase,LVD,EEPROM,SIMandtheA/Dconverter.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.Thenumberofregistersdependsuponthedevicechosenbutfall intothreecategories.ThefirstistheINTC0~INTC3registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI4registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEGregistertosetuptheexternalinterrupttriggeredgetype.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.

Function Enable Bit Request Flag NotesGlobal EMI — —INTn Pin INTnE INTnF n=0~3Comparator CPnE CPnF n=0~1�/D Converter �DE �DF —Time Base TBnE TBnF n=0~1M�lti-f�nction MFnE MFnF n=0~4SIM SIME SIMF —LVD LVE LVF —EEPROM DEE DEF —PINT XPE XPF —SPI� SPI�E SPI�F —

TMTnPE TnPF n=0~5Tn�E Tn�F n=0~5TnBE TnBF n=1

Interrupt Register Bit Naming Conventions

Rev. 1.40 190 ��st �� 01� Rev. 1.40 191 ��st �� 01�


Interrupt Register Contents

NameBit

7 6 5 4 3 2 1 0INTEG INT3EG1 INT3EG0 INT�EG1 INT�EG0 INT1EG1 INT1EG0 INT0EG1 INT0EG0INTC0 — CP0F INT1F INT0F CP0E INT1E INT0E EMIINTC1 �DF MF1F MF0F CP1F �DE MF1E MF0E CP1EINTC� MF3F TB1F TB0F MF�F MF3E TB1E TB0E MF�EINTC3 — MF4F INT3F INT�F — MF4E INT3E INT�EMFI0 T��F T�PF Tn�F TnPF T��E T�PE T0�E T0PEMFI1 — T1BF T1�F T1PF — T1BE T1�E T1PEMFI� SIMF XPF T3�F T3PF SIME XPE T3�E T3PEMFI3 — SPI�F DEF LVF — SPI�E DEE LVEMFI4 T5�F T5PF T4�F T4PF T5�E T5PE T4�E T4PE

INTEG Register

Bit 7 6 5 4 3 2 1 0Name INT3EG1 INT3EG0 INT�EG1 INT�EG0 INT1EG1 INT1EG0 INT0EG1 INT0EG0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 INT3EG1,INT3EG0:interruptedgecontrolforINT3pin00:Disable01:Risingedge10:Fallingedge11:Risingandfallingedges



Bit1~0 INT0EG1,INT0EG0:interruptedgecontrolforINT0pin00:Disable01:Risingedge10:Fallingedge11:Risingandfallingedge

Rev. 1.40 190 ��st �� 01� Rev. 1.40 191 ��st �� 01�


INTC0 Register

Bit 7 6 5 4 3 2 1 0Name — CP0F INT1F INT0F CP0E INT1E INT0E EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6 CP0F:Comparator0interruptrequestflag

0:Norequest1:Interruptrequest

Bit5 INT1F:INT1interruptrequestflag0:Norequest1:Interruptrequest


Bit3 CP0E:Comparator0interruptcontrol0:Disable1:Enable

Bit2 INT1E:INT1interruptcontrol0:Disable1:Enable


Bit0 EMI:Globalinterruptcontrol0:Disable1:Enable

Rev. 1.40 19� ��st �� 01� Rev. 1.40 193 ��st �� 01�


INTC1 Register

Bit 7 6 5 4 3 2 1 0Name �DF MF1F MF0F CP1F �DE MF1E MF0E CP1ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 ADF:A/DConverterinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 MF1F:Multi-functioninterrupt1requestflag0:Norequest1:Interruptrequest


Bit4 CP1F:Comparator1interruptrequestflag0:Norequest1:Interruptrequest

Bit3 ADE:A/DConverterinterruptcontrol0:Disable1:Enable

Bit2 MF1E:Multi-functioninterrupt1control0:Disable1:Enable


Bit0 CP1E:Comparator1interruptcontrol0:Disable1:Enable

Rev. 1.40 19� ��st �� 01� Rev. 1.40 193 ��st �� 01�


INTC2 Register

Bit 7 6 5 4 3 2 1 0Name MF3F TB1F TB0F MF�F MF3E TB1E TB0E MF�ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0


Bit6 TB1F:TimeBase1interruptrequestflag0:Norequest1:Interruptrequest

Bit5 TB0F:TimeBase0interruptrequestflag0:Norequest1:Interruptrequest



Bit2 TB1E:TimeBase1interruptcontrol0:Disable1:Enable

Bit1 TB0E:TimeBase0interruptcontrol0:Disable1:Enable


Rev. 1.40 194 ��st �� 01� Rev. 1.40 195 ��st �� 01�


INTC3 Register

Bit 7 6 5 4 3 2 1 0Name — MF4F INT3F INT�F — MF4E INT3E INT�ER/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6 MF4F:Multi-functioninterrupt4requestflag




Bit3 Unimplemented,readas“0”Bit2 MF4E:Multi-functioninterrupt4control

0:Disable1:Enable



Rev. 1.40 194 ��st �� 01� Rev. 1.40 195 ��st �� 01�


MFI0 Register

Bit 7 6 5 4 3 2 1 0Name T��F T�PF T0�F T0PF T��E T�PE T0�E T0PER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 T2AF:TM2ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 T2PF:TM2ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest



Bit3 T2AE:TM2ComparatorAmatchinterruptcontrol0:Disable1:Enable

Bit2 T2PE:TM2ComparatorPmatchinterruptcontrol0:Disable1:Enable



Rev. 1.40 196 ��st �� 01� Rev. 1.40 19� ��st �� 01�


MFI1 Register

Bit 7 6 5 4 3 2 1 0Name — T1BF T1�F T1PF — T1BE T1�E T1PER/W — R/W R/W R/W — R/W R/W R/WPOR — 0 0 0 — 0 0 0

Bit7 Unimplemented,readas“0”Bit6 T1BF:TM1ComparatorBmatchinterruptrequestflag




Bit3 Unimplemented,readas“0”Bit2 T1BE:TM1ComparatorBmatchinterruptcontrol

0:Disable1:Enable



Rev. 1.40 196 ��st �� 01� Rev. 1.40 19� ��st �� 01�


MFI2 Register

Bit 7 6 5 4 3 2 1 0Name SIMF XPF T3�F T3PF SIME XPE T3�E T3PER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 SIMF:SIMinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 XPF:Externalperipheralinterruptrequestflag0:Norequest1:Interruptrequest



Bit3 SIME:SIMInterruptControl0:Disable1:Enable

Bit2 XPE:ExternalperipheralInterruptControl0:Disable1:Enable



Rev. 1.40 19� ��st �� 01� Rev. 1.40 199 ��st �� 01�


MFI3 Register

Bit 7 6 5 4 3 2 1 0Name — SPI�F DEF LVF — SPI�E DEE LVER/W — R/W R/W R/W — R/W R/W R/WPOR — 0 0 0 — 0 0 0

Bit7 Unimplemented,readas“0”Bit6 SPIAF:SPIAinterruptrequestflag


Bit5 DEF:DataEEPROMinterruptrequestflag0:Norequest1:Interruptrequest

Bit4 LVF:LVDinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 Unimplemented,readas“0”Bit2 SPIAE:SPIAInterruptControl

0:Disable1:Enable

Bit1 DEE:DataEEPROMInterruptControl0:Disable1:Enable

Bit0 LVE:LVDInterruptControl0:Disable1:Enable

Rev. 1.40 19� ��st �� 01� Rev. 1.40 199 ��st �� 01�


MFI4 Register

Bit 7 6 5 4 3 2 1 0Name T5�F T5PF T4�F T4PF T5�E T5PE T4�E T4PER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0









Rev. 1.40 �00 ��st �� 01� Rev. 1.40 �01 ��st �� 01�


Interrupt Operation

INT0 Pin

INT1 Pin

INT0F

INT1F

INT0E

INT1E

EMI 04H

EMI 0�H

M. F�nct. 0 MF0F MF0E

0CH

10H

14H

Time Base 0 TB0F TB0E

1�H

SPI� SPI�F SPI�E

1CH

Interr�pt Name

Req�est Fla�s

Enable Bits

Master Enable Vector

EMI a�to disabled in ISR

PriorityHi�h

Low

TM1 P T1PF T1PE

TM1 � T1�F T1�E M. F�nct. 1 MF1F MF1E

TM0 P T0PF T0PE

TM0 � T0�F T0�E

Interr�pts contained within M�lti-F�nction Interr�pts

xxE Enable Bits

xxF Req�est Fla�� a�to reset in ISR

LegendxxF Req�est Fla�� no a�to reset in ISR

EMI

EMI

M. F�nct. � MF�F MF�E

EEPROM DEF DEE

EMI

TM� P T�PF T�PE

TM� � T��F T��E

TM1 B T1BF T1BE

Time Base 1 TB1F TB1E

EMI

EMIComparator 0 CP0F CP0E

Comparator 1 CP1F CP1E

�/D �DF �DE

�0HEMI

�4H

��H

�CH

EMI

EMI

EMI

30HEMI

34H

3�H

EMI

EMI



INT� Pin

INT3 Pin

INT�F

INT3F

INT�E

INT3E

XPF XPE

TM3 P T3PF T3PE


SIM SIMF SIME

LVD LVF LVE

TM5 P T5PF T5PE


TM4 P T4PF T4PE


PINT Pin

Interrupt Structure

Rev. 1.40 �00 ��st �� 01� Rev. 1.40 �01 ��st �� 01�


External InterruptTheexternal interruptsarecontrolledbysignal transitionsonthepinsINT0~INT3.Anexternalinterruptrequestwill takeplacewhentheexternal interruptrequestflags,INT0F~INT3Fareset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternalinterruptpins.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INT0E~INT3E,mustfirstbeset.AdditionallythecorrectinterruptedgetypemustbeselectedusingtheINTEGregistertoenabletheexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinsarepin-sharedwithI/Opins, theycanonlybeconfiguredasexternal interruptpins if theirexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflags,INT0F~INT3F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinswillremainvalidevenifthepinisusedasanexternalinterruptinput.

TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.

Comparator InterruptThecomparator interruptsarecontrolledbythetwointernalcomparators.Acomparator interruptrequestwill takeplacewhen thecomparator interrupt request flags,CP0ForCP1F,areset,asituationthatwilloccurwhenthecomparatoroutputchangesstate.Toallowtheprogramtobranchto its respective interruptvectoraddress, theglobal interruptenablebit,EMI,andcomparatorinterruptenablebits,CP0EandCP1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandthecomparatorinputsgenerateacomparatoroutputtransition,asubroutinecalltothecomparatorinterruptvector,will takeplace.Whentheinterruptisserviced, theexternal interruptrequestflags,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

Multi-function InterruptWithin thesedevicesarefiveMulti-functioninterrupts.Unlike theother independent interrupts,these interruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheTMInterrupts,SIMInterrupt,ExternalPeripheralInterrupt,LVDinterruptandEEPROMInterrupt.

AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflags,MF0F~MF5F,areset.TheMulti-functioninterruptflagswillbesetwhenanyoftheirincludedfunctionsgeneratean interrupt request flag.Toallow theprogram tobranch to its respectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecalltooneoftheMulti-functioninterruptvectorswilltakeplace.Whentheinterruptisserviced,therelatedMulti-Functionrequestflag,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhen the interrupt is serviced, the request flags from theoriginal sourceof theMulti-functioninterrupts,namelytheTMInterrupts,EEPROMInterruptandLVDinterruptwillnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

Rev. 1.40 �0� ��st �� 01� Rev. 1.40 �03 ��st �� 01�


A/D Converter InterruptTheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwilltakeplacewhentheA/DConverterInterruptrequestflag,ADF,isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Time Base InterruptThefunctionoftheTimeBaseInterruptistoprovideregulartimesignalintheformofaninternalinterrupt. It iscontrolledby theoverflowsignal fromits internal timer.When thishappens itsinterruptrequestflag,TBnF,willbeset.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebit,TBnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecall to itsrespectivevector locationwill takeplace.Whentheinterrupt isserviced, theinterruptrequest flag,TBnF,willbeautomaticallyresetand theEMIbitwillbecleared todisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.Itsclocksource,fTB,originatesfromtheinternalclocksourcefSUB, fSYS/4,fSYSorfHandthenpassesthroughadivider,thedivisionratioofwhichisselectedbyprogrammingtheappropriatebitsintheTBC0andTBC1registerstoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcewhichinturncontrolstheTimeBaseinterruptperiodisselectedusingtheCLKS01andCLKS00bitsinthePSC0register.

fSYS/4

fTB

CLKS0[1:0 ]

fSUB

fSYS

fHPrescaler

TB0EN

TB0[�:0 ]fP/�� ~ fP/�15

TB1EN

Time Base 0 Interr�pt

TB1[�:0 ]

Time Base 1 Interr�pt

Time Base Interrupt

Rev. 1.40 �0� ��st �� 01� Rev. 1.40 �03 ��st �� 01�


PSC0 Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — CLKS01 CLKS00R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 CLKS01~CLKS00:TimeBaseclocksourceSelection

00:fSYS

01:fSYS/410:fTB11:fH

TBC0 Register

Bit 7 6 5 4 3 2 1 0Name TB0ON — — — — TB0� TB01 TB00R/W R/W — — — — R/W R/W R/WPOR 0 — — — — 0 0 0

Bit7 TB0ON:TimeBase0Enable/DisableControl0:Disable1:Enable

Bit6~3 Unimplemented,readas“0”Bit2~0 TB02~TB00:TimeBase0Time-outPeriod

000:28/fTB001:29/fTB010:210/fTB011:211/fTB100:212/fTB101:213/fTB110:214/fTB111:215/fTB

TBC1 Register

Bit 7 6 5 4 3 2 1 0Name TB1ON — — — — TB1� TB11 TB10R/W R/W — — — — R/W R/W R/WPOR 0 — — — — 0 0 0

Bit7 TB1ON:TimeBase1Enable/DisableControl0:Disable1:Enable

Bit6~3 Unimplemented,readas“0”Bit2~0 TB12~TB10:TimeBase1Time-outPeriod

000:28/fTB001:29/fTB010:210/fTB011:211/fTB100:212/fTB101:213/fTB110:214/fTB111:215/fTB

Rev. 1.40 �04 ��st �� 01� Rev. 1.40 �05 ��st �� 01�


Serial Interface Module InterruptsTheSerial InterfaceModuleInterrupt,alsoknownas theSIMinterrupt, iscontainedwithin theMulti-functionInterrupt.ASIMInterruptrequestwill takeplacewhentheSIMInterruptrequestflag,SIMF,isset,whichoccurswhenabyteofdatahasbeenreceivedortransmittedbytheSIMinterface.Toallowtheprogramtobranch to its respective interruptvectoraddress, theglobalinterruptenablebit,EMI,andtheSerialInterfaceInterruptenablebit,SIME,andMuti-functioninterruptenablebits,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandabyteofdatahasbeentransmittedorreceivedbytheSIMinterface,asubroutinecall totherespectiveMulti-functionInterruptvector,willtakeplace.WhentheSerialInterfaceInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheSIMFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

SPIA Interface InterruptTheSPIAInterfaceInterrupt iscontainedwithin theMulti-functionInterrupt.ASPIAInterruptrequestwill takeplacewhentheSPIAInterruptrequestflag,SPIAF,isset,whichoccurswhenabyteofdatahasbeenreceivedortransmittedbytheSPIAinterface.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtheSPIAInterfaceInterruptenablebit,SPIAE,andMuti-functioninterruptenablebits,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandabyteofdatahasbeentransmittedorreceivedbytheSPIAinterface,asubroutinecall totherespectiveMulti-functionInterruptvector,will takeplace.WhentheSPIAInterfaceInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheSPIAFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

External Peripheral InterruptTheExternalPeripheralInterruptoperatesinasimilarwaytotheexternalinterruptandiscontainedwithintheMulti-functionInterrupt.APeripheralInterruptrequestwilltakeplacewhentheExternalPeripheralInterruptrequestflag,XPF,isset,whichoccurswhenanegativeedgetransitionappearson thePINTpin.Toallowtheprogramtobranch to its respective interruptvectoraddress, theglobal interruptenablebit,EMI,externalperipheral interruptenablebit,XPE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanegativetransitionappearsontheExternalPeripheralInterruptpin,asubroutinecall totherespectiveMulti-functionInterrupt,will takeplace.WhentheExternalPeripheralInterruptisserviced, theEMIbitwillbeautomaticallyclearedtodisableother interrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.

AstheXPFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.Theexternalperipheralinterruptpinispin-sharedwithseveralotherpinswithdifferentfunctions.ItmustthereforebeproperlyconfiguredtoenableittooperateasanExternalPeripheralInterruptpin.

Rev. 1.40 �04 ��st �� 01� Rev. 1.40 �05 ��st �� 01�


EEPROM InterruptTheEEPROMInterrupt, iscontainedwithintheMulti-functionInterrupt.AnEEPROMInterruptrequestwill takeplacewhentheEEPROMInterruptrequestflag,DEF,isset,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobalinterruptenablebit,EMI,EEPROMInterruptenablebit,DEE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecalltotherespectiveMulti-functionInterruptvector,willtakeplace.WhentheEEPROMInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheDEFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

LVD InterruptTheLowVoltageDetector Interrupt iscontainedwithin theMulti-function Interrupt.AnLVDInterruptrequestwill takeplacewhentheLVDInterruptrequest flag,LVF, isset,whichoccurswhentheLowVoltageDetectorfunctiondetectsalowpowersupplyvoltage.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,LowVoltageInterruptenablebit,LVE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotheMulti-functionInterruptvector,willtakeplace.WhentheLowVoltageInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheLVFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

TM InterruptsTheCompactTMhas two interrupts,while theEnhancedTypeTMhas three interrupts.AlloftheTMinterruptsarecontainedwithintheMulti-functionInterrupts.For theCompactTypeTMtherearetwointerruptrequestflagsTnPFandTnAFandtwoenablebitsTnPEandTnAE.FortheEnhancedTypeTMtherearethreeinterruptrequestflagsTnPF,TnAFandTnBFandthreeenablebitsTnPE,TnAEandTnBE.ATMinterruptrequestwill takeplacewhenanyoftheTMrequestflagsareset,asituationwhichoccurswhenaTMcomparatorP,AorBmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,respectiveTMInterruptenablebit,andrelevantMulti-functionInterruptenablebit,MFnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecalltotherelevantMulti-functionInterruptvectorlocations,willtakeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.

Rev. 1.40 �06 ��st �� 01� Rev. 1.40 �0� ��st �� 01�


Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthesedevicesare in theSLEEPor IDLEModeand its systemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpins,alowpowersupplyvoltageorcomparatorinputchangemaycause theirrespectiveinterruptflag tobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptservice routine isexecuted,asonly theMulti-function interrupt request flags,MFnF,willbeautomaticallycleared, the individual request flag for the functionneeds tobeclearedby theapplicationprogram.

It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

EveryinterrupthasthecapabilityofwakingupthemicrocontrollerwhenitisintheSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

Rev. 1.40 �06 ��st �� 01� Rev. 1.40 �0� ��st �� 01�


Low Voltage Detector – LVDEachdevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenabledthedevicetomonitorthepowersupplyvoltage,VDD,andprovideawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.

LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebits inthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetermined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbit isusedtocontrol theoverallon/offfunctionof thelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.

LVDC Register

Bit 7 6 5 4 3 2 1 0Name — — LVDO LVDEN — VLVD� VLVD1 VLVD0R/W — — R R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas“0”Bit5 LVDO:LVDOutputFlag

0:NoLowVoltageDetected1:LowVoltageDetected

Bit4 LVDEN:LowVoltageDetectorEnable/Disable0:Disable1:Enable

Bit3 Unimplemented,readas“0”Bit2~0 VLVD2~VLVD0:SelectLVDVoltage

000:2.0V001:2.2V010:2.4V011:2.7V100:3.0V101:3.3V110:3.6V111:4.0V

Rev. 1.40 �0� ��st �� 01� Rev. 1.40 �09 ��st �� 01�


LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasarangeofbetween2.0Vand4.0V.Whenthepowersupplyvoltage,VDD,fallsbelowthispre-determinedvalue,theLVDObitwillbesethighindicatinga lowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbyareferencevoltagewhichwillbeautomaticallyenabled.WhenthedeviceispowereddownthelowvoltagedetectorwillremainactiveiftheLVDENbitishigh.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,atthevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.

� � �

� � � �

� � � � �

� � � ��

LVD Operation

TheLowVoltageDetector alsohas its own interruptwhich is containedwithinoneof theMulti-functioninterrupts,providinganalternativemeansof lowvoltagedetection, inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.WhenthedeviceispowereddowntheLowVoltageDetectorwillremainactiveif theLVDENbit ishigh.Inthiscase, theLVFinterruptrequestflagwillbeset,causinganinterrupttobegeneratedifVDDfallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheSLEEPorIDLEMode,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVFflagshouldbefirstsethighbeforethedeviceenterstheSLEEPorIDLEMode.

Rev. 1.40 �0� ��st �� 01� Rev. 1.40 �09 ��st �� 01�


SCOM Function for LCDThedeviceshavethecapabilityofdrivingexternalLCDpanels.ThecommonpinsforLCDdriving,SCOM0~SCOM3,arepinsharedwiththePC0~PC1,PC6~PC7pins.TheLCDsignals(COMandSEG)aregeneratedusingtheapplicationprogram.

LCD OperationAnexternalLCDpanelcanbedrivenusingthisdevicebyconfiguringthePC0~PC1,PC6~PC7pinsascommonpinsandusingotheroutputportslinesassegmentpins.TheLCDdriverfunctioniscontrolledusingtheSCOMCregisterwhichinadditiontocontrollingtheoverallon/offfunctionalsocontrols thebiasvoltagesetupfunction.Thisenables theLCDCOMdriver togenerate thenecessaryVDD/2voltagelevelsforLCD1/2biasoperation.

TheSCOMENbit in theSCOMCregister is theoverallmastercontrol for theLCDdriver.TheLCDSCOMnpinisselectedtobeusedforLCDdrivingbythecorrespondingpin-sharedfunctionselectionbits.NotethatthePortControlregisterdoesnotneedtofirstsetupthepinsasoutputstoenabletheLCDdriveroperation.

� � �

� � � � � ��

� � � � � ��

� � � � �

� � � � � � � � � � � � � � � � �

LCD COM Bias

LCD Bias ControlTheLCDCOMdriverenablesarangeofselectionstobeprovidedtosuit therequirementoftheLCDpanelwhichisbeingused.ThebiasresistorchoiceisimplementedusingtheISEL1andISEL0bitsintheSCOMCregister.

SCOMC Register

Bit 7 6 5 4 3 2 1 0Name D� ISEL1 ISEL0 SCOMEN — — — —R/W R/W R/W R/W R/W — — — —POR 0 0 0 0 — — — —

Bit7 ReservedBit0:Correctlevel-bitmustberesettozeroforcorrectoperation1:Unpredictableoperation-bitmustnotbesethigh

Bit6~5 ISEL1, ISEL0:SelectSCOMtypicalbiascurrent(VDD=5V)00:25μA01:50μA10:100μA11:200μA

Bit4 SCOMEN:SCOMmoduleControl0:Disable1:Enable

Bit3~0 Unimplemented,readas“0”

Rev. 1.40 �10 ��st �� 01� Rev. 1.40 �11 ��st �� 01�


Configuration OptionsConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedevicesduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopmenttools.Astheseoptionsareprogrammedintothedevicesusingthehardwareprogrammingtools,once theyareselectedtheycannotbechangedlaterusingtheapplicationprogram.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.

No. Options

1 Hi�h Speed System Oscillator Selection – fH

HXT� ERC or HIRC

� Low Speed System Oscillator Selection – fSUB

LXT or LIRC

3 I/O or Reset pin selectionReset pin or I/O pin

Application Circuits

VDD

PB0/RES

VSS

PB1/OSC1

PB�/OSC�

PB3/XT1

PB4/XT�

OSCCirc�it

OSCCirc�it

100KΩ

0.1�F

0.1�F PC0~PC�

PD0~PD�

PE0~PE�

PF0~PF�

PG0~PG�

PH0~PH5

VDD

PB0~PB�

P�0~P��

Rev. 1.40 �10 ��st �� 01� Rev. 1.40 �11 ��st �� 01�


Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe“CLRPCL”or“MOVPCL,A”.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofseveralkindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsistoreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandless than0forsubtraction.Theincrementanddecrement instructionssuchasINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

Rev. 1.40 �1� ��st �� 01� Rev. 1.40 �13 ��st �� 01�


Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction“RET”inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe“SET[m].i”or“CLR[m].i”instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe“HALT”instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

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Instruction Set SummaryTheinstructionsrelated to thedatamemoryaccess in thefollowingtablecanbeusedwhenthedesireddatamemoryislocatedinDataMemorysection0.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmetic�DD ��[m] �dd Data Memory to �CC 1 Z� C� �C� OV� SC�DDM ��[m] �dd �CC to Data Memory 1Note Z� C� �C� OV� SC�DD ��x �dd immediate data to �CC 1 Z� C� �C� OV� SC�DC ��[m] �dd Data Memory to �CC with Carry 1 Z� C� �C� OV� SC�DCM ��[m] �dd �CC to Data memory with Carry 1Note Z� C� �C� OV� SCSUB ��x S�btract immediate data from the �CC 1 Z� C� �C� OV� SC� CZSUB ��[m] S�btract Data Memory from �CC 1 Z� C� �C� OV� SC� CZSUBM ��[m] S�btract Data Memory from �CC with res�lt in Data Memory 1Note Z� C� �C� OV� SC� CZSBC ��x S�btract immediate data from �CC with Carry 1 Z� C� �C� OV� SC� CZSBCM ��[m] S�btract Data Memory from �CC with Carry� res�lt in Data Memory 1Note Z� C� �C� OV� SC� CZD�� [m] Decimal adj�st �CC for �ddition with res�lt in Data Memory 1Note CLogic Operation�ND ��[m] Lo�ical �ND Data Memory to �CC 1 ZOR ��[m] Lo�ical OR Data Memory to �CC 1 ZXOR ��[m] Lo�ical XOR Data Memory to �CC 1 Z�NDM ��[m] Lo�ical �ND �CC to Data Memory 1Note ZORM ��[m] Lo�ical OR �CC to Data Memory 1Note ZXORM ��[m] Lo�ical XOR �CC to Data Memory 1Note Z�ND ��x Lo�ical �ND immediate Data to �CC 1 ZOR ��x Lo�ical OR immediate Data to �CC 1 ZXOR ��x Lo�ical XOR immediate Data to �CC 1 ZCPL [m] Complement Data Memory 1Note ZCPL� [m] Complement Data Memory with res�lt in �CC 1 ZIncrement & DecrementINC� [m] Increment Data Memory with res�lt in �CC 1 ZINC [m] Increment Data Memory 1Note ZDEC� [m] Decrement Data Memory with res�lt in �CC 1 ZDEC [m] Decrement Data Memory 1Note ZRotateRR� [m] Rotate Data Memory ri�ht with res�lt in �CC 1 NoneRR [m] Rotate Data Memory ri�ht 1Note NoneRRC� [m] Rotate Data Memory ri�ht thro��h Carry with res�lt in �CC 1 CRRC [m] Rotate Data Memory ri�ht thro��h Carry 1Note CRL� [m] Rotate Data Memory left with res�lt in �CC 1 NoneRL [m] Rotate Data Memory left 1Note NoneRLC� [m] Rotate Data Memory left thro��h Carry with res�lt in �CC 1 CRLC [m] Rotate Data Memory left thro��h Carry 1Note C

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Mnemonic Description Cycles Flag AffectedData MoveMOV ��[m] Move Data Memory to �CC 1 NoneMOV [m]�� Move �CC to Data Memory 1Note NoneMOV ��x Move immediate data to �CC 1 NoneBit OperationCLR [m].i Clear bit of Data Memory 1Note NoneSET [m].i Set bit of Data Memory 1Note NoneBranchJMP addr J�mp �nconditionally � NoneSZ [m] Skip if Data Memory is zero 1Note NoneSZ� [m] Skip if Data Memory is zero with data movement to �CC 1Note NoneSZ [m].i Skip if bit i of Data Memory is zero 1Note NoneSNZ [m] Skip if Data Memory is not zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero 1Note NoneSDZ [m] Skip if decrement Data Memory is zero 1Note NoneSIZ� [m] Skip if increment Data Memory is zero with res�lt in �CC 1Note NoneSDZ� [m] Skip if decrement Data Memory is zero with res�lt in �CC 1Note NoneC�LL addr S�bro�tine call � NoneRET Ret�rn from s�bro�tine � NoneRET ��x Ret�rn from s�bro�tine and load immediate data to �CC � NoneRETI Ret�rn from interr�pt � NoneTable ReadT�BRD [m] Read table to TBLH and Data Memory �Note NoneT�BRDL [m] Read table (last pa�e) to TBLH and Data Memory �Note NoneIT�BRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory �Note None

IT�BRDL [m] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Memory �Note None

MiscellaneousNOP No operation 1 NoneCLR [m] Clear Data Memory 1Note NoneSET [m] Set Data Memory 1Note NoneCLR WDT Clear Watchdo� Timer 1 TO� PDFSW�P [m] Swap nibbles of Data Memory 1Note NoneSW�P� [m] Swap nibbles of Data Memory with res�lt in �CC 1 NoneH�LT Enter power down mode 1 TO� PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthenuptothreecyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.

3.Forthe“CLRWDT”instructiontheTOandPDFflagsmaybeaffectedbytheexecutionstatus.TheTOandPDFflagsareclearedafterthe“CLRWDT”instructionsisexecuted.OtherwisetheTOandPDFflagsremainunchanged.

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Extended Instruction SetTheextendedinstructionsareusedtosupport thefullrangeaddressaccessfor thedatamemory.When theaccesseddatamemory is located inanydatamemorysectionsexceptsection0, theextendedinstructioncanbeusedtoaccessthedatamemoryinsteadofusingtheindirectaddressingaccesstoimprovetheCPUfirmwareperformance.

Mnemonic Description Cycles Flag AffectedArithmeticL�DD ��[m] �dd Data Memory to �CC � Z� C� �C� OV� SCL�DDM ��[m] �dd �CC to Data Memory �Note Z� C� �C� OV� SCL�DC ��[m] �dd Data Memory to �CC with Carry � Z� C� �C� OV� SCL�DCM ��[m] �dd �CC to Data memory with Carry �Note Z� C� �C� OV� SCLSUB ��[m] S�btract Data Memory from �CC � Z� C� �C� OV� SC� CZLSUBM ��[m] S�btract Data Memory from �CC with res�lt in Data Memory �Note Z� C� �C� OV� SC� CZLSBC ��[m] S�btract Data Memory from �CC with Carry � Z� C� �C� OV� SC� CZLSBCM ��[m] S�btract Data Memory from �CC with Carry� res�lt in Data Memory �Note Z� C� �C� OV� SC� CZLD�� [m] Decimal adj�st �CC for �ddition with res�lt in Data Memory �Note CLogic OperationL�ND ��[m] Lo�ical �ND Data Memory to �CC � ZLOR ��[m] Lo�ical OR Data Memory to �CC � ZLXOR ��[m] Lo�ical XOR Data Memory to �CC � ZL�NDM ��[m] Lo�ical �ND �CC to Data Memory �Note ZLORM ��[m] Lo�ical OR �CC to Data Memory �Note ZLXORM ��[m] Lo�ical XOR �CC to Data Memory �Note ZLCPL [m] Complement Data Memory �Note ZLCPL� [m] Complement Data Memory with res�lt in �CC � ZIncrement & DecrementLINC� [m] Increment Data Memory with res�lt in �CC � ZLINC [m] Increment Data Memory �Note ZLDEC� [m] Decrement Data Memory with res�lt in �CC � ZLDEC [m] Decrement Data Memory �Note ZRotateLRR� [m] Rotate Data Memory ri�ht with res�lt in �CC � NoneLRR [m] Rotate Data Memory ri�ht �Note NoneLRRC� [m] Rotate Data Memory ri�ht thro��h Carry with res�lt in �CC � CLRRC [m] Rotate Data Memory ri�ht thro��h Carry �Note CLRL� [m] Rotate Data Memory left with res�lt in �CC � NoneLRL [m] Rotate Data Memory left �Note NoneLRLC� [m] Rotate Data Memory left thro��h Carry with res�lt in �CC � CLRLC [m] Rotate Data Memory left thro��h Carry �Note CData MoveLMOV ��[m] Move Data Memory to �CC � NoneLMOV [m]�� Move �CC to Data Memory �Note NoneBit OperationLCLR [m].i Clear bit of Data Memory �Note NoneLSET [m].i Set bit of Data Memory �Note None

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Mnemonic Description Cycles Flag AffectedBranchLSZ [m] Skip if Data Memory is zero �Note NoneLSZ� [m] Skip if Data Memory is zero with data movement to �CC �Note NoneLSNZ [m] Skip if Data Memory is not zero �Note NoneLSZ [m].i Skip if bit i of Data Memory is zero �Note NoneLSNZ [m].i Skip if bit i of Data Memory is not zero �Note NoneLSIZ [m] Skip if increment Data Memory is zero �Note NoneLSDZ [m] Skip if decrement Data Memory is zero �Note NoneLSIZ� [m] Skip if increment Data Memory is zero with res�lt in �CC �Note NoneLSDZ� [m] Skip if decrement Data Memory is zero with res�lt in �CC �Note NoneTable ReadLT�BRD [m] Read table to TBLH and Data Memory 3Note NoneLT�BRDL [m] Read table (last pa�e) to TBLH and Data Memory 3Note NoneLIT�BRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory 3Note None

LIT�BRDL [m] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Memory 3Note None

MiscellaneousLCLR [m] Clear Data Memory �Note NoneLSET [m] Set Data Memory �Note NoneLSW�P [m] Swap nibbles of Data Memory �Note NoneLSW�P� [m] Swap nibbles of Data Memory with res�lt in �CC � None

Note:1.Fortheseextendedskipinstructions,iftheresultofthecomparisoninvolvesaskipthenuptofourcyclesarerequired,ifnoskiptakesplacetwocyclesisrequired.

2.AnyextendedinstructionwhichchangesthecontentsofthePCLregisterwillalsorequirethreecyclesforexecution.

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Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C,SC

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

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CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

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CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA[m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

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JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

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RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

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RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

SBC A, x SubtractimmediatedatafromACCwithCarryDescription Theimmediatedataandthecomplementofthecarryflagaresubtractedfromthe Accumulator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionis negative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflag willbesetto1.Operation ACC←ACC-[m]-CAffectedflag(s) OV,Z,AC,C,SC,CZ

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

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SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

Rev. 1.40 ��4 ��st �� 01� Rev. 1.40 ��5 ��st �� 01�


SNZ [m] SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C,SC,CZ

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

Rev. 1.40 ��4 ��st �� 01� Rev. 1.40 ��5 ��st �� 01�


SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

TABRD [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

ITABRD [m] IncrementtablepointerlowbytefirstandreadtabletoTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthentheprogramcodeaddressedbythe tablepointer(TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbyte movedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

ITABRDL [m] Incrementtablepointerlowbytefirstandreadtable(lastpage)toTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthenthelowbyteoftheprogramcode (lastpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryand thehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

Rev. 1.40 ��6 ��st �� 01� Rev. 1.40 �� st �� 01�


XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

Rev. 1.40 ��6 ��st �� 01� Rev. 1.40 �� st �� 01�


Extended Instruction DefinitionTheextendedinstructionsareusedtodirectlyaccessthedatastoredinanydatamemorysections.

LADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

LADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

LADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

LADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

LAND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

LANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

LCLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

LCLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

Rev. 1.40 �� st �� 01� Rev. 1.40 ��9 ��st �� 01�


LCPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

LCPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

LDAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

LDEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

LDECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

LINC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

LINCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

Rev. 1.40 �� st �� 01� Rev. 1.40 ��9 ��st �� 01�


LMOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

LMOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

LOR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

LORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

LRL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

LRLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

LRLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

LRLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

Rev. 1.40 �30 ��st �� 01� Rev. 1.40 �31 ��st �� 01�


LRR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

LRRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

LRRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

LRRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

LSBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

LSBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

Rev. 1.40 �30 ��st �� 01� Rev. 1.40 �31 ��st �� 01�


LSDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

LSDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

LSET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

LSET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

LSIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

LSIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

LSNZ [m].i SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

Rev. 1.40 �3� ��st �� 01� Rev. 1.40 �33 ��st �� 01�


LSNZ [m] SkipifDataMemoryisnot0Description IfthecontentofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.As thisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisa twocycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]≠0Affectedflag(s) None

LSUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

LSUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

LSWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

LSWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

LSZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

LSZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

Rev. 1.40 �3� ��st �� 01� Rev. 1.40 �33 ��st �� 01�


LSZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

LTABRD [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

LTABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

LITABRD [m] IncrementtablepointerlowbytefirstandreadtabletoTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthentheprogramcodeaddressedbythe tablepointer(TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbyte movedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)

Affectedflag(s) None

LITABRDL [m] Incrementtablepointerlowbytefirstandreadtable(lastpage)toTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthenthelowbyteoftheprogramcode (lastpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryand thehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

LXOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

LXORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

Rev. 1.40 �34 ��st �� 01� Rev. 1.40 �35 ��st �� 01�


Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

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Rev. 1.40 �34 ��st �� 01� Rev. 1.40 �35 ��st �� 01�


48-pin LQFP (7mm×7mm) Outline Dimensions

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SymbolDimensions in mm

Min. Nom. Max.� — 9.00 BSC —B — �.00 BSC —C — 9.00 BSC —D — �.00 BSC —E — 0.50 BSC —F 0.1� 0.�� 0.��G 1.35 1.40 1.45H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.�5 K 0.09 — 0.�0 α 0° ― �°

Rev. 1.40 �36 ��st �� 01� Rev. 1.40 �3� ��st �� 01�


64-pin LQFP (7mm×7mm) Outline Dimensions

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� — 0.354 BSC —

B — 0.��6 BSC —

C — 0.354 BSC —

D — 0.��6 BSC —

E — 0.016 BSC —

F 0.005 0.00� 0.009

G 0.053 0.055 0.05�

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I 0.00� — 0.006

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SymbolDimensions in mm

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B — �.0 BSC —

C — 9.0 BSC —

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F 0.13 0.1� 0.�3

G 1.35 1.40 1.45

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I 0.05 — 0.15

J 0.45 0.60 0.�5

K 0.09 — 0.�0

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Rev. 1.40 �36 ��st �� 01� Rev. 1.40 �3� ��st �� 01�


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