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Activities on tracker and calorimetry ofKorean physicists
- Silicon Tracker- Silicon-Tungsten Calorimeter- Tile-Tungsten Calorimeter
Youngdo OhKyungpook National University
The 2nd KILC Workshop, Pohang2004/12/28
• stand-alone tracking capability
▣ Intermediate Tracker Configuration
• 5 layers at r = 9 to 37 cm• angular coverage |cosΘ|<0.9• spatial resolution σ = 10 μm• thickness of a layer: 0.6% Xo
Huge detector concept:TPC: Rmin = 40 cm
Do not expect much changes in IT
Intermediate Tracker Designfor GLC - Double-sided silicon microstrip detectors i. excellent spatial resolution ii. well-established technology
Layout of the IT surrounding the VTX.
- The distance between the last layer of VTX and the first layer of Trackeris about 39cm in Large detector design.
i. 5 layers of coaxial cylinders at 9, 16, 23, 30 and 37cmii. covers | cosΘ |<0.90 coinciding with the region covered by VTX
Intermediate Tracker R&D Activities in Korea √ linking and reconstruction efficiency (Fast Simulation) √ track momentum resolution (Full Simulation) √ DSSD simulation/design/fabrication Electronics(RC chip, VA1TA, FADC), DAQ √ S/N ratio measurement and beam test
- Kyungpook National University - Korea University - Seoul National University - Chunnam National University - Sungkyunkwan University
Sensor designProcess chart
KNU / SNU
Simulation(process and device)
KNU/SKKU
DAQ/Electronics/Test
KNU/KU/CNU
Sensor
512ch 100um pitch sensor Without hour glass
512ch 100um pitch sensorWith hour glass
1cm PIN Diode
For SDD R&D
PIN Diode array
16ch 100um pitch sensor
16ch 100um pitch SSD
32ch 100um pitch sensor
64ch 100um pitch sensor
▣ MASK Design : P SideMASK Design : P Side
▣ Silicon sensor R&D Silicon sensor R&D <- Details by B.G.Cheon<- Details by B.G.Cheon
Metal 1 and metal 2 contact (VIA) Metal 1 and metal 2 contact (VIA)
n+ ohmic n+ ohmic sideside
p+ junction p+ junction sideside
11stst metal metal
22ndnd metal readout line metal readout line
• double sided silicon strip• tree metal process- implant strips in ohmic side are orthogonal to those in junction side-readout strips in junction side have the same direction as that of ohmic side
Front Side: - brown: implanted n+ - blue: p-stop - sky blue: SiO2 - gray: Al for readout
Back Side: - blue: implanted p+ - first gray: 1st metal - sky blue: SiO2 - vertical gray: VIA - second gray: 2nd metal
▣ Silicon Sensor
n+ implantedp-stop in atoll
via in hourglassreadout pad in staggering
guard ring
p+ implanted readout strip
N side P side
▣ Measurements
0 20 40 60 80 100 120
1E-8
1E-7
1E-6
Leak
age
curr
ent (
A)
Reverse bias voltage(V)
LOT4_1_T1 LOT4_4_T1 LOT4_4_T3
These aredisappearedafter insulatingwafer edges
▣ Measurements of the sensor
Silicon-Tungsten Calorimetry
•Advantage well known, well proven technology, proven high accuracy•High granularity, but expensive to date•Built-in ShowerMax & Presampler•Modest Tracking capability for both charged/neutral particles
•Sampling EM and even Hadron calorimeter
•Cost–At moment 10 times more expensive that other types, but will be comparable in next 5 years–Cost depends on how you build it
•Many grounds do R&D
Why Silicon for Calorimeter?
•DC coupled•4*4 array matrix in 4 inch wafer•Pixel size : 1.5 * 1.4 cm^2•3 guard rings
N-type silicon 5 ㏀
SiO2
p+
Al
Guard Ring Pixels(Signal)
650 ㎛
Korean Silicon Sensor (1st Prototype, Oct.2002)
•Fabricated a sensor on 5’ wafer using the method of “stepper”
•Size : 6.52*5.82 cm2 (including 3 guard rings )
•array : 4*4 matrix
•Pixel size: 1.55 * 1.37 cm2
•Full depletion voltage : 90V
•Leakage current level : about 3 nA per pixel at full depletion voltage
3 Guard Rings
60um
20um
gap between sensors
Clean wafer
Oxidation
Cover with photoresist
Expose through mask
Develop
Etch, Stip
N+Diffusion
P+ ImplantationAnneal
Metallization
Fabrication process
CALICE : 6*6 pixels, each 1cm*1cm (4” wafer) 525um or 380um thick
Fab at SENS Technology (www.senstechnology.co.kr)
Korean Silicon Sensor (Mass Production in 2003-4)
Capacitance Measurement
CV
0.00E+00
2.00E+17
4.00E+17
6.00E+17
8.00E+17
1.00E+18
1.20E+18
10 20 30 40 50 60 70 80 90 100
110
120
130
140
150
160
Reverse bias voltage (V)
Cap
acita
nce(
F)
ED3_10_all
ED3_11_all
ED3_12_all
ED3_13_all
ED3_14_all
ED3_17_all
ED3_19_all
ED3_2_all
ED3_20_all
Full depletion voltage : 90V
Dark box
Pb Pb
Photodiode sensor
Beta (90Sr) source
Gate GeneratorShaping AMP
Discriminator Trigger Photodiode
PreAmp
PreAmp for sensor
S/N ~ 120
S/N Ratio Measurement with Sr-90 source(use of single channel very low noise preamp)
Digital Electronics : ADC, Contorl, Power Board
FPGA ACP Board
Power DC Voltag
e
High Voltage
ADC
ADC: MAX 1133•Sampling Speed : 200ksps
(200ksps X 16bit = 0.4Mbyte/s)•Resolution : 16bit (65536 Level)
•size : 65.5 mm X 57.5 mm ( ~ sensor size)• thickness : 3.5 mm (= 1 X0) •purity : close to 99% (Rm = 9mm)
Tungsten
tungsten
Beam Direction
Layers of Si sensorsand Tungstens
Frontend readout boards
Digital readout boardsand PC interface
CERN Beam test ( 2004/8~9)
Data Summary (50GB)Beam Beam Energy (GeV) Etc
Muon 150
4x4x20
TD Check
Electron 50 TD Check
Pion 150 Sensor scan
Pion 150
4x4x20Tungsten Muon 150
Electron 150,100, 80,50, 30 ,20 ,10
Pion 150
4x8x10Tungsten Muon 150
Electron 150, 100, 50, 20
files
23
33
35
12
42
399/37~89
3
18
162/36~48
Detector Response to Electron Beam(sum of all channel)
Total ADC of an event / 640
150 GeV Electron
100 GeV Electron
80 GeV Electron
50 GeV Electron
30 GeV Electron
20 GeV Electron
10 GeV Electron
First look of data
Energy Resolution vs Energy
Electron Energy in GeV
dE /
E (%
)
Very preliminaryFirst look of data
Analysis is underway
Tile-Tungsten Calorimeter
Tile Tungsten Calorimeter R&D Prototype Layout One Layer : Wolfram 20cm X 20cm X 0.3cm Scintillator 1cm X 20cm X 0.2cm X 20
Total: 30 Layers
Wolfram
Scintillator
Current Status
• Survey almost finished for the all the components
• aimed all the components supplied in Korea
• Largely five components
Tungsten, Scintillator, SiPM, Simulation package, readout electronics
• R & D has already been started for some parts • expect very active R & D for the next two years
• 3 professors from Kobe, Shinshu and Niigata universities visited KNU on Dec 7 – 9 to discuss the cowork about TiCAL - development of SiPM - Readout - Scintillator - Physics simulation using current simulation tools, ( Mokka, Jupiter ..)
Tungsten• TaeguTec( 전 대한중석회사 ) 에서의
텅스텐 판 제작 가능성 타진
• 판 구조의 가능성 : Alloy, Heavy metal or other ???– W:Ni:Cu=95:3.5:1.5 Alloy– WC + Cr heavy metal– W:Pb = 7:3 ??? : new possibility
• 현재 100 mm by 100 mm 판 제작 가능 .
• 성분 구성에 대한 모의시늉 등 연구 필요 – W 와 Pb 구성이면 매우 만들기 쉬움 –
모의시늉 필요 – 회사측과 연구 / 개발 협의
SiPM
• 한국 / 러시아 / 일본 공동연구 수행 .
• Quantum Efficiency 향상 • Noise level 의 줄임 • 국내에서의 제작
Scintillator
• 1 cm 정도 폭의 strip 형태의 scintillator 는 필연적임 .
• 압출 기술에 의한 scintillator 제작
• Fermilab 팀과 연구 /개발하기로 합의– Light yield 를 높이기 위한
성분 시험– Groove 디자인 등등
• 모든 scintillator 의 제작 한국에서 가능
Simulation• Geant4 based Simulation packages are considered. : Mokka, Jupiter • Mokka : installed - running successfully - geometry database installed at KNU - We are ready to open account to anyone interested in running physics.• Jupiter : not yet - Japanese site doesn’t distribute official version yet - We asked cooperation when Japanese professors visited KNU - And we are also asked to cowork about physics simulations.• As first stage, we are interested in physics simulation of SUSY using sus
ygen3.0 and SUSY parameter scan.
Summary
• Silicon tracker and silicon sensors are fabricated at Korea.
• Sensor R&D is underway.
• First Prototype of silicon calorimeter was tested at
CERN.
• Started design optimization and R&D work of TiCAL proto type
R&D of Scintillator, W, SiPM
R&D of Readout Electronics
• Ready for physics simulation
need informations and discusstions with
theory & physics working group
• Target : Prototype beam test at Fermilab (summer, 2006)