Active Devices for Communication Integrated Circuits

Berkeley

Active Devices for Communication IntegratedCircuits

Prof. Ali M. Niknejad

U.C. BerkeleyCopyright c© 2014 by Ali M. Niknejad

Niknejad Advanced IC’s for Comm

Overview of Key Device Parameters


Generic Three Terminal Device


Large Signal Equations


Generic Device Behavior

slope is output resistance of deviceresistor (triode) region (very small output voltage)non-linear resistor region (small output voltage)“constant” current region (large output voltage, current nearlyindependent of output)


Large Signal Models

+Vi

−

I = f(Vi)

Resistors and capacitors are non-linear

Rπ and Ro depend on bias pointRg (intrinsic) depends on channel inversion levelRb can change due to current spreading effectsCgs varies from accumulation to depletion to inversionJunction capacitors vary with bias


Small Signal Models

Cπrπ

Cµ

+vπ

−gmvπ

rx

rz

ry

ro

In small signal regime, R and C linear about a bias point:

ForBJT:rx = rb

For aFETinput:

Cgs

Rg = Rnqs +1

dRpoly

d = 3 ↔ 12

Rnqs ∼ 1

5gm


Various Figures of Merit

Intrinsic

Voltage

Gain (a0)

Power Gain

Unilateral Gain

Noise

Noise figure (NF and Noise Measure M)Flicker noise corner frequency

Unity Gain Frequency

fT

Maximum Osc Freq fmax

Gain (normalized to current): gm/I

Gain Bandwidth


Other Important Metrics

Complementary devices

Device with same order of magnitude of fT / fmax

Lateral pnp a “dog” compared to vertical npn

Availability of Logic

Low power/high densityUseful with S/H (sample hold) and SC (switch capacitor)circuitsImportant for calibration

Breakdown voltage

Power amplifiers, dynamic range of analog circuitry

Thermal conductivity

Power amplifiers

Quality and precision of passives

Inductors, capacitors, resistors, and transmission lines


Current Gain

ii

io = gmvgs =gmvgs

jω(Cgs + Cgd)

Ai =ioii

Since id = gmvgs , and vgs jω(Cgs + Cgd ) = is , taking the ratiowe have

Ai =idis

=gm

jω(Cgs + Cgd )

Solving for |Ai = 1|, we arrive at the unity gain frequency

ωT = 2πfT =gm

Cgs + Cgd


Why fT?

vi

It is not at first obvious why fT plays such an important rolein analog (and digital) circuits. To see this, consider thesimple cascade amplifier, where a single stage amplifier drivesan identical copy. The gain of this first stage is given by theintrinsic gain of the amplifier, and the 3-dB bandwidth islimited by the pole at the high impedance node

ω0 =1

ro,1((1 + |A2|)Cgs,2 + Cd1,tot)


Cascade Example

Here Cd1,tot is the total drain capacitance(Cgd + Cds + Cwire + · · · ) and the effect of Millermultiplication is captured by boosting the second stage inputcapacitance by the gain A2. If the second stage is a cascodewith a small voltage gain between the gate/drain, then A2 canbe made smaller than unity to minimize its impact. So if weneglect the Miller effect, we have

ω0 =1

ro(Cgs + Cd ,tot)


Gain/Bandwidth Product

In most applications, we intend to embed this amplifier in afeedback loop, so the gain-bandwidth product is of interest.

For a feedback system, we know that we can approximatelytrade gain for bandwidth. So if we place the amplifiers in afeedback loop, we have

Gain = A0

BW = ω0

Gain × BW = A0ω0 < gmro1

ro(Cgs + Cd ,tot)

=gm

Cgs + Cd ,tot≈ ωT


fT in Digital Circuits

Even in a digital circuit, we find that fT plays a key role.Consider the time constant of a simple gate, such as aninverter. If the fan out of an inverter is unity, in other wordsthe inverter drives an identical copy of itself, then the load ofthe inverter is approximately Cgs + Cd ,tot .


fT in Digital Circuits (cont)

The discharge current takes a complicated form, but to firstorder the transistor acts like a switch with on-conductancegds = gm (in triode region), so the discharge time is given bythe product

τT =Cgs

gm=

1

ωT

For larger fan-out (FO) circuits (and/or gates), we just scalefT by the FO.


Bipolar Junction Transistors


BJT Cross Section

n+ buried layer

p+

n+ poly contact n+ emitter base collector

field oxide

p-type substrate

n

Most transistor “action” occurs in the small npn sandwichunder the emitter. The base width should be made as small aspossible in order to minimize recombination. The emitterdoping should be much larger than the base doping tomaximize electron injection into the base.

A SiGe HBT transistor behaves very similarly to a normalBJT, but has lower base resistance rb since the doping in thebase can be increased without compromising performance ofthe structure.


Bipolar Small-Signal Model

roCπ

Cµ

gmvin

+vin

−Rπ Ccs

B

E

Crb

rc

re

The resistor Rπ dominates the input impedance at lowfrequency. At high frequency, though, Cπ dominates.

Cπ is due to the collector-base reverse biased diodecapacitance.

Ccs is the collector to substrate parasitic capacitance. In someprocesses, this is reduced with an oxide layer.

Cπ has two components, due to the junction capacitance(forward-biased) and a diffusion capacitance


Bipolar Exponential

Due to Boltzmann statistics, the collector current is describedvery accurately with an exponential relationship

IC ≈ ISeqVBE

kT (1)

The device transconductance is therefore proportional tocurrent

gm =dICdVBE

= ISq

kTe

qVBEkT =

qICkT

(2)

where kT/q = 26mV at room temperature. Compare this tothe equation for the FET. Since we usually havekT/q < Vgs − VT , the bipolar has a much largertransconductance for the same current. This is the biggestadvantage of a bipolar over a FET.


Control Terminal Sensitivity

BJT:

10 = exp

(q∆VBE

kT

)∆VBE =

kT

q× ln 10 ≈ 60mV

MOSFET:

10 =

(VGS ,1 − VT

VGS ,2 − VT

)2

√10 =

(VGS ,1 − VT

VGS ,1 + ∆VGS − VT

)∆VGS =

1−√

10√10

(VGS ,1 + VT ) ≈ 1V


Bipolar Unity Gain Frequency

The unity gain frequency of the BJT device is given by

ωT =gm

Cπ + Cµ=

gm

Cdiff + 2Cje0 + Cµ(3)

where we assumed the forward bias junction has Cje ≈ 2Cje0

Since the base-collector junction capacitance Cµ is a functionof reverse bias, we should bias the collector voltage as high aspossible for best performance.

The diffusion capacitance is a function of collector current,Cdiff = gmτF

ωT =gm

gmτF + 2Cje0 + Cµ=

1

τF +2Cje0+Cµ

gm

(4)


Bipolar Optimum Bias Point

fT (GHz)

IC

10−310−4 10−2

0

40

160

220

80

No Kirk Effect

ωT →1

τF

We can clearly see that if we continue to increase IC , thengm ∝ IC increases and the limiting value of fT is given by theforward transit time ωT ≈ 1/τF

In practice, though, we find that there is an optimum collectorcurrent. Beyond this current the transit time increases. Thisoptimum point occurs due to the Kirk Effect. It’s related tothe “base widening” due to high level injection. (Not StarTrek!)


Base Transmit Time

Ci = Cj + Cdiff ≈ Cdiff = τF · gm

Base transmit time

Current gain unity freq.

fT =gm

2πCi≈ 1

2πτF

fT ≈2µn

2πW 2B

kT

q

fT ∝1

W 2B


CMOS FET Transistors


CMOS Cross Section

p-type substrate

n+ n+ n+ p+ p+ p+

S D G S D G

n-well

PMOS NMOS

LLov

VDD

Modern CMOS process has very short channel lengths(L < 100nm). To ensure gate control of channel, as opposedto drain control (DIBL), we employ thin junctions and thinoxide (Tox < 5nm).

Due to lithographic limitations, there is an overlap betweenthe gate and the source/drain junctions. This leads to overlapcapacitance. In a modern FET this is a substantial fraction ofthe gate capacitance (up to half).


CMOS DNW Device

NW NWPWPW PW

P-Substrate

In a standard CMOS process, only the PMOS is isolated bythe n-well. All NMOS devices share a common body (psub).This means that the body-source cannot be tied together(unless grounded) and moreover, digital substrate noisecouples to sensitive analog and RF circuitsIn many processes, a deep n-well (“DNW”) can be used toisolate the p-well. This is like a triple-well process, allowingisolated NMOS transistors. The DNW is formed from a ringof NW and an overlapping DNW region.

NW NWPWPW PW

P-Substrate

DNW


FET Small Signal Model

Cgs gmvgs gmbvbs ro

+vgs

−

CgdRg

Cdb

RS CsbCgb

G

S

D

B

The junctions of a FET form reverse-biased pn junctions withthe substrate (well), or the body node. This is another formof parasitic capacitance in the structure, Cdb and Csb.

At DC, input is an open circuit. The input impedance has asmall real part due to the gate resistance Rg (polysilicon gateand NQS) and Rs,d account for junction and contactresistance.


FET Simplified Models

In the forward active (saturation) region, the inputcapacitance is given by Cgs

Cgs =2

3W · L · Cox + Cpar

Don’t forget that layout parasitics increase the capacitance inthe model, sometimes substantially (esp in deep submicrontechnologies). Ro is due to channel length modulation andother short channel effects (such as DIBL).

Cgs gmvgs gmbvbs ro

+vgs

−

Cgd

Cdb

CsbCgb

G

S

D

B

Cgs gmvgs ro

+vgs

−

Cgd

Cdb

G

S

D

For low frequencies, the resistors are ignored. But theseresistors play an important role at high frequencies.If the source is tied to the bulk, then the model simplifies.


FET Extrinsic Model

G

DS

B

Rge

Cgse Cgde

Rse Rde

Cbse Cbde

Rs,bs Rs,bd

Rbe

Substrate parasitics, gate resistance, source/drain resistances,extra metal and contact resistance and capacitance. At veryhigh frequencies, the distributed inductance of the leads.


Intrinsic Voltage Gain

Important metric for analog circuits

Av ,mos = gmro =2IDS

Vdsat

VA

IDS= 2

VA

Vdsat

Av ,bjt = gmro =qICkT

VA

IC= 2

VAkTq

Communication circuits often work with low impedances inorder to achieve high bandwidth, linearity, and matching.

To achieve high fT , the Vdsat is relatively large so the currentis increased to obtain sufficient gain.


Voltage Gain for Tuned Amplifiers

Inductive loads are also common to tune out the loadcapacitance and form a resonant circuit. The gain is thusgiven by

Av = gmRp = gmω0QL

In a given process, there’s a maximum Q that we can obtain,usually Q ∼ 10 at 1 GHz in a typical 90nm process with thickmetal options. The inductance cannot be increased withoutbound due to area limitations and ultimately due to thetuning requirements

ω0L =1

ω0(Cgs + Cdb + Cpar )

ω0L ≤1

ω0Cgs

Av = gmω0QL = gmQ1

ω0Cgs=

gm

Cgs· Q · 1

ω0= Q · fT

f0


DC Gain for Short Channel Devices

1e-07 2e-07 3e-07 4e-07 5e-07 6e-07 7e-07 8e-07 9e-07 1e-06

A 0

L (m)

Vgs=1.2V

0 0.2 0.4 0.6 0.8 1 1.2

A 0

Vds

L=100nmL=200nmL=250nmL=500nm

L=1000nm

CMOS is running out of steam because the DC gain per deviceis dropping with smaller L. This makes design very difficult,especially since the DC gain drops with supply voltage.

Most fast transistor come with the penalty of lower speed ofoperation.


Normalized Gain

For a bipolar device, the exponential current relationshipresults in a high constant normalized gain

gm

IC=

q

kT≈ 1

26mV

For a square law MOSFET, in saturation we have

gm

IDS=

2

VGS − VT

In weak inversion, the MOSFET is also exponential

gm

IDS=

q

nkT≈ 1

26mV

1

n

The factor n is set by the ratio of oxide to depletioncapacitance


MOSFET in Subthreshold

In sub-threshold, the surface potential varies linearity with VG

The surface charge, and hence current, is thus exponentiallyrelated to VG


I-V Curves Vgs

0 0.2 0.4 0.6 0.8 1 1.2

I ds

Vgs

Vds=50mVVds=250mVVds=650mVVds=1.25V

The I-V curve of a given transistor with fixed dimension (Wand L) reveals most of the salient features. For example, aplot of Ids versus Vgs for a family of Vds quickly revealscurrent drive capability. If a device is biased in weak ormoderate inversion, then the logarithmic plot is more useful asit expands this regime of operation.


I-V Curves Vgs (log)

0 0.2 0.4 0.6 0.8 1 1.2

log(

I ds)

Vgs

Vds=50mVVds=250mVVds=450mVVds=750mVVds=850mVVds=1.25V

The leakage currents (sub-threshold slope) is important inanalog applications that use the transistor as a switch. If thedevice cannot be turned off, then it’s very difficult to buildhigh precision discrete time circuits.


I-V Curves Vds

0 0.2 0.4 0.6 0.8 1 1.2

I ds

Vds

Plotting the current versus drain-source voltage, or a plot ofIds versus Vds for a family of Vgs shows the current saturationbehavior of a device. The output conductance is more easilyobserved using small-signal parameters as discussed shortly,but certain trends can be observed even from the raw I-Vcurves.


MOS Transconductor Efficiency

Since the power dissipation is determined by and large by theDC current, we’d like to get the most “bang for the buck”.

From this perspective, the weak and moderate inversionregion is the optimal place to operate.

The price we pay is the speed of the device which decreaseswith decreasing VGS

Current drive is also very small.


Transconductance (Vgs)

0 0.2 0.4 0.6 0.8 1 1.2

g m

Vgs


L=1000nm

The value of gm increases with Vgs . For the diffusioncomponent of current, at low overdrive, the increase in gm isexponential due to the exponential dependence of current ongate voltage.For the drift component of current, Ids is proportional to theamount of charge in the channel and the carrier velocity. Thechannel charge scales in proportion to the gate bias, so for afixed mobility, we expect the gm to increase linearly.


gm vs. Vgs (cont)

0

200

400

600

Effective FieldM

obilit

y

Triode CLM DIBL SCBE

Rou

tkΩ

Vds (V)

2

4

6

8

10

12

14

0 1 2 3 4

In fact, for low fields, due to Coulomb scattering, the mobilitywill experience an enhancement due to screening provided bythe inversion layer, and the increase in gm is faster than linear.

On the other hand, due to high field effects, we know themobility will eventually degrade as carriers are pushed closerto the silicon-insulator interface, where surface scatteringcauses the mobility to drop.


gm vs. Vds

0 0.2 0.4 0.6 0.8 1 1.2

g m

Vds


L=1000nm

The trend for gm as a function of Vds can be divided into tworegions. In the triode region of operation, increasing Vds

increases the current, so the overall gm increases.

As the device nears saturation, one would expect the gm tosaturate.


Output Conductance

0 0.2 0.4 0.6 0.8 1 1.2

g ds

Vds


L=1000nm

gds in triode region is very large since the drain voltage has adirect impact on the channel charge. In fact, to first order,gds = gm since varying the gate has the same impact asvarying the gate due to the presence of the inversion layer,making the drain terminal just as effective as the gate-source.

In a long channel device, in the so-called pinch-off region, thedevice terminal no longer controls the channel charge directly,and the output conductance drops dramatically.


Output Resistance

0 0.2 0.4 0.6 0.8 1 1.2

r o

Vds


L=1000nm

The drain still modulates the depletion region width, whichindirectly impacts the device through channel lengthmodulation (CLM).

In short channel devices, both because of the increase in therelative magnitude of the change in channel length δL relativeto L, but also due to Drain Induced Barrier Lowering (DIBL).


Output Resistance Broken Down

Triode CLM DIBL SCBE

Rou

tkΩ

Vds (V)

2

4

6

8

10

12

14

0 1 2 3 4


FET Unity Gain Frequency

Long channel FET:

Note that there is apeak fT sinceeventually themobility of thetransistor drops dueto high vertical fields

Short channel limit:

fT =1

2π

gm

Cgs + Cgb + Cgd

assuming Cgs Cgb + Cgd

fT =1

2π

gm

Cgs=

1

2π

3

2

µn

L2(VGS − VT )

IDS ≈ vsatQinvW = WCox (VGS − VT )vsat → gm = WCoxvsat

fT =1

2π

gm

Cgs=

3

2

WCoxvsat

WLCox∝ 1

L


Scaling Speed Improvements

0

1

10

100

1980 1985 1990 1995 2000 2005

long-c

hannel regio

n

short-channel re

gion

year

fT

CMOS transistors have steadily improved in performance justas predicted by theory. In the short channel regime theimprovements are linear with scaling.

At the same time, the decreasing supply voltage has led to areduced dynamic range. Also the maximum gain has notimproved as much· · ·


fT versus Dimension

1e-07 2e-07 3e-07 4e-07 5e-07 6e-07 7e-07 8e-07 9e-07 1e-06

f T

L (m)

Vgs=1.2V

The well known improvement in fT with channel scaling isshown here. Since both gm and Cgs depend linearity on thewidth, only the channel length L matters.

Shorter channel lengths improve both the gm and lower thecapacitance of the device. In the velocity saturated limit, onlythe drop in capacitance plays a role.


Cgs versus Bias

Classical

Quantum

Poly Depletion

Cgg

Cox

VGBVFB VTH

The MOS capacitor of modern devices does not followclassical equations due to polysilicon depletion and quantumeffects ...


fT versus Bias

0 0.2 0.4 0.6 0.8 1 1.2

f T

Vgs


L=1000nm

To go fast, you must burn power ...

It is important to note that fT is usually measured usingscattering parameters and so using the “DC” values of gm andC will fail to capture fT at high frequency. We will return tothis point in the RF section of this chapter.


High Frequency


Maximum Two-Port Power Gain

Measure or calculate two-port parameters at a particularfrequency. To obtain maximum gain Gmax , design an inputand output matching network to satisfy the followingconditions

YS = Y ∗in

YL = Y ∗out

where YS and YL are the source and load admittance seen bythe two-port and Yin and Yout are the input and outputadmittance seen looking into the two-port when loaded bythese matched admittances.This leads to two equations and two unknowns (4 real).


Maximum Power Gain fmax

fmax = max. freq. of activity = max. freq. of oscillation =freq. when power gain = 1

Gp ≈

(fTf

)24rx(go + gm

CµCπ

)+ 4rxgo

Gmax ≈fT

8πrxCµf 2max

= 1

fmax =

√fT

8πrxCµ

Cπ

Cµ

+vπ

−

gmvπ

rx

go


FET fmax

Ids

gds

Rs

Rg

Cgs

Rd

L

Source Gate Drain

Cgso Cgdo

WF

Csb

Rsb

Cdb

RdbRbb

Bulk

p-sub

fT ≈gm

2πCgg

fmax ≈fT

2√

Rg (gmCgd/Cgg ) + (Rg + rch + Rs )gds

Minimize all resistances

Rg –use many small parallel gate fingers, < 1µm eachRsb, Rdb and Rbb – substrate contacts < 1− 2µm from deviceRs , Rd – don’t use source/drain extensions to reduce L


SiGe HBT and CMOS FinFETs


SiGe Technology

Higher Performance: Demonstrations of fT > 500GHz andapproach 1THz.

Problem:

As WB decreases → rb increases

Solution:

SiGe base allows for higher fTwithout reducing WB


SiGe HBT Action

A SiGe BJT is often called an HBT (heterojunction bipolartransistor)

Ge epitaxially grown in base

Causes strain in crystalCauses extra potential barrier for holes (majority carrier) in thebase from flowing into emitter

Beneficial effects

WB decreases, NB increases, rb lowNE decreases, Cj decreases


GaAs/InP Technology

Electric Field (V/cm)

Car

rier

Dri

ft V

elo

city

(cm

/s)

10 101010 102 654310 5

108

10 7

10 6

Si

Ge

InPGaAs

Si

One of the primary advantages of the III-V based transistors isthe higher peak mobility compared to Si. With short channeldevices, most of the current flow is due to velocity saturation,which greatly limits the advantages of III-V over silicon.

The insulating substrate also allows higher Q passives.

The extra cost of these technologies limits it to nicheapplications such as very high frequencies, high performance,and power amplifiers.


FinFETs and Multigate Transistors

To combat the problems with scaling of MOSFETs below45nm, Berkeley researchers introduced the “FinFET”, adouble gate device. (Intel uses this technology at the 22nmnode)

Due to thin body and double gates, there is better “gatecontrol” as opposed to drain control, leading to enhancedoutput resistance and lower leakage in subthreshold.


FinFET Structure and Layout

Gate straddles thin silicon fin, forming two conductingchannels on sidewall

Multi-finger layout very similar to RF layout.


An Aside on Thermal Conductivity

GaAs

Semi-insulating substrateNot very good conductor of heatHigh quality passive elements (next topic)

Si

Semi-conducting substrateGood conductor of heatLossy substrate leads to lower quality passives


An Aside on Thermal conductivity (2)

Also depends on packaging

Example: in flip-chip bonding, thermal conductivity function ofnumber of bumps rather than substrateBack-side of die can lose heat through radiation or convectionthrough air but thermal contact is much more effective

Flip chip bonding

Wire bonding


FET/BJT Comparisons


High BJT Transconductance

gm =dICdVBE

= ISq

kTe

qVBEkT =

qICkT

For fixed current, BJT gives more gain

Precision

Important in multiplication, log, and exponential functionsMore difficult in FETs due to process/temp. dependenceIS process dependent in BJT ... use circuit tricks


Advantages of BJT

gm

IC=

q

kT=

1

25mV

gm

ID=

2

VGS − VT≈ 1

250mV

IC ∝ e−E/kt = eqVBE/kT

For high-speedapplications, need to biasin stronginversion...Results in ∼10xlower efficiency

For a BJT, this relationship is fundamental and related to theBoltzman statistics (approximation of Fermi-Dirac statistics)

For a MOSFET, this relationship is actually only valid for asquare-law device and varies with VT (body bias) andtemperature


Advantage of BJT over FET (2)

Better precision

About 4 decades(420mV) of linearity

Example:

VBE1 + VBE2 = VBE3

VBE = VT ln

(ICIS

)IC1 · IC2

IS1 · IS2=

IC3

IS3

log(IC)

VBE(V)420mV

Can build exp, log, roots, vector mag

Lower 1/f noise corner

Lower offset voltageVOS ∼ 1mV


Disadvantage of BJT

rb hurts gain (power), NF

SiGe allows fast transistors with low rb

Exponential transfer function (advantage and disadvantage)

Exponential → non-linear

Expensive in high volumes, cheaper in low volumes

Absence of a switch

Old CMOS gets cheaper!45nm ∼ $1M mask → 0.25µm $50k mask


Advantage of FET over BJT

Cheaper and more widely available (many fabs in US, Asia,and Europe)

Square law → less distortion

PMOS P-FET widely available, only ∼ 2× less performance.

Triode region → variable resistor

Widely available digital logic

Low leakage in gates

Sample and hold (S/H) and switch cap filters (SCF)

Dense digital circuitry / DSP for calibration

Offset voltages and mismatches can be compensated digitally

Dense metal layers allows MIM (“MOM”) capacitors for free


References and Further Reading

UCB EECS 142/242 Class Notes (Niknejad/Meyer)

UCB EECS 240 Class Notes (Niknejad/Boser)

Analysis and Design of Analog Integrated Circuits, Paul R.Gray, Robert G. Meyer. 3rd ed. New York : Wiley, c1993.

Manku, T. “Microwave CMOS-device physics and design,”IEEE Journal of Solid-State Circuits, vol.34, (no.3), March1999. p.277-85. 32


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Active Devices for Communication Integrated Circuits