GLSVLSI'07

Proceedings of the

mmMM Great Lakes

special interest group on

design automation

with technical support from:

IEEE CAS

&CEDA

and corporate support from:

StlVlicroelectronies

TIB/UB Hannover 89130 457 523

Table of Contents

Foreword iii

GLSVLSP07 Organization xiii

Additional Reviewers xv

Sponsor & Supporters xvii

Monday, March 12th

Keynote Talk 1 » 8:30 - 9:15 a.m.

® Design Challenges in 45nm and Below: DFM, Low-Power and Design for Reliability 1

P. Magarshack (STMicroelectronics)

Session 1 A: Architecture and Memory » 9:15-10:55 a.m.

• Improving Performance and Energy Consumption in Embedded MicroprocessorPlatforms with a Flexible Custom Coprocessor Data-path 2

M. D. Galanis, G. Dimitroulakos, C. E. Goutis (University ofPatras)

» An Optimized Linear Skewing Interleave Scheme

for On-chip Multi-access Memory Systems 8

C. Liu, X. Yan, X. Qin (Zhejiang University)

• l-Cache Multi-Banking and Vertical Interleaving 14

S. Cho (University ofPittsburgh)

• A VLSI Architecture Design of an Edge Based Fast Intra

Prediction Mode Decision Algorithm for H.264/AVC 20

S. Li, X. Wei, T, Ikenaga, S, Goto (Waseda University)

Session 1B: Timing and Power Analysis • 9:15-10:55 a.m.

• Nostra-XTalk: A Predictive Framework for Accurate

Static Timing Analysis in UDSM VLSI Circuits 25

D. Das, A. Shebaita, Y. Ismail, H. Zhou (North-western University), K. Killpack (Intel Corporation)

® Dummy Fill Aware Buffer Insertion During Routing 31

Y. Jia, Y. Cai, X. Hong (Tsinghua University)

• Probabilistic Gate-level Power Estimation using a Novel Waveform Set Method 37

S. T. Oskuii, P. G. Kjeldsberg, E. J. Aas (Norwegian University ofScience and Technology)

» Robust Wiring Networks for DfY Considering Timing Constraints 43

P, Panitz, M. Olbrich, E. Barke (University ofHannover), J. Koehl (IBMDeutschlandEntwickhng GmbH)

Session 1C: Test and Reliability • 9:15 - 10:55 a.m.

• Simultaneous Reduction in Test Data Volume and Test Time for TRC-Reseeding 49

B. Zhou, Y.-Z. Ye, Y.-S. Wang (Harbin Institute ofTechnology)

• SEU Mitigation for SRAM-Based FPGAs through Dynamic Partial Reconfiguration 55

C, Bolchini, D. Quarta, M. D. Santambrogio (Politecnico di Milano)

v

• Estimating Path Delay Distribution Considering Coupling Noise 61

R. Tayade (University of Texas at Austin), V. K. Kalyanam (Advanced Micro Devices Inc.),

S. Nassif (IBM Austin Research Laboratory), M. Orshansky, J. Abraham (University of Texas at Austin)

« Co-Evolutionary High-Level Test Synthesis 67

S. Aininzadeh, S. Safari (University of Tehran)

Session 2A: Device, Interconnect, and Power Optimizationfor nano-CMOS ® 11:15 a.m. - 12:55 p.m.

• Optimizing FinFET Technology for High-Speed and Low-Power Design 73

T. Sairam (Sun Microsystems Inc.), W. Zhao, Y. Cao (Arizona State University)

• Analysis of Data Dependence of Leakage Current in CMOS Cryptographic Hardware 78

J. Giorgetti, G. Scotti, A. Simonetti, A. Trifiletti (Universita di Roma "La Sapienza ")

• Temperature-Aware Circuit Design using Adaptive Body Biasing 84

Y. Zhang (Qualcomm), M. Stan (University of Virginia)

• Using Buffered Crossbars for Chip Interconnection 90I, Papaefstathiou, G. Kornaros (Technical University ofCrete), N. Chrysos (ICS-FORTH)

Session 2B: Emerging Technologies • 11:15 a.m. - 12:55 p.m.

• Exact SAT-based Toffoli Network Synthesis 96

D, Grofle, X. Chen (University ofBremen), G. W. Dueck (University ofNew Brunswick),R. Drechsler (University ofBremen)

• Combinational Equivalence Checking for Threshold Logic Circuits 102

T, Gowda, S. Vrudhula, G. Konjevod (Arizona State University)

• On-Chip Characterization of Molecular Electronic Devices:

The Design and Simulation of a Hybrid Circuit Based

on Experimental Molecular Electronic Device Results 108N. Gergel-Hackett (NationalInstitute ofStandards and Technology),G. S. Rose, P. Paliwoda (Polytechnic University),C. A. Hacker, C. A, Richter (National Institute ofStandards and Technology)

• Operation Limits in RTD-based Ternary Quantizers 114J, Nufiez, J. M. Quintana, M. J. Avedillo (Instituto de Microelectronica de Sevilla & Universidad cle Sevilla)

Session 2C: Low Power Architecture and Interconnect -11:15 a.m. - 12:55 p.m.

• Transition-activity Aware Design of Reduction-stages for Parallel Multipliers 120S. T, Oskuii, P. G. Kjeldsberg (Norwegian University ofScience and Technology),0. Gustafsson (Linkoping University)

• Reducing Snoop-Energy in Shared Bus-Based MPSoCs by Filtering Useless Broadcasts 126C.-M. Chung, J. Kim (Seoul National University), D. Kim (University of California at San Diego)

• GALS SoC Interconnect Bus for Wireless Sensor Network Processor Platforms 132C. H. Fernandez, R. K. Raval, C. J. Bleakley (University College Dublin)

• Sensitive Registers: a Technique for Reducingthe Fetch Bandwidth in Low-Power Microprocessors 138A. Robinson, J. D, Garside (The University ofManchester)

Poster Session 1

» Side-channel Resistant System-level Design Flow for Public-key CryptographyK. Sakiyama, E. De Mulder, B. Preneel, I, Verbauwhede (Katholieke Universiteit Leuven /IBBT)

144

» Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop 14X

Raghavendra. R G, B. Amrutur tindian Institute of Science)

« A New Approach to Logic Synthesis of Multi-Output BooleanFunctions on PAL-based CPLDs 152

D. Kania (Silesian University of TechnologyI

® A Novel Charge Recycler for TFT-LCD Source Driver IC 156D. Li, T. Wei. W. Wu (Northwestern University)

8 Hardware-Efficient Propagate Partial SAD Architecture

for Variable Block Size Motion Estimation in H.264/AVC 160

Z. Liu, Y. Huang, Y. Song, S. Goto, T. Ikenaga tWaseda University)

» Compiler Assisted Architectural Exploration for Coarse Grained Reconfigurable Arrays 164

G. Dimitroulakos, N. Kostaras, M. D. Galanis, C. E. Goutis (University of Putrus)

» Self-biased Charge Sampling Amplifier in 90nm CMOS for Medical Ultrasound Imaging 168

L. R. Cenkeramaddi, T. Singh, T. Ytterdal (Norwegian University ofScience and Technology)

8 RT Level Reliability Enhancement by Constructing Dynamic TMRs 172

N. Karimi, S. Mirkhani, Z. Navabi (University ofTehran), F. Lombardi (Northeastern University)

8 An Asynchronous FPGA Logic Cell Implementation 176

A. Mahram, M. Najibi, H. Pedram (Amirkabir University of Technology)

8 Real-time Implementation of a Time-frequency Analysis Scheme 180

M. Martina (Politecnico di Torino), A. Terreno (Centra RicercheFIAT),

F. Vacca, A. Molino, G. Masera (Politecnico di Torino), G. D'Angelo, G. Pasquettaz (Centro Ricerche FIAT)

8 Flexible Blocks for High Throughput Serially Concatenated Convolutional Codes 184

M. Martina, G. Masera (Politecnico di Torino)

8 Novel Architectures for Efficient (m, n) Parallel Counters 188

S. Veeramachaneni, L. R. Avinash, M. K. Krishna, M. B. Srinivas (International Institute ofInformation Technology)

• High CMRR Current Mode Operational Amplifier with a Novel Class AB Input Stage 192

M, Alton, H. Kuntman (Istanbul Technical University)

8 Hardware Architecture for Matrix Factorization in MIMO Receivers 196

B. Cerato, G. Masera (Politecnico di Torino), P. Nilsson (Lund University)

8 Reduced-Complexity MIMO Detector with Close-to ML Error Rate Performance 200

C. Hess, M. Wenk, A. Burg, P. Luethi, C. Studer, N. Felber, W. Fichtner (ETHZurich)

8 Design and Realization of a Fault-Tolerant 90nm CMOS CryptographicEngine Capable of Performing under Massive Defect Density 204

M. Stanisavljevic, F. K. Giirkaynak, A. Schmid, Y. Leblebici (Swiss Federal Institute ofTechnology),M, Gabrani (IBMZurich Research Laboratory)

8 Exploring Subsets of Standard Cell Libraries to ExploitNatural Fault Masking Capabilities for Reliable Logic 208

D. C. Ness, C. J. Hescott, D. J. Lilja (Univesity ofMinnesota)

8 A Symmetric Mos Current-Mode Logic Universal Gate for High Speed Applications 212

O. M. Abdulkarim, M. Shams (Carleton University)

8 An Automated Unique Tagging System Using CMOS Process Variation 216

B. L. Dell, J. F. Bolus, T. N. Blalock (University ofVirginia)

8 A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA 219

A. Tumeo, M. Monchiero, G. Palermo, F. Ferrandi, D. Sciuto (Politecnico di Milano)

• Probabilistic Maximum Error Modeling for Unreliable Logic Circuits 223

K. Lingasubramanian, S. Bhanja (University ofSouth Florida)

vn

« Critical Charge and SET Pulse Widths for Combinational Logic

in Commercial 90nm CMOS Technology 227

R. Naseer, J. Draper, Y. Boulghassoul (University ofSouthern California),

S. DasGupta, A. Witulski (Vanderbilt University)

« Active Bank Switching for Temperature Control

of the Register File in a Microprocessor 231

K. Patel, W. Lee, M. Pedram (University ofSouthern California)

Keynote Talk 2 * 2:45 - 3:30 p.m.

e Sleep Transistor Distribution in Row-Based MTCMOS Designs 235

C. Hwang (SamsungElectronics), P. Rong (LSI Logic Corporation),M. Pedram (University ofSouthern California)

Session 3A: Circuits and Logic * 3:30 - 5:10 p.m.

8 A New Decompression System for the Configuration Process of SRAM-Based FPGAs 241

L. Sterpone, M. Violante (Politecnico di Torino)

8 Minimizing Peak Power in Synchronous Logic Circuits 247

K. Rahimi (Impinj. Inc.)

8 Linearized CMOS Active Resistor Independent on the Bulk Effect 253

C. Popa (University Politehnica ofBucharest)

a Structured and Tuned Array Generation (STAG) for High-Performance Random Logic 257

M. M. Ziegler, G. S. Ditlow, S. V. Kosonocky (IBM T.J. Watson Research Center),Z. Qi, M. R. Stan (University ofVirginia)

Session 3B: Emerging Technologies for Low Power Design * 3:30 - 5:10 p.m.

8 Design of Mixed Gates for Leakage Reduction 263

F. Sill, J. You, D. Timmermann (University ofRostock)

8 Modeling and Estimating Leakage Current in Series-Parallel CMOS Networks 269

P. F. Butzen (Instituto de Informdtica - UFRGS), A. I. Reis (NangateInc.),C. H. Kim (University ofMinnesota), R. P. Ribas (Instituto de Informdtica - UFRGS)

8 Analyzing and Modeling Process Balance for Sub-threshold Circuit Design 275

J. F. Ryan, J. Wang, B, H. Calhoun (University of Virginia)

8 Viewing Direction-Aware Backlight Scaling 281

C.-N. Wu, W.-C. Cheng (National Chiao Tung University)

Session 3C: Digital Synthesis • 3:30 - 5:10 p.m.

8 Synthesis of Irregular Combinational Functions with Large Don't Care Sets 287

V. Gherman (CEA), H.-J. Wunderlich, R. Mascarenhas (Universitaet Stuttgart),J. Schloeffel, M. Garbers (NXP Semiconductors)

8 DAG Based Library-Free Technology Mapping 293

F. S. Marques, L. S. Rosa Jr., R. P. Ribas (Instituto de Informdtica - UFRGS),S. S. Sapatnekar (University ofMinnesota), A. I. Reis (Instituto de Informdtica & Nangate Inc.)

a Using Standard ASIC Back-End for QDI Asynchronous Circuits:

Dealing with Isochronic Fork Constraint 299

M. Najibi, K. Saleh, H. Pedram (Amirkabir University of Technology)

8 An Evolutionary Approach for Standard-Cell Library Reduction 305

A. Ricci, I. De Munari, P. Ciampolini (University ofParma)

via

Keynote Talk 3 « • 5:30 - 6:15 p.m.

e Multi-Processor Operating System Emulation Frameworkwith Thermal Feedback for Systems-on-Chip 311S. Carta, M. Pittau (DMl-University Cagliari), A. Acquaviva (STI/Univcr.sity ofUrbino),P. G. Del Valle (DACYA-Complutense University ofMadrid), D. Atienza, G. De Micheli (LSI/EPFL),F. Rincon (UCLM), L. Benini (DEIS/Bologna University), J. M. Mendias (University oj Madrid)

Tuesday, March 13th

Keynote Talk 4 » 8:30 - 9:15 a.m.

a Computer-Aided Design of 3D Integrated Circuits 317S. S. Sapatnekar (University ofMinnesota)

Session 4A: Special Session - Embedded Tutorial»9:15 -10:55 a.m.

8 DFM Issues for 65nm and Beyond 318J. Kawa, C. Chiang (Synopsys, Inc.)

Session 4B: ASIP/ASIC 8 9:15 -10:55 a.m.

8 Utilizing Custom Registers in Application-specific Instruction Set Processors

for Register Spills Elimination 323

H. Lin, Y. Fei (University ofConnecticut)

8 Implementation of a JPEG Object-Oriented ASIP:

A Case Study on a System-Level Design Methodology 329

N. MohammadZadeh, M. NajafVand, S. Hessabi, M. Goudarzi (Sharif University ofTechnology)

• Beyond 3G Wireless Communication System Prototype 335

A. Dassatti, S, Zezza, M. Nicola, G. Masera (Politecnico di Torino)

8 A New Hardware Architecture for Performing the Gridding of DNA Microarray Images 341

L. Sterpone, M. Violante (Politecnico di Torino)

Session 4C: System Level Design • 9:15 - 10:55 a.m.

8 A Design Methodology for Space-Time Adapter 347

C. Cyrille (STMicroelectronics), C. Philippe (UBS University),U. Pascal (STMicroelectronics), M. Eric (UBS University)

8 A Synchronization Algorithm for Local Temporal Refinements

in Perfectly Synchronous Models with Nested Feedback Loops 353

T. Raudvere, I. Sander, A. Jantsch (Royal Institute ofTechnology)

8 HW/SW Partitioning Using Discrete Particle Swarm 359

A. Farmahini-Farahani (University ofTehran), M. Kamal (SharifUniversity ofTechnology),S. M. Fakhraie, S. Safari (University ofTehran)

8 Complexity-Constrainted Partitioning of Sequential Programsfor Efficient Behavioral Synthesis 365

Y. Hara, H. Tomiyama, S. Honda, H. Takada, K. Ishii (Nagoya University)

Session 5A: CMOS & Logic Applications Optimizationand Techniques 811:15 a.m.-12:55 p.m.

8 Bus-Encoding Technique to Reduce Delay, Powerand Simultaneous Switching Noise (SSN) in RLC Interconnects 371

C. Raghunandan, K. S. Sainarayanan, M. B. Srinivas (International Institute ofInformation Technology)

IX

a A 5 GHz Wide Band Input and Output Matched Low Noise Amplifier 377

R, Salmeh, B. Maundy (University ofCalgary)

« A 900 MHz ISM Band MASH-12 Fractional-N Frequency Synthesizer

for 5-Mbps Data Transmission 381

H. Arora (Marvell Semiconductor), N. Klemmer (Ericsson Mobile Platforms), P. Wolf (Duke University)

o Design of an UHF RFID Transponder for Secure Authentication 387

P. Bernardi, F. Gandino, B. Montrucchio, M. Rebaudengo, E. R. Sanchez (Politecnico di Torino)

Session 5B: Verification Techniques • 11:15 a.m. - 12:55 p.m.

» Effective Heuristics for Counterexample-Guided Abstraction Refinement 393

F. He (Tsinghua University), X. Song (Portland State University), M. Gu, J. Sun (Tsinghua University)

« Reducing Verification Overhead with RTL Slicing 399

J.-C. Ou, D. G. Saab (Case Western Reserve University), Q. Qiang (Synopsys Inc.),J. A. Abraham (The University ofTexas atAustin)

« Optimization Techniques for BDD-based Bisimulation Computation 405

R. Wimmer, M. Herbstritt, B. Becker (Albert-Ludwigs University)

• Hardware-Accelerated Path-Delay Fault Grading of Functional Test Programsfor Processor-based Systems 411

P. Bernardi, M. Grosso, M. S. Reorda (Politecnico di Torino)

Session 5C: Optimization and Verification • 11:15 a.m. - 12:55 p.m.

• An Approximation Algorithm for Fully Testable kEP-SOP Networks 417A. Bernasconi (University ofPisa), V. Ciriani, R. Cordone (University ofMilano)

• A Coefficient Optimization and Architecture Selection Tool

for SD Modulators Considering Component Non-Idealities 423

M. O. Saglamdemir, O, Yetik, S. Talay, G. Dundar (Bogazici University)

• Hand-in-hand Verification of High-level Synthesis 429C. Karfa, D. Sarkar, C. Mandal (Indian Institute ofTechnology), C. Reade (Kingston University)

• Area Minimization Algorithm for Parallel Prefix Adders

under Bitwise Delay Constraints 435T. Matsunaga (FLEETS), Y. Matsunaga (Kyushu University)

Poster Session 2

• A New Algorithm for the Largest Compositionally Progressive Solution

of Synchronous Language Equations 441T. Villa (Universitd Verona), S. Zharikova, N. Yevtushenko (Tomsk State University),R, Brayton, A. Sangiovanni-Vincentelli (University of California at Berkeley)

• An Efficient Cost-Based Canonical Form for Boolean Matching 445G. Agosta, F. Bruschi, D. Sciuto (Politecnico di Milano)

« Evaluation of Using Active Circuitry for Substrate Noise Suppression 449R. Farivar, S. Kristiansson, F. Ingvarson, K. O. Jeppson (Chalmers University ofTechnology)

• The Effect of Temperature on Cache Size Tuning for Low Energy Embedded Systems 453H. Noori, M. Goudarzi, K. Inoue, K. Murakami (Kyushu University)

• Efficient Space-Time NoC Path Allocation Basedon Mutual Exclusion and Pre-reservation 457S. Evain, J.-P. Diguet (UBS/CNRS)

x

8 Skew Spreading for Peak Current Reduction 461

Z. Yu (North Carolina State University), M. C. Papaefthymiou (University ofMichigan),X. Liu (North Carolina State University)

» Block Placement to Ensure Channel Routability 465

S. Nakatake (University ofKitakyushu), Z. Karimi, T. Taghavi, M. Sarrafzadeh

(University ofCalifornia at Los Angeles)

» GA-SVM Feasibility Model and Optimization Kernel Appliedto Analog IC Design Automation 469

M. Barros (Instituto de Telecomunicacoes, Escola Superior de Tecnologia de Tamar & Instituto Superior Ticnico),J. Guilherme (Instituto de Telecomunicacoes & Escola Superior de Tecnologia de Tomar),

N. Horta (Instituto de Telecomunicacoes & Instituto Superior Tecnico)

• Physical Aware Clock Skew Rescheduling 473

X. Wei, Y. Cai, X. Hong (Tsinghua University)

o A Low-Power 333Mbps Mobile-Double Data Rate Output Driver

with Adaptive Feedback to Minimize Overshoots and Undershoots 477

R. K. Gupta, V. Naran, R. H.M., V. Menezes (Texas Instruments India Pvt. Ltd.)

• Extended Register-Sharing in the Synthesisof Dual-Rail Two-Phase Asynchronous Datapath 481

K. Ohashi, M. Kaneko (Japan AdvancedInstitute ofScience and Technology)

8 Three-Valued Automated Reasoning on Analog Properties 485

R. Gentilini, K. Schneider (Kaiserslautern University), A. Dreyer (Fraunhofer 1TWM)

• On the Energy Efficiency of Synchronization Primitives

for Shared-Memory Single-Chip Multiprocessors 489

0. Golubeva, M. Loghi, M. Poncino (Politecnico di Torino)

• Improvements for Constraint Solving in the SystemC Verification Library 493

D. GroBe (University ofBremen), R. Ebendt (Institute ofTransportResearch),

R. Drechsler (University ofBremen)

• Systematic Design of Two-Stage Operational Amplifiers Based

on Settling Time and Open-Loop Constraints 497

H. Aminzadeh, M. Danaie (Ferdowsi University ofMashhad)

» Design of a Family of Sleep Transistor Cells

for a Clustered Power-Gating Flow in 65nm Technology 501

A. Calimera, A. Pullini, A. V. Sathanur (Politecnico di Torino),

L. Benini (Universitd di Bologna), A. Macii, E. Macii, M. Poncino (Politecnico di Torino)

• StateCharts to SystemC: a High Level Hardware Simulation Approach 505

M. Mura, M. Paolieri (ALaRi), L. Negri, M. G. Sami (Polytechnic ofMilan)

• A Lightweight Parallel Java Execution Environment

for Embedded Multiprocessor Systems-on-Chip 509

M. Mantovani, S. Leardini, M. Ruggiero, L. Benini (University ofBologna),A. Acquaviva (University ofUrbino)

» Improvement of Power Distribution Network

using Correlation-based Regression Analysis 513

S. Hagiwara, T. Uezono, T. Sato, K. Masu (Tokyo Institute ofTechnology)

8 A High-Level Register Optimization Technique

for Minimizing Leakage and Dynamic Power 517

D. Dal, N. Mansouri (Syracuse University)

XI

» An Efficient Net Ordering Algorithm for Buffer Insertion 521

H. R. Kheirabadi, M. S. Zamani (Amirkabir University ofTechnology)

a Address Generation for Nanowire Decoders 525

J. Wang, M.-Y. Kao, H. Zhou (Northwestern University)

Keynote Talk 5 • 2:45 - 3:30 p.m.

• Low-Voltage Limitations of Deep-Sub-100-nm CMOS LSIs —View of Memory Designers 529

K. Itoh, M. Yamaoka, T. Kawahara (Hitachi, Ltd.)

Session 6A: Arithmetic and Coding • 3:30 - 5:10 p.m.

8 Efficient Pipelining for Modular Multiplication Architectures in Prime Fields 534

N. Mentens, K. Sakiyama, B. Preneel, I. Verbauwhede (Katholieke Universiteit Leuven)

8 Design of a Versatile and Cost-Effective Hybrid Floating-Point/LNS Arithmetic Processor 540

C. Chen (Feng Chia University), P. Chow (University ofToronto)

8 Multi-Segment GF(2m) Multiplication and its Application to Elliptic Curve Cryptography 546

D.-H. Lee, J.-S. Oh (Kyungpook National University)

Session 6B: Routing and Buffer Insertion • 3:30 - 5:10 p.m.

8 Floorplan Repair Using Dynamic Whitespace Management 552

K. Vorwerk, A. Kennings, D. T. Chen (University ofWaterloo), L. Behjat (University ofCalgary)

8 Improved Timing Closure by Early Buffer Planning in Floor-Placement Design Flow 558

A, Jahanian (IslamicAzad University), M. S. Zamani (Amirkabir University ofTechnology)

8 An Effective Buffer Planning Algorithm for IP Based Fixed-Outline SOC Placement 564

0. He, S. Dong, J. Bian, Y. Ma, X. Hong (Tsinghua University)

8 New Timing and Routability Driven Placement Algorithms for FPGA Synthesis 570

Y. Zhuo, H. Li (University ofNorth Texas), Q, Zhou, Y. Cai, X. Hong (Tsinghua University)

Session 6C: Power Estimation and Modeling • 3:30 - 5:10 p.m.

8 RT-Level Vector Selection for Realistic Peak Power Simulation 576

C.-C. Weng, C.-S. Yang S.-Y. Huang (National Tsing-Hua University)

8 A Fast Clock Scheduling for Peak Power Reduction in LSI 582

Y. Takahashi, Y. Kohira, A. Takahashi (Tokyo Institute ofTechnology)

8 A Path Based Modeling Approach for Dynamic Power Estimation 588

P. Agrawal (Indian Institute ofTechnology Kharagpur),S. R. STG, A. N. Oke, S. Vijay (Intel Technology (I)(P) Ltd.)

8 Software Power Estimation using IPI (Inter-Prefetch Interval) Power Model

for Advanced Off-the-Shelf Processor 594K. Kang, J. Kim, H. Shim, C.-M. Kyung (Korea Advanced Institute ofScience and Technology)

Keynote Talk 6 • 5:30 - 6:15 p.m.

8 Future Trends for Wireless Communication Frontends in Nanometer CMOS 600

G. G. E. Gielen (Katholieke Universiteit Leuven)

Author Index 606

Xll