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ACiD Summer School 2002 Balsa Tutorial: - 1
Build a better life with Balsa
A Hands-on Tutorial SessionAndrew Bardsley
John BainbridgeAmulet Group, Department of Computer Science,
University of Manchester, UK
ACiD Summer School 2002 Balsa Tutorial: - 2
Balsa Tutorials
Async 2000 (Eilat)• Concentrated on language aspects• Xilinx implementation of calculator
Async 2002 (Manchester)• Larger exercise (SSEM) • Standard cell implementations
This tutorial• Language and Handshake Circuits• Much larger exercise (Spamulet0)• Buy the book - ISBN 0-792-37613-7
ACiD Summer School 2002 Balsa Tutorial: - 3
Aims of this tutorial
To show Balsa in a large(ish) example• Simulate that example• Modify its description (?)
Not including:• Detailed examination Handshake Circuits• Synthesis to netlists• Implementation details
ACiD Summer School 2002 Balsa Tutorial: - 4
Session Schedule
Brief overview of the Balsa system Language introduction
• hands-on examples• “Shift Registers”: small pipelines
Either:• Modify a processor description (add new
instructions and simulate)• Read some Balsa examples and try a
simpler example (Rotate Right)
ACiD Summer School 2002 Balsa Tutorial: - 5
The Balsa TeamDoug EdwardsDoug EdwardsTeam LeaderTeam Leader
Luis PlanaLuis PlanaDual RailDual RailBack-endBack-end
Andrew BardsleyAndrew BardsleyChief Architect/ImplementerChief Architect/Implementer
Will TomsWill Toms1-of-4 Back-end1-of-4 Back-end
Lilian JaninLilian Janinbalsa-mgr/LARDbalsa-mgr/LARD
ACiD Summer School 2002 Balsa Tutorial: - 6
Balsa Requirements
Freely available• ftp://ftp.cs.man.ac.uk/pub/amulet/balsa/• http://www.cs.man.ac.uk/amulet/• not all back-ends available
OS requirements:• Linux• Sun Solaris 7-8 (today’s platform)• MacOS X (+ X11R6 …)
ACiD Summer School 2002 Balsa Tutorial: - 7
ACiD Summer School 2002 Balsa Tutorial: - 8
Front EndFront End
ACiD Summer School 2002 Balsa Tutorial: - 9
ACiD Summer School 2002 Balsa Tutorial: - 10
Compass DACompass DARouteRoute
ACiD Summer School 2002 Balsa Tutorial: - 11
ACiD Summer School 2002 Balsa Tutorial: - 12
XilinxXilinxrouteroute
ACiD Summer School 2002 Balsa Tutorial: - 13
top level relies ontop level relies onViewlogic PowerviewViewlogic Powerview
ACiD Summer School 2002 Balsa Tutorial: - 14
CadenceCadencerouteroute
ACiD Summer School 2002 Balsa Tutorial: - 15
ACiD Summer School 2002 Balsa Tutorial: - 16
Other Balsa Work
Burst-mode resynthesis• Tibi Chelcea & Steve Nowick
Faster LARD/Balsa simulation• Lilian Janin (x50 speed up)
Datapath compilation optimisation• Andrew Bardsley
Complete Amulet implementation - SPA1 - Synthesised ARM v5T core• Peter Riocreux, Luis Plana et al.
ACiD Summer School 2002 Balsa Tutorial: - 17
Proven Balsa Synthesis- DMA Controller for DRACO
Balsa SynthesisedBalsa SynthesisedDMA ControllerDMA Controller
ACiD Summer School 2002 Balsa Tutorial: - 18
DMA Controller Layout
ACiD Summer School 2002 Balsa Tutorial: - 19
What is Balsa?
Language for synthesising large async circuits & systems
CSP/OCCAM background Tangram-like
• based on Tangram compilation function• compiles to a small, parameterisable, set
of handshake components• origins: ESPRIT 6143 EXACT project
ACiD Summer School 2002 Balsa Tutorial: - 20
Handshake circuits – 1
Components communicate along handshake channels
Channels connect to ports on components
Ports have:• Type• Direction• Sense
name
ACiD Summer School 2002 Balsa Tutorial: - 21
Handshake Circuits – 2
Port type determines the number of data wires• no data wires = control only port!
Port direction is input, output or control only (called sync)
Port sense• Active: initiate transfers (source the req)• Passive: respond to requests (… the ack)
ACiD Summer School 2002 Balsa Tutorial: - 22
Balsa Language Features
Data types based on sequence of bits• Arrays and records are bit-based• Element extraction is by array slicing• Strict data typing
Structural iteration Arrayed channels Parameterised, recursively expanded
procedures
ACiD Summer School 2002 Balsa Tutorial: - 23
Balsa Language Features
Enclosed selection semantics• Allows passive ported circuits• Allows push (micropipeline-style) circuits• Allows unbuffered (latch-free) circuits
ACiD Summer School 2002 Balsa Tutorial: - 24
Example: Single Place Buffer
import [balsa.types.basic]
type word is 16 bits
procedure buffer (input i : word; output o : word) is
variable x : word
begin
loop
i -> x ; -- Input communication
o <- x -- Output communication
end
end
ACiD Summer School 2002 Balsa Tutorial: - 25
Example: Single Place Buffer
import [balsa.types.basic]
type word is 16 bits
procedure buffer (input i : word; output o : word) is
variable x : word
begin
loop
i -> x ; -- Input communication
o <- x -- Output communication
end
end
librarymechanismtype declaration
channel declarationsprocedure
definitionimplies latch
repeat forever
output local variable xto output channel
read input channel intolocal variable x
sequential operation
ACiD Summer School 2002 Balsa Tutorial: - 26
Buffer Handshake Circuit
Single-place buffer
#
x T
;
Ti o
activationchannel
repeater
sequencer
variable
transferrer
ACiD Summer School 2002 Balsa Tutorial: - 27
#
Buffer Handshake Circuit
Single-place buffer
Repeater is activated
x T
;
Ti o
ACiD Summer School 2002 Balsa Tutorial: - 28
;
#
Buffer Handshake Circuit
Single-place buffer
Sequencer handshakes to left transferrer
x TTi o
ACiD Summer School 2002 Balsa Tutorial: - 29
;
#
Buffer Handshake Circuit
Single-place buffer
Transferrer requests data from environment
x TTi o
ACiD Summer School 2002 Balsa Tutorial: - 30
x
;
#
Buffer Handshake Circuit
Single-place buffer
Data transferred to variable x
TTi o
ACiD Summer School 2002 Balsa Tutorial: - 31
x
;
#
Buffer Handshake Circuit
Single-place buffer
Variable handshake completes
TTi o
ACiD Summer School 2002 Balsa Tutorial: - 32
x
;
#
Buffer Handshake Circuit
Single-place buffer
Transferrer handshake completes to environment
TTi o
ACiD Summer School 2002 Balsa Tutorial: - 33
x
;
#
Buffer Handshake Circuit
Single-place buffer
Transferrer handshake completes
TTi o
ACiD Summer School 2002 Balsa Tutorial: - 34
x
;
#
Buffer Handshake Circuit
Single-place buffer
Sequencer handshakes to right transferrer
TTi o
ACiD Summer School 2002 Balsa Tutorial: - 35
x
;
#
Buffer Handshake Circuit
Single-place buffer
Transferrer reads variable
TTi o
ACiD Summer School 2002 Balsa Tutorial: - 36
x
;
#
Buffer Handshake Circuit
Single-place buffer
Transferrer outputs to environment
TTi o
ACiD Summer School 2002 Balsa Tutorial: - 37
x
;
#
Buffer Handshake Circuit
Single-place buffer
Sequencer initiated handshakes complete
TTi o
ACiD Summer School 2002 Balsa Tutorial: - 38
x
;
#
Buffer Handshake Circuit
Single-place buffer
Sequencer completes its activation handshake
TTi o
ACiD Summer School 2002 Balsa Tutorial: - 39
Buffer Handshake Circuit
Single-place buffer
Repeater initiates another transfer, repeat
x
;
#
TTi o
ACiD Summer School 2002 Balsa Tutorial: - 40
Example Handshake Component
Handshake definition of repeater (Loop)Loop(a,b) = (a: #[b])
= (a: #[b;b])
= (ar: #[br ; ba ; br ; ba])
ba
brar
aa
ACiD Summer School 2002 Balsa Tutorial: - 41
Example Handshake Component
Case component (single-rail)
data “n” bits wide
true/complement lines:dual-rail expansion
1 hot encoding
ACiD Summer School 2002 Balsa Tutorial: - 42
Compilation Tools
balsa-c• compiles Balsa programs to Breeze• includes other Breeze definition files
– Breeze is a handshake -circuit netlist format– acts as a library format for within Balsa
balsa-netlist• produces an appropriate netlist from a
compiled Balsa program– technology specific options
ACiD Summer School 2002 Balsa Tutorial: - 43
Simulation Tools
breeze2lard• produces a LARD simulation file
various LARD utilities• mainly hidden within the Makefile by
balsa-md
ACiD Summer School 2002 Balsa Tutorial: - 44
Utilitity Tools
breeze2ps• creates a PostScript HC graph
breeze-cost• enumerates the handshake circuits used
and gives an approximate area cost balsa-md
• automatic Makefile maker balsa-mgr
• GUI interface to balsa-md
ACiD Summer School 2002 Balsa Tutorial: - 45
Exercise: Single Stage Shift Register
Objective: introduction to balsa-mgr
cd ~/Balsa/shift-reg balsa-mgr &
• create new project: Project -> New
• add SRA1.balsa to project
ACiD Summer School 2002 Balsa Tutorial: - 46
create new projectcreate new project
Creating a Project
ACiD Summer School 2002 Balsa Tutorial: - 47
set nameset name
Set Project Name
ACiD Summer School 2002 Balsa Tutorial: - 48
Add FilesAdd Files
Adding Files
ACiD Summer School 2002 Balsa Tutorial: - 49
pick file(s)pick file(s)
Choosing Files
ACiD Summer School 2002 Balsa Tutorial: - 50
File list paneFile list pane edit paneedit pane
usual iconsusual icons
Project Window
ACiD Summer School 2002 Balsa Tutorial: - 51
Project Manager
tool-tip help pop-ups for icons editor icon opens the editor defined in: Project -> Environment dialogue• syntax modes for xemacs, elvis, nedit
right-mouse clicking on panes brings up context sensitive menus
Browse the various menus (& pop-ups)
ACiD Summer School 2002 Balsa Tutorial: - 52
Single Stage Shift-Register
-- Single Stage Shift Register SRA1.balsaimport [balsa.types.basic]
procedure SRA1 (input i : byte ; output o : byte) is
variable x : byte
begin
loop
o <- x ;
i -> x
end
end
read before writeread before write
ACiD Summer School 2002 Balsa Tutorial: - 53
Examining the Handshake Circuits
Switch to Makefile pane in balsa-mgr list handshake circuits & their area cost
• click on cost run button view handshake circuit graph
• click on SRA1.ps view button
ACiD Summer School 2002 Balsa Tutorial: - 54
Viewing Cost
click on tabclick on tab
ACiD Summer School 2002 Balsa Tutorial: - 55
make commandsmake commandsidentifiesidentifiesoutput paneoutput pane
list of HCslist of HCs
total costtotal cost
Execution Window
standard error panestandard error pane
standard out panestandard out pane
ACiD Summer School 2002 Balsa Tutorial: - 56
Making Handshake Circuit Graph
ACiD Summer School 2002 Balsa Tutorial: - 57
repeaterrepeater
sequencersequencer
transferrerstransferrers
registerregister
internalinternalchannel nameschannel names
I/O portsI/O ports
ACiD Summer School 2002 Balsa Tutorial: - 58
Exercise:n-place Shift Register
Objective: illustration of composition, structural iteration and simulation.
specify an 8-place shift register• add SRA8.balsa to project• ensure SRA8.balsa is selected• click on breeze compile button in
Makefile pane• select add test fixture from right-click
pop-up
See KvB: “Handshake Circuits”See KvB: “Handshake Circuits”
ACiD Summer School 2002 Balsa Tutorial: - 59
Adding SRA8
ACiD Summer School 2002 Balsa Tutorial: - 60
SRA8 Code
-- Multistage Shift Register SRA8.balsaimport [balsa.types.basic]import [SRA1]
procedure SRA8 (input i : byte; output o : byte) is constant n = 8 array 1..n-1 of channel c : bytebegin SRA1 (i, c[1]) || SRA1 (c[n-1], o) || for || j in 1 .. n-2 then SRA1 (c[j], c[j+1]) endend
ACiD Summer School 2002 Balsa Tutorial: - 61
SRA8 Code
-- Multistage Shift Register SRA8.balsaimport [balsa.types.basic]import [SRA1]
procedure SRA8 (input i : byte; output o : byte) is constant n = 8 array 1..n-1 of channel c : bytebegin SRA1 (i, c[1]) || SRA1 (c[n-1], o) || for || j in 1 .. n-2 then SRA1 (c[j], c[j+1]) endend
define a constantdefine a constant
internalinternalchannel arraychannel array
parallelparallelcompositioncomposition
structuralstructuraliterationiteration
ACiD Summer School 2002 Balsa Tutorial: - 62
Structure of Circuit
SRA8SRA8 SRA8SRA8 SRA8SRA8 SRA8SRA8……..
channel ichannel i channel ochannel o
channel c[1]channel c[1] channel c[n-1]channel c[n-1]
channel c[2]channel c[2] channel c[n-2]channel c[n-2]
ACiD Summer School 2002 Balsa Tutorial: - 63
SRA8 Code
-- Multistage Shift Register SRA8.balsaimport [balsa.types.basic]import [SRA1]
procedure SRA8 (input i : byte; output o : byte) is constant n = 8 array 1..n-1 of channel c : bytebegin SRA1 (i, c[1]) || SRA1 (c[n-1], o) || for || j in 1 .. n-2 then SRA1 (c[j], c[j+1]) endend
ACiD Summer School 2002 Balsa Tutorial: - 64
Exercise:Hierarchical vs Flattened views
Check the cost of SRA8 and view the handshake circuit
Change to flattened compilation• Project -> Project Options -> Flattened Compilation
Recheck the cost of SRA8 and view the handshake circuit again• Flattened compilation gives “true” cost
ACiD Summer School 2002 Balsa Tutorial: - 65
AddingTest Fixture
right clickright clickpop-uppop-up
ACiD Summer School 2002 Balsa Tutorial: - 66
Test Options Pane
set inputset inputfilename to: datafilename to: data
ACiD Summer School 2002 Balsa Tutorial: - 67
Running LARD Simulations
text-onlytext-onlysimulationsimulation
channel-viewerchannel-viewersimulationsimulation
ACiD Summer School 2002 Balsa Tutorial: - 68
Simulation Results (Text)
empty values readempty values readthen input datathen input data
ACiD Summer School 2002 Balsa Tutorial: - 69
Lard Channel Viewer -1
ACiD Summer School 2002 Balsa Tutorial: - 70
Lard Channel Viewer -2
input & outputinput & outputchannelschannels
internalinternalchannelschannels
incompleteincompletehandshakeshandshakes
red = requestred = request
green = ackgreen = ack
data valuesdata valueson channelson channels
zoom buttonszoom buttons
ACiD Summer School 2002 Balsa Tutorial: - 71
Improved Shift-Register Stage
After 1st output last stage is ready for an input: it is vacant• The vacancy propagates backwards
towards the input stage Can not input a new value until vacancy
reaches input stage• poor throughput
Modify SRA1 to include an input and output register
ACiD Summer School 2002 Balsa Tutorial: - 72
Improved Shift-Register Stage
Input channel i to reg x in parallel with outputting y to channel o from reg y
Then assign y to x Register assignment
is: y := x
ii
oo
xx
SRC1SRC1
yy
ACiD Summer School 2002 Balsa Tutorial: - 73
Exercise:Language Level Trade-offs
Write your own SRC1 and SRC8• copy SRA1.balsa to SRC1.balsa and edit
Compare the cost of SRC8 with SRA8(must use flattened compilation)
Compare the behaviours of SRC8 and SRA8
ACiD Summer School 2002 Balsa Tutorial: - 74
Wagging Shift Register: SRW8
SRD1: demux i to o1, o2 alternately SRE1: mux i1, i2 into o alternately Middle SR can be either type A or C
SRA/C3SRA/C3
SRA/C3SRA/C3
xx
yy
xx
yy
ii ooo1o1
o2o2
i1i1
i2i2
SRD1SRD1 SRE1SRE1
ACiD Summer School 2002 Balsa Tutorial: - 75
Exercise:Build a Wagging Shift Register
SRD1• read channel i into register x while writing
register y to channel o1• read channel i into register y while writing
register x to channel o2• repeat
Middle Registers• compose 3 type A or type C register stages
in each half
ACiD Summer School 2002 Balsa Tutorial: - 76
Answers:SRD1
-- Single Stage Shift Register: SRD1.balsa-- DeMuxes data stream for Wagging Shift Registerimport [balsa.types.basic]
procedure SRD1 (input i : byte; output o1, o2 : byte)is variable x, y : bytebegin loop o1 <- x || i -> y; o2 <- y || i -> x endend
ACiD Summer School 2002 Balsa Tutorial: - 77
Answers:SRE1
-- Single Stage Shift Register: SRE1.balsa-- Muxes data streams for Wagging Shift Registerimport [balsa.types.basic]
procedure SRE1 (input i1, i2 : byte; output o : byte)is variable x, y : bytebegin loop o <- x || i1 -> y; o <- y || i2 -> x endend
ACiD Summer School 2002 Balsa Tutorial: - 78
Answers:SRW8
-- multi-Stage Wagging Shift Register SRW8.balsaimport [balsa.types.basic]import [SRD1] import [SRE1] import [SRC1]
procedure SRW8 (input i : byte; output o : byte) is constant n = 8 -- n must be even array 1 .. n/2 of channel c1, c2 : bytebegin SRD1 (i, c1[1], c2[1]) || SRE1 (c1[n/2], c2[n/2], o) || for || j in 1 .. n/2 -1 then SRC1 (c1[j], c1[j+1]) || SRC1 (c2[j], c2[j+1]) endend
ACiD Summer School 2002 Balsa Tutorial: - 79
Spamulet0 - Prototype for SPA1
Subset of ARM instruction set ALU ops, LDR/STR, Branch, Branch
with link (procedure call) implemented Sequential, register based design, DoThis (); DoThat ()
Your task is to add to this description Spamulet0 lacks LDM/STM, MUL, SWI,
Coprocessor I/F, Pipelining, Exceptions, Operating modes
ACiD Summer School 2002 Balsa Tutorial: - 80
The Project File cd ~/Balsa/spamulet0 4 Balsa files, LARD test harness
• types.balsa - type and instruction format records
• alu.balsa - ALU with CC handling• shift.balsa - parameterised shifter• spamulet.balsa - top-level, fetch-
decode-execute loop• test-spamulet.l - LARD test harness
ACiD Summer School 2002 Balsa Tutorial: - 81
Simulation Framework
LARD test harness provides simulated memory loaded from raw memory dump files
Small number of provided examples: hello.s, multiply.s, helloc.c
Memory dumps generated from:• Assembler: .s spamulet-asm .raw• C: .c spamulet-cc .s
ACiD Summer School 2002 Balsa Tutorial: - 82
LDM/STM - Load/Store Multiple
Load and store any of the registers as a block - including the PC!
Commonly used for function arguments, entry register saves and return
ldmdir Rbase!opt, {Ri, Rj, …} stmdir Rbase!opt, {Ri, Rj …} Registers always appear in memory in
the same order with R0 at lowest address, R15 at highest
ACiD Summer School 2002 Balsa Tutorial: - 83
LDM/STM Directions
dir is one of:• ib - increment before• db - decrement before• ia - increment after• da - decrement after
Problems include loading PC last and avoiding overwriting the base register
ACiD Summer School 2002 Balsa Tutorial: - 84
LDM/STM Directions 2
LDM/STM can also be used with “stack addressing”• fa - full ascending (ldmda, stmib)• fd - full descending (ldmia, stmdb)• ea - empty ascending (ldmdb, stmia)• ed - empty descending (ldmib, stmda)
The C compiler generated LDM/STMs with the stack addressing names
ACiD Summer School 2002 Balsa Tutorial: - 85
Instruction Encoding
ACiD Summer School 2002 Balsa Tutorial: - 86
Instruction Encoding – 2
Look at instLdmStm in types.balsa Use: (ir as instLdmStm) to decode
instructions• e.g. (ir as instLdmStm).options.L
is the load(1)/store(0) select bit Option bits very similar to LDR and STR
instructions, read spamulet.balsa
ACiD Summer School 2002 Balsa Tutorial: - 87
Implementation Strategies
Edit spamulet.balsa Use a while loop and a variable to
iterate through the register select bits ((inst as instLdmStm).regs)
Perform memory access using MemoryRead and MemoryWrite
Don’t worry about PC or overwriting the base register yet
ACiD Summer School 2002 Balsa Tutorial: - 88
Some Important InformationInstruction L bit P bit U bit
ldmda/ldmfa 1 0 0
ldmia/ldmfd 1 0 1
ldmdb/ldmea 1 1 0
ldmib/ldmed 1 1 1
stmda/stmed 0 0 0
stmia/stmea 0 0 1
stmdb/stmfd 0 1 0
stmib/stmfa 0 1 1
ACiD Summer School 2002 Balsa Tutorial: - 89
Some Important Information 2
W bit specifies whether the base register is to be written back (W=1) or keep its pre-LDM/STM value (W=0)
The “!” in the mnemonic selects writeback
Ignore the S bit - it’s used for processor mode changes (e.g. ISR returns)
ACiD Summer School 2002 Balsa Tutorial: - 90
Some Important Information 3
To help with debugging, Balsa has the print command
Prints simulation values in LARD Example:
• b <- v1; print “Hello”; b <- v2• print “v1=“, v1, “v2=“, v2
Enjoy
ACiD Summer School 2002 Balsa Tutorial: - 91
Additional Exercises
A choice of advanced design exercises:• A general shifter• A bit population counter
Language Summary in handout + code listings
ACiD Summer School 2002 Balsa Tutorial: - 92
A Balsa Shifter
General shifters required for processors Write a description for a rotate right
function• solution in ror/solution
Alternatively extend the standard solution to other shift functions
ACiD Summer School 2002 Balsa Tutorial: - 93
Structure of a ROR shifter
a local procedure
ACiD Summer School 2002 Balsa Tutorial: - 94
Bit Population Counter
Counting the number of bits that are set to ‘1’ is necessary for ARM’s LDM/STM instructions
Write description for such a unit• solution in popcount/solution
ACiD Summer School 2002 Balsa Tutorial: - 95
Bit Population Counter
ACiD Summer School 2002 Balsa Tutorial: - 96
Login and Account Setup
Login with tpacidXX … Make sure this is your allocated group
account name, not just tpacid02 > /usr/openwin/bin/openwin In a shell window > bash > rmdir balsa > gtar xzf /softs/balsa/examples.tar.gz