ACCUMULATOR BASED 3-WEIGHT PATTERN GENERATION.pptx

8/10/2019 ACCUMULATOR BASED 3-WEIGHT PATTERN GENERATION.pptx

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INTRODUCTION

IDEA OF AN ACCUMULATOR-BASED 3-WEIGHT PATTER

DESIGN METHODOLOGY

ACCUMULATOR CELL

COMPARISONS WITH SCAN-BASED SCHEMES

AN ACCUMULATOR-BASED SCHEME

CONCLUSION


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Pseudorandom built-in self test (BIST) generatorswidely utilized to test integrated circuits and system

The arsenal of pseudo-random generators incl

feedback shift registers (LFSRs), cellular auto

accumulators driven by a constant value.

Cont


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In order to minimize the hardware implementation cost, other

based on multiple weight assignments utilized weights are 0, 1

ABIST is to utilize accumulators for built-in testing (compres

the CUT responses, or generation of test patterns) and has been

to result in low hardware over-head and low impact on the circ

normal operating speed.

The scheme generates test patterns having one of three weight

0, 1, and 0.5 there-fore it can be utilized to drastically reduce t

application time in accumulator-based test pattern generation.


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A typical weight assignment procedure would

separating the test set into two subsets, S1 and S2.

The weight assignments for these subsets is whe

denotes a weight assignment of 0.5, a 1indicateinput is constantly driven by the logic 1 value,

indicates that the input is driven by the logic 0val


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The implementation of the weighted-pattern genera

scheme is based on the full adder truth table. Truth Table Of The Full Adder


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The comparison will be performed with respect to: 1)

hardware overhead and 2) the impact on the timingcharacteristics of the adder of the accumulator.

The hardware overheads are calculated in gate equiva

where an input NAND or NOR accounts for 0.5 gates

inverter accounts for 0.5 gates. For the comparisons of the ripple carry adder imple-m

the adder cell utilized


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Logic is inserted between the scan chain and the CUto fix the outputs to the required weight (0, 0.5, or 1

A number of 3-gate modules is required for every re

weighted input.

For an input CUT and, assuming the availability of tchain, the hardware overhead, apart from the LFSR

generate the pseudorandom inputs and the scan coun

includes a decoding logic.


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COMPARISONS WITH THE SCAN SCHEMESPROPOSED


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The scheme operates in test sessions based on triple

form (S, I, L), where S is the starting value of the

accumulator, I is the increment, and L is he number

the increment is applied before going to the next ses

The average increase in the number of tests is 19%, the average decrease in hardware overhead is 98%.


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COMPARISONS WITH THE SCHEME PROPOSED


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We have presented an accumulator-based 3-weigh

and 1) test-per-clock generation scheme, which ca

utilized to efficiently generate weighted patterns w

altering the structure of the adder.


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ACCUMULATOR BASED 3-WEIGHT PATTERN GENERATION.pptx