AccuCell

Introduction to CellCharacterization

2

Overview

ß Objective of Cell Characterization

ß Digital Design Tools that Use Standard Cell Models

ß Input Data Files Required by Digital Design Tools

ß Types of Standard Cell Libraries

ß Input Views of Circuits – Bridging Analog and Digital

ß Cell Library Attributes

ß Cell Library Model Quality

ß Synopsys Liberty Format (.lib)

ß Characterization of Gates

ß Characterization of Sequential Circuits

3

Summary Slide

ß Objective of Cell Characterization

ß Digital Design Tools That Use Standard Cell Models

ß Input Data Files Required by Digital Design Tools (Generatedby AccuCell)

ß Input Data Files Required by Digital Design Tools (Generatedby Other Tools)

ß Types of Standard Cell Libraries

ß Digital Circuit Representation – Inverter

ß Analog Circuit Description - Inverter

ß Input Views of CircuitsBridging Analog and Digital

ß Static Timing Analysis Use of Liberty Format

ß Cell Library Attributes

ß Measurements

ß Cell Library Model Quality

ß Liberty .lib File Structureß Operating Conditions

ß Cell Attributes in .lib File

ß Datasheet View of AND2

ß Pin Attributes

ß Setting Output Load Limits

ß Delay Modeling Concepts

ß Total Delay Equation

ß Slope Delay

ß Slew Modeling

ß Intrinsic and Transition Delaysß Connect Delay

ß Interconnect Delay

ß Timing Arcs

ß Combinational Timing Arcs

ß Sequential Timing Arcs

ß Timing Arcs Between Single and Multiple Pinsß Three-State Timing Arcs

ß Edge-Sensitive Timing Arcs

ß Preset Arcs

ß Clear Arcs

ß Defining Delay Arcs With Lookup Tables

ß Defining Lookup Table Templates

ß Assigning Values to Lookup Tables

ß Timing Constraints

ß Setup and Hold Constraints

ß Non Sequential Setup and Hold Constraintsß Recovery Timing Constraints

ß Removal Timing Constraints

ß .lib of State Table Flip Flop

ß .lib of Type ff D Flip Flop

ß Components of Power Dissipation

ß Power Modeling

ß State Dependent Leakage Power

ß Modeling Internal Power Lookup Tables

ß Internal Power Calculations

ß Clock Pin Powerß Output Pin Power

ß Power Lookup Tables Descriptions 1D, 2D, 3D

ß Internal Power Table for Cell Output

ß Calculating Switching Power

ß Switching Power Calculations

4

Objective of Cell Characterization

ß Create a set of high quality modelsof a standard cell library thataccurately and efficiently model cellbehavior. This set of models areused by several different digitaldesign tools for different purposes.

5

Digital Design Tools That Use Standard CellModels

ß Synthesis Tools

ß Place and Routing Systems

ß High level Design Language (HDL) Simulators (Verilog andVHDL)

ß Floorplanning Tools

ß Physical Placement tools

ß Static Timing Analysis (STA) tools

ß Power Analysis tools

ß Formal Verification tools

ß Automatic Test Program Generation (ATPG) tools

ß Library Compiler

6

Input Data Files Required by Digital DesignTools (Generated by AccuCell)

ß .lib Technology library source files

ß .v Generated Verilog simulation libraries

ß .vhd Generated VHDL simulation libraries

ß atpg.lib ATPG library

ß .tbench Verilog testbench to compare SPICE to Verilogwith same stimulus

ß .html HTML datasheet

7

Input Data Files Required by Digital DesignTools (Generated by Other Tools)

ß .db Compiled technology libraries in Synopsys internaldatabase format

ß Synopsys Milkyway Files - Abstracts or Bounding Boxes

ß Cadence Encounter Files - Abstracts or Bounding Boxes

ß .LEF

ß .DEF

ß GDS

8

Types of Standard Cell Libraries

ß There are often several cell libraries per semi process thattypically contain 100 to 1,000 cells including:ß Functionsß Gates – inverter, AND, NAND, NOR, XOR, AOI, OAI

ß Flops – Flip flops (D, RS, JK), Latches, Scan Flops, Gated Flops

ß I/O Cells – Input pads, Output pads, Bidirectional Pads, Complex

ß Process Optionsß Mask layer options, gate shrinks, # of metals, special diffusions, thick

metal, multiple oxides

ß Cell Optionsß Drive strengths, sets, resets, scans, substrate ties, antenna diodes

ß Optimized for Addressing Tradeoffs Betweenß High speed, high density, low power, low leakage, low voltage, low

noise

ß Cell Libraries are Produced by Foundries, IP Vendors,Fabless and IDMs

9

Digital Circuit Representation – Inverter

IEEE-1164 Verilog Logic StatesStrength State Value

U UninitializedDriven X UnknownDriven 0 LowDriven 1 High

Z High impedanceResistive W Weak XResistive L Weak 0Resistive H Weak 1

-- Don’t care

Verilog Language Description of Inverternot i1 (out, in); // basic inverternot #(5,3)i1 (out, in); // Rise=5ns, Fall=3ns

Inverter

Rise/FallDiagram

10

Analog Circuit Description - Inverter

Schematic Netlist

Transistor Inverter Schematic Schematic Netlist with Parasitics

*svc_inv.schM3 y a gnd gnd nmos L=0.35u W=4.0uM2 y a vdd vdd pmos L=0.35u W=4.0u.END

*svc_inv.schM3 y a gnd gnd nmos L=0.35u W=4.0uM2 y a vdd vdd pmos L=0.35u W=4.0uC1 …..C2 …..C3 …...END

11

Input Views of CircuitsBridging Analog and Digital

ß Timing back annotationfor Verilog simulator(gate, behavioral) Modelmust work in Verilog-XL,VCS, NCsim, Modelsim,SILOS

ß Methodology haslimitations on accuracy(load based only)

ß STA is preferredmethodology

12

Static Timing Analysis Use of Liberty Format

ß In a standalone flow, STA operates independently ofcharacterization reading both a Verilog netlist and multipletiming libraries in Liberty format. It can also readinterconnect parasitic data in SPF or SDF formats.

13

Cell Library Attributes

ß Pin Typesß direction

ß function

ß Loadsß Capacitive

ß Active

ß Fanout and wire loads

ß Stimulusß PWL for slope

ß Active drivers

ß Indexesß Load

ß Input slope

pin (A) {direction : output ;

function : "X + Y" ;}

lu_table_template(wire_delay_table_template) { variable_1 : fanout_number; variable_2 : fanout_pin_capacitance; variable_3 : driver_slew; index_1 ("1.0 , 3.0"); index_2 ("0.12, 4.24"); index_3 ("0.1, 2.7, 3.12");}lu_table_template(trans_template) { variable_1 : total_output_net_capacitance; index_1 ("0.0, 1.5, 2.0, 2.5");}wire_load("05x05") { resistance : 0 ; capacitance : 1 ; area : 0 ; slope : 0.186 ; fanout_length(1,0.39) ; interconnect_delay(wire_delay_table_template) values("0.00,0.21,0.3", "0.11,0.23,0.41", \ "0.00,0.44,0.57", "0.10 0.3, 0.41");}

14

Measurements

ß Capacitance

ß Thresholds/switching points

ß Rise Time

ß Fall Time

ß Delay (propagation + transition = cell) (i.e. timing arcs)

ß Power ( static state dependent leakage, dynamic, short-circuit, hidden, internal ) (i.e. power arcs)

15

Cell Library Model Quality

ß Accuracy to silicon over the required power supply voltage,load range, input signal slope range

ß Completeness of characterization (state, types[rise/fall],indexes, pins ) – all timing arcs are included

ß Conformance with digital tool format requirements (syntax,units, thresholds)

ß Conformance with digital tool value constraints(monotonicity) and multi-tool timing engine correlation

ß Model Efficiency - speed of execution of model in digital toolthat runs many times on large circuits using generatedmodels

ß Characterization time efficiency – runs once butcharacterizing a single flop can take hours

ß Minimum size of model file - .lib files can become huge,especially with noise data

16

Synopsys Liberty .lib File Structure

ß Structural informationß Describes each cell’s connectivity to

the outside world, including cell,bus, and pin descriptions.

ß Functional informationß Describes the logical function of

every output pin of every cell so thatthe digital design tools can map thelogic of a design to the actualtechnology.

ß Timing informationß Describes the parameters for pin-to-

pin timing relationships and delaycalculation for each cell in thelibrary.

ß Environmental informationß Describes the manufacturing

process, operating temperature,supply voltage variations, anddesign layout, all of which directlyaffect the efficiency of every design.

17

Liberty .lib File Library Level Attributes

library (name) {technology (name) ;/* library-level attributes */delay_model : generic_cmos | table_lookup |

cmos2 | piecewise_cmos | dcm |polynomial ;

bus_naming_style : string ;routing_layers(string);time_unit : unit ;voltage_unit : unit ;current_unit : unit ;pulling_resistance_unit : unit ;capacitive_load_unit(value,unit);leakage_power_unit : unit ;

Defines units for entire library

Default Units

18

Operating Conditions

ß name

ß The name (WCCOM in the example)identifies the set of operatingconditions.

ß process

ß The scaling factor accounts forvariations in the outcome of the actualsemiconductor manufacturing steps.This factor is typically 1.0 for normaloperating conditions.

ß temperature

ß The ambient temperature in which thedesign is to operate.

ß voltage

ß The operating voltage of the design

ß tree_type

ß The definition for the environmentinterconnect model.

ß power_rail

ß The voltage value for a power supply.

19

Cell Attributes in .lib File

ß Structureß The cell, bus, and pin structure that describes each cell’s connection to

the outside world.

ß Functionß The logical function of every output pin of each cell that digital design

tools use to map the logic of a design to the actual technology.

ß Timingß Timing analysis and design optimization information, such as the

parameters for pin-to-pin timing relationships, delay calculations, andtiming constraints for sequential cells.

ß Powerß Modeling for state-dependent and path-dependent power

ß Other parametersß These parameters describe area and design rules.

20

Datasheet View of AND2

ß Correlation between datasheetand .lib representation of a 2input AND gate

21

Pin Attributes

ß directionß Defines the direction of each pin. In the example on the previous page, A and B are

defined as input pins and Z as an output pin.

ß capacitanceß Defines the input pin load (input capacitance) placed on the network. Load units

should be consistent with other capacitance specifications throughout the library.Typical units of measure for capacitance are picofarads and standardized loads.

ß functionß Defines the logic function of an output pin in terms of the cell’s input or inout pins. In

the example, the function of pin Z is defined as the logical AND of pins A and B.

ß timingß Describes timing groups. The timing groups describe the following:

ß - A pin-to-pin delay

ß - A timing constraint such as setup and hold

ß In the example, the timing group for pin Z describes the delays between pin Z andpins A and B.

22

Setting Output Load Limits

ß fanout_loadß Specifies how much to add to the fanout on the net.

ß max_fanoutß Specifies the maximum number of loads a pin can drive.

ß max_transitionß Specifies the maximum rise or fall transition time on an output due to total

capacitive load.

ß max_capacitanceß Specifies the maximum total capacitive load that an output pin can drive.

ß min_fanoutß Specifies the minimum number of loads that a pin can drive.

ß min_capacitanceß Specifies the minimum total capacitive load that an output pin can drive.

23

Delay Modeling Concepts

ß Total Delay Equation

ß Total Delay Scaling

ß Slope Delay

ß Intrinsic Delay

ß Transition Delay

ß Connect Delay

ß Interconnect Delay

ß Delay Calculation Example

24

Total Delay Equation

ß Dtotal = DI + DS + DC + DT

ß DIß Intrinsic delay inherent in the

gate and independent of

ß particular instantiation.

ß DSß Slope delay caused by the

ramp time of the input signal.

ß DCß Connect media delay to an

input pin (wire delay).

ß DTß Transition delay caused by

loading of the output pin.

25

Total Delay Scaling

ß When calculating total delay, the digital tool scales eachparameter of Dtotal individually.

ß Each component of the total delay has its own globalparameters to model the effects on the nominal case ofvariations in process, temperature, and voltage.

*Total Delay is typically measured

from 50% to 50%, regardless

of where transition thresholds are set

26

Slope Delay

ß The slope delay of an element (DS) is the incremental time delay caused by slowlychanging input signals. This is not used by AccuCell.

ß In some technologies, this delay is a strong function of the ramp time.

ß D is calculated with the transition delay at the previous output pin, plus a slopesensitivity factor, as shown here:

ß This equation calculates both the rise and fall delays. Where applicable, usethe “rise” parameter to calculate the rise delay and the “fall” parameter tocalculate the fall delay.

ß DS

ß Transition delay is calculated at the previous stage of logic. Therefore, thecalculation of DS enforces a global order on local analysis.

ß SSß Slope sensitivity factor. This factor accounts for the time during which the input

voltage begins to rise but has not reached the threshold level at which channelconduction begins. The attributes that define it in the timing group of thedriving pin are slope_rise and slope_fall.

ß DT(prevstage)ß The transition delay calculated at the previous output pin.

27

Slew Modeling

ß Slew is the time it takes for thevoltage value to fall or risebetween two designatedthreshold points on an input,an output, or a bidirectionalport.

ß The designated thresholdpoints must fall within avoltage falling from 1 to 0 orrising from 0 to 1.

28

Intrinsic and Transition Delays

ß Intrinsic Delayß The intrinsic delay of a circuit element (DI) is the portion of the

total delay that is independent of the circuit element’s usage. Thisportion is the fixed (or zero load) delay from the input pin to theoutput pin of a circuit element.

ß Transition Delayß The transition delay of a circuit element is the time it takes the

driving pin to change state. The transition time of the output pinon a net is a function of the capacitance of all pins on the net andthe capacitance of the interconnect network that ties the pinstogether.ß This equation calculates the rise and fall delays.

29

Connect Delay

ß The connect delay of anelement (DC) is the timeit takes the voltage atan input pin to chargeafter the driving outputpin has made atransition.

ß This delay is alsoknown as time-of-flightdelay, which is the timeit takes a waveform totravel along a wire.

30

Interconnect Delay

ß Interconnect delay isdefined as the delaycaused by connect delayand fanout. It is calculatedas the sum of DT and DC.

ß Include the capacitanceattribute in the pin group ofthe input pin.

ß Give zero capacitance tothe pin group of the outputpin.

ß Resistance is attributedentirely to the output pin.

31

Timing Arcs

ß Timing arcs can be delay arcs or constraint arcs.ß Each timing arc has a startpoint and an endpoint.ß The startpoint can be an input, output, or inout pin.ß The endpoint is always an output pin or an inout pin.ß The only exception is a constraint timing arc, such as a setup,

hold, recovery or removal constraint between two input pins.ß related_pinß This attribute defines the pin or pins representing the startpoint of a timing

arc.

ß All delay information in a library refers to an input-to-output pinpair or an output-to-output pin pair defined as:ß intrinsic delay

ß The fixed delay from input to output pins.

ß transition delayß The time it takes the driving pin to change state. Transition delay attributes

represent the resistance encountered in making logic transitions.

ß slope sensitivityß The incremental time delay due to slow change of input signals.

32

Combinational Timing Arcs

ß A combinational timing arc describes the timingcharacteristics of a combinational element. The timing arc isattached to an output pin, and the related pin is either aninput or an output. AccuCell does not use these.

ß A combinational timing arc is of one of the following types:ß combinational

ß combinational_rise

ß combinational_fall

ß three_state_disable

ß three_state_disable_rise

ß three_state_disable_fall

ß three_state_enable

ß three_state_enable_rise

ß three_state_enable_fall

AND Gate With Timing Arc

XOR Gate With State-Dependent Timing Arc

33

Sequential Timing Arcs

ß A sequential timing arc is of one of the following types:ß Edge-sensitive (rising_edge or falling_edge)

ß Preset or clear

ß Setup or hold (setup_rising, setup_falling, hold_rising, orhold_falling)

ß Nonsequential setup or hold (non_seq_setup_rising,non_seq_setup_falling, non_seq_hold_rising,non_seq_hold_falling)

ß • Recovery or removal (recovery_rising, recovery_falling,removal_rising, or removal_falling)

ß • No change (nochange_high_high, nochange_high_low,nochange_low_high, nochange_low_low)

34

Timing Arcs Between Single and Multiple Pins

Pin and a Single Related Pin Pin and Multiple Related Pins

*Timing Arcs can also be between pins, groups, and busses

35

Three-State Timing Arcs

ß Assign related_pin to the enable pin of the three-statefunction.

ß Define the Z-to-1 propagation time with the intrinsic_risestatement.

ß Define the Z-to-0 propagation time with the intrinsic_fallstatement.

ß Include the timing_type : three_state_enable statement.

36

Edge-Sensitive Timing Arcs

ß Edge-sensitive timing arcs, such as the arc from the clockon a flipflop, are identified by the following values of thetiming_type attribute in the timing group.

ß rising_edgeß Identifies a timing arc whose output pin is sensitive to a rising

signal at the input pin.

ß falling_edgeß Identifies a timing arc whose output pin is sensitive to a falling

signal at the input pin.

ß These arcs are path-traced; the path tracer propagates onlythe active edge (rise or fall) path values along the timingarc.

37

Preset Arcs

ß Selectß timing_type : preset;ß timing_sense :

ß positive_unateß Indicates that the rise arrival time of the arc’s source pin is used to

calculate the arc’s delay. This calculation produces the rise arrival time onthe arc’s endpoint pin. In the case of slope delays, the source pin’s risetransition time is added to the arc’s delay. The source pin is active-high.

ß negative_unateß Indicates that the fall arrival time of the arc’s source pin is used to

calculate the arc’s delay. This calculation produces the rise arrival time onthe arc’s endpoint pin. In the case of slope delays, the source pin’s falltransition time is added to the arc’s delay. The source pin is active-low.

ß non_unateß Indicates that the maximum of the rise and fall arrival times of the arc’s

source pin is used to calculate the arc’s delay. This calculation producesthe maximum arrival time on the arc’s endpoint pin. In the case of slopedelays, the maximum of the source pin’s rise and fall transition times isadded to the arc’s delay.

38

Clear Arcs

ß Clear arcs affect only the fall arrival time of the arc’s endpoint pin. A cleararc means that you are asserting a logic 0 on the output pin when thedesignated related_pin is asserted.

ß Selectß timing_type : clear;ß timing_sense :

ß positive_unateß Indicates that the fall arrival time of the arc’s source pin is used to calculate the

arc’s delay. This calculation produces the fall arrival time on the arc’s endpoint pin.In the case of slope delays, the source pin’s fall transition time is added to the arc’sdelay. The source pin is active-low.

ß negative_unateß Indicates that the rise arrival time of the arc’s source pin is used to calculate the

arc’s delay. This calculation produces the fall arrival time on the arc’s endpoint pin.In the case of slope delays, the source pin’s rise transition time is added to the arc’sdelay. The source pin is active-high.

ß non_unateß Indicates that the maximum of the rise and fall arrival times of the arc’s source pin

is used in calculating the arc’s delay. This calculation produces the maximum fallarrival time on the arc’s endpoint pin. In the case of slope delays, the maximum ofthe source pin’s rise and fall transition times is added to the arc’s delay.

39

ß Transition time is the time it takes for an output signal tomake a transition between the high and low logic states.With nonlinear delay models, it is computed by table lookupand interpolation. Transition delay is a function ofcapacitance at the output pin and input transition time.

ß Group attributes:ß cell_rise

ß cell_fall

ß rise_propagation

ß fall_propagation

ß retaining_rise

ß retaining_fall

ß retain_rise_slew

ß retain_fall_slew

Defining Delay Arcs With Lookup Tables

To specify cell delay independently of transition delay,

use one of these timing group attributes as your lookup table:

To specify transition delay as a term in the total cell delay,use one of these timing group attributes as your lookup table

40

Defining Lookup Table Templates

ß CMOS Nonlinear Delay Model isspecified by a one or twodimensional table of delayvalues dependent on input nettransition and outputcapacitance

41

Assigning Values to Lookup Tables

ß Referring to tablesdefined in previousslide

ß Pin a is twodimensional 4X4

ß Pin b is onedimensional X4

ß These timing valuesare the results ofSmartSpice.MEASUREstatements withinAccuCell

42

Timing Constraints

ß setup and hold arcsß Set these constraints to ensure that a data signal has stabilized,

before latching its value.

ß recovery and removal arcsß Use the recovery timing arc and the removal timing arc for

asynchronous control pins such as clear and preset.

ß skewß This is another constraint that the VHDL library generator uses for

simulation.

ß You can also set state-dependent and conditionalconstraints.

43

Setup and Hold Constraints

Setup and Hold Constraints for Rising-Edge-Triggered Flip-Flop

Setup and Hold Constraints for High-Enable Latch

44

Non Sequential Setup and Hold Constraints

ß In some nonsequential cells,the setup and hold timingconstraints are specified onthe data pin with a nonclockpin as the related pin.

ß The signal of a pin must bestable for a specified period oftime before and after anotherpin of the same cell rangestate for the cell to function asexpected.

Nonsequential Setup and Hold Constraints

45

Recovery Timing Constraints

Recovery Timing Constraint for a Rising-Edge-Triggered Flip-Flop

Recovery Timing Constraint for a Low-Enable Latch

46

Removal Timing Constraints

ß Removal Constraintß This constraint is also known as the

asynchronous control signal holdtime.

ß The removal constraint describesthe minimum allowable timebetween the active edge of the clockpin while the asynchronous pin isactive and the inactive edge of thesame asynchronous control pin

ß No-Change Timing Constraintsß You can model no-change timing

checks to use in static timingverification during synthesis.

ß A no-change timing check checks aconstrained signal against a level-sensitive related signal.

ß The constrained signal must remainstable during an established setupperiod, for the width of the relatedpulse, and during an establishedhold period.

Timing Diagram for Removal Constraint

No-Change Timing Check

47

.lib of State Table Flip Flop

48

.lib of Type ff D Flip Flop

ß The ff group statementreplaces the statetable groupstatement

ß The function attribute, ratherthan the internal_nodeattribute, defines the outputpin’s function

ß The D flip-flop defines twovariables, IQ and IQN

ß The next_state equationdetermines the value of IQafter the next clocked_ontransition.

ß In this example IQ is assignedthe value of the D input.

49

Components of Power Dissipation

50

Power Modeling

ß Leakage Powerß Leakage power is the static (or quiescent) power dissipated when a gate

is not switching.

ß Short-Circuit Powerß Short-circuit or internal power is the power dissipated whenever a pin

makes a transition. This can be handled in two ways:ß Include the effect of the output capacitance in the internal_power group

(defined in a pin group within a cell group), which gives the output pins zerocapacitance

ß Give the output pins a real capacitance, which causes them to be included inthe switching power, and model only the short-circuit power as the cell’sinternal power (in the internal_power group)

ß Switching Powerß Switching (or interconnect) power is the power dissipated in the circuit as

a result of a logical transition of the capacitive load. Switching power(along with internal power) is used to compute the design’s total dynamicpower dissipation.

51

State Dependent Leakage Power

ß Leakage power isstate dependentbased on input pinstate values

52

Modeling Internal Power Lookup Tables

ß You should measure the energy dissipated by varying either input voltagetransition or output load while holding the other constant.

ß Because a table indexed by T input transition times and C output loadcapacitances has TxC entries, the cell’s internal power must becharacterized TxC times, once for each input transition time and outputload capacitance combination.

ß For example, if internal power will be modeled by use of a 3x3 table at theoutput of the cell, the design will have 9 input voltage transitions—outputload combinations where energy dissipation must be measured.

ß The library group supports a one-, two-, or three-dimensional internalpower lookup table indexed by the total output load capacitances (bestmodel), the input transition time, or both.

ß NOTE: The input pin power is added to the output pinpower. When you model the library, avoid double counting.

53

Modeling Internal Power Lookup Tables

Power is calculated by integrating energy

54

Internal Power Calculations

ß To calculate the internal power for cell U1, use the followingequation:

ß PIntß Total internal power for the cell.

ß Eß Internal energy for the pin.

ß AFß Activity factor.

ß Accurate sequential modeling requires a separate table forthe clock and for the output pin the clock controls. The twotables are used to ensure that clock pin power and outputpower are accounted for separately, because a clock pinoften toggles without causing any observable state changeon the output pin.

55

Clock Pin Power

ß This energy is characterized by simulation of a single fullcycle (one rise transition and one fall transition) of the clock,with no transition at the output and input pins. A one-dimensional internal power table indexed by input transitiontime should be attached to the clock pin. Total energydissipated in the cell during this simulation is measured. Ifseparate rise and fall power modeling is not used, theenergy measured must be divided by 2 to get the energydissipated by the clock pin transition, because themeasurement is done for two transitions of the clock.

ß Clk_Pin_Energy = Clk_Total / 2

ß Add Clk_Pin_Energy as an entry indexed by input transitiontime in the one-dimensional internal power table attached tothe clock pin.

56

Output Pin Power

ß This power is characterized by simulation of two full cyclesof the clock, with two rise and fall transitions at the output. Atwodimensional internal power table should be attached tothe output pin. Total energy dissipated in the cell during thetwo-full-cycle simulation (Out_total) is measured. If separaterise and fall power modeling is not used, the energymeasured must be divided by 2, because the measurementis done for two transitions.

ß Output_Pin_Energy = (Out_total)/2 - 2*(Clk_Pin_Energy)

57

Power Lookup Tables Descriptions 1D, 2D, 3D

ß The example at left showsshows fourpower_lut_template groupsthat have one-, two-, orthree-dimensionaltemplates.

ß The index values are listsof floating-point numbersgreater than or equal to 0.0.

ß The values in the list mustbe in increasing order.

ß The number of floating-point numbers in theindexes determines thesize of each dimension

58

Internal Power Table for Cell Output

59

Calculating Switching Power

ß Switching (or interconnect) power is the power dissipated in the circuit asa result of a logical transition of the capacitive load

ß With internal power, switching power is used to compute the design’stotal dynamic power dissipation.

ß Switching power information is a function of a net’s capacitive loading,associated clock frequency, and the supply voltage level of the design.

ß An explicit units attribute is not required for switching power, because theunits are implicitly determined by the units of the voltage, time, andcapacitance attributes.

60

Switching Power Calculations

ß For a single net with a total load of 100 femtofarad, a togglerate of two transitions every 100 ns, and a supply voltage of5 volts, the calculation of the net’s power dissipation is:

ß TRß Toggle rate (number of toggles per unit of time).

ß CLoadß Capacitive load of each net.

61

Syllabus for Advanced Cell Characterization

ß Review of Introduction to Cell Characterization

ß Latches

ß Scan Flop

ß Gated Clocks

ß Definition of I/O cell terms

ß Example of I/O Cell

ß Active Loads

ß Active Drivers

ß Derating factors, K factors

ß Verilog Timing Checks

ß Noise Considerations (CCS, ECSM)