-1-May 30 – June 2, 2006

56th ECTC – San Diego – May/June 2006

AC Coupled Interconnect using Buried Bumps for Laminated Organic Packages

J. Wilson1, L. Luo1, J. Xu1, S. Mick1, E. Erickson1, H. Su1, B. Chan2, H. Lin2, P. Franzon1

1North Carolina State University, Raleigh, NC2Endicott Interconnect Technologies, Endicott , NY

NC STATE UNIVERSITY

-2-May 30 – June 2, 2006

Agenda / Outline / Overview

Why ACCI?

Demonstrations

Organic Packaging

Conclusions

Acknowledgements

-3-May 30 – June 2, 2006

AC Coupled Interconnect

Form signal connection with series capacitor -half-plate on package and half-plate on-chipForm DC connections with buried solder bumps

Chip 1 Chip 2

CouplingCapacitor

CouplingCapacitor

Transmitter Receiver

Interconnect

Chip 1 Chip 2

CouplingCapacitor

CouplingCapacitor

Transmitter Receiver

DifferentialInterconnect

-4-May 30 – June 2, 2006

Why ACCI?

Compliant Interface• Small signal pad pitch (65 um)• High pin count. e.g. 4,800 power/ground, 4,200 signal

on an 18x18 mm chip • Larger Chip Size possible

Power = 12 mW per channel @ 6 Gbps• About 3x less than conventional signaling

Circuit area ~ 5x less than conventionalReduced ESD protection neededHigh Signaling Bandwidth

-5-May 30 – June 2, 2006

Alternative Technologies

Flip-chip Solder Bump• Difficult to scale reliably below

150 μm pitch • Limited neutral distance

Potential replacements for solder bump• Conducting adhesives• Pillar processes• Compliant spring systems• Reliability or cost concerns!

MCNC

GaTech

AdvanPack

-6-May 30 – June 2, 2006

Substrate

Chip

ACCI chip and substrate

Buried solder bumps

ACCI coupling capacitor and buried solder bumpsCoupling capacitor

MCM-D fabricated and assembled by MCNC (RTI)

MCM-D Demonstration

-7-May 30 – June 2, 2006

36 Gbps Circuit DemonstrationUsing on-chip capacitors (6 channels @ 6 Gbps)_

Die photo

Annotation for I/Os and TRXs

used in this paper

-8-May 30 – June 2, 2006

(a)

(b)

Differential signal

Single ended signals +

Differential Eye

Single ended signals -

Single ended Eyes +

Single ended Eyes -

Measured RX output at 6Gb/s operation

-9-May 30 – June 2, 2006

Basics of Pulse Signaling

Frequency

Pulse RX (latch)

Bit-rate/2Frequency

Equalized Channel

Bit-rate/2Frequency

ACCI Channel

Bit-rate/2

ACCI Channel

Frequency

Pulse RX (latch)

Bit-rate/2Frequency

Equalized Channel

Bit-rate/2Frequency

ACCI Channel

Bit-rate/2Frequency

Pulse RX (latch)

Bit-rate/2Frequency

Equalized Channel

Bit-rate/2Frequency

Equalized Channel

Bit-rate/2Frequency

ACCI Channel

Bit-rate/2

ACCI ChannelACCI Channel

-10-May 30 – June 2, 2006

20 Gbps ACCI Channel (Simulation)

0.7 V Vdd

20Gb/s waves

At T-line inputAt T-line outputAt RX input

80fF CC size10cm T-line

-11-May 30 – June 2, 2006

Signal Integrity

Robustness similar to typical backplane serial link• Demonstrated BER <10-12

• Crosstalk, SSN, Reflection noise at stubs all manageable (EPEP05)

-12-May 30 – June 2, 2006

Laminate Packaging

Potential Benefits:• Cost-effective, high-pin-count package that can

support large die Challenges:• Coping with larger capacitor gaps

• And greater variation• Accommodating Buried Bump• Incorporating Underfill

• Standard Capillary flow Underfill• Process flow and Integration

-13-May 30 – June 2, 2006

General Concept

Package

Chip

DC bumps with stress-relief underfill

AC I/O with High-K material

-14-May 30 – June 2, 2006

General Concept

Underfill inletDC bumpsCommon Trench

AC I/O

-15-May 30 – June 2, 2006

Modified HyperBGA

Build-Up

EmbeddedResistorStandard HyperBGA

-16-May 30 – June 2, 2006

28 x 28 mm Chip Layout

6,064 solder bumps- 22x22 mm- 250 um pitch

7,236 ACCI- 166 um pitch- 12 rows

CC return path

Underfill ingress/ egress

-17-May 30 – June 2, 2006

High-K Material

Ceramic Loaded photo-definable epoxyFor use underneath Capacitive pads

30 40 50 60 7010

20

30

40

50

60

70

Perm

ittiv

ity (K

)

BaTiO 3 loading (vol%)

1 KHz 10 KHz 100 KHz 1 MHz

Plate size vs. High-K filling thickness for desired Coupling capacitance(Permittivity of High-K material: 30.0)

4652

5762

6670

7478

8185

56

63

7075

8186

9195

100104

65

73

80

87

93

99105

110115

120

30

40

50

60

70

80

90

100

110

120

130

2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0

High-K filling thickness (um)

Pla

te s

ize

(um

)

150 fF225 fF300 fF

(c/- Kingon, Kim, MSE)

-18-May 30 – June 2, 2006

Integrated Process Flow

1. Fabricate bumped chips and modified HyperBGA

2. Deposit High-K ceramic-loaded epoxy• Barium titanate (BaTiO3); Epoxy (LMB7081)

3. Partially cure epoxy (120 oC)4. Pattern epoxy

• Etch; or• Lift-off BT7081 on FR-4

200 um / 150 um

-19-May 30 – June 2, 2006

… Process Flow

5. Flip-chip attach / Reflow• Cure and glass transition temperature

range supports lead and lead-free solder• Pressure needed for uniformity

6. Capillary Underfill Application7. Underfill / High-K cure

500g

Applied force= 2 Kgf/cm2

Mechanical flattening for high K patterns

-20-May 30 – June 2, 2006

Advantages of Approach

Leverages established technologies• Capilliary Underfill• HyperBGA Technology• Ceramic-loaded epoxy

Gives Considerable Design Margin on Capacitor• 150 fF minimum required• Design = 600 fF @ 10 um gap• Compensate for co-planarity and process variation

-21-May 30 – June 2, 2006

Open Questions

Optimal Ingress/Egress patterns for underfill

Tradeoffs of details on temperature profileLift-off or etching of epoxy

Or?

-22-May 30 – June 2, 2006

Conclusions

ACCI permits high pin-count chips• High Signal I/O• AND high power/ground count for power integrity• Multi-Gbps at low power• Larger chips possible

Laminate demonstration in process• Enabled by high-K ceramic loaded polymer and

flatness of HyperBGA technology• Potentially enables 13,000 pin chip!

-23-May 30 – June 2, 2006

Backups

-24-May 30 – June 2, 2006

Microwave frequency measurement

-50

-40

-30

-20

-10

0

0 5 10 15 20 25 30

S21

(dB

)

Frequency (GHz)

Alumina

BaTiO3-epoxy on alumina

Composite cured at 210 oCNo significant relaxation in permittivty up to ~ 15 GHzMultimoding beyond 20 GHz - needs wirebond or air brdgeExtraction of precise dielectric loss is underway (from CPW transmission line)

17.514.3316.24.906

Permittivity of BaTiO3-epoxy nanocomposite

Frequency (GHz)

1014.83

9.385.071

Permittivity of Al2O3Frequency

(GHz)

Reflection coefficient (S21) for CPW T-resonator for BaTiO3-epoxy/Al2O3 substrate

-25-May 30 – June 2, 2006

Direct Photolithography of BaTiO3-polymer thick films

- MaterialsBarium titanate (BaTiO3)Epoxy (LMB7081, photodefinable)

- 150~250 μm sized square patterns on Cu clad FR4 board- Photdefinability limit with BaTiO3 loading (above 20vol%)

BaTiO3 5 vol%

4000 mJ/cm2

120 oC/12 min

BaTiO3 10 vol%

4000 mJ/cm2

120 oC/12 min

BaTiO3 15 vol%

7000 mJ/cm2

110 oC/60 min

BaTiO3 20 vol%

7000 mJ/cm2

110 oC/60 min

BaTiO3 25 vol%

7000 mJ/cm2

110 oC/60 min

BaTiO3 30 vol%

7000 mJ/cm2

110 oC/60 minPatterns shown Patterns washed Off

-26-May 30 – June 2, 2006

Thermal properties of ceramic-polymer composites

Differential scanning calorimetry (DSC) analysis in N2 atmosphereUseful for investigating cure reaction in polymer containing systemMax. curing reaction occurs 210~220 oC (in left fig.): Closely matches with commercial capillary underfillTg (transition temperature) ranges 100~110 oC (in right fig.) : Needs to be go up and be close to 130~140 oC as in ideal capillary underfill

-20

-15

-10

-5

50 100 150 200 250 300

EpoxyBaTiO3-epoxy

Hea

t flo

w (W

/g)

Temperature (oC)

-25

-20

-15

-10

-5

0

5

10

50 100 150 200 250 300

EpoxyBaTiO3-epoxy

Hea

t flo

w (W

/g)

Temperature (oC)