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AC circuit analysis. Procedures to solve a problem Identify the sinusoidal and note the excitation frequency. Covert the source(s) to phasor form Represent each circuit element by its impedance Solve the resulting phasor circuit using previous learnt analysis tools - PowerPoint PPT Presentation
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AC circuit analysis
• Procedures to solve a problem– Identify the sinusoidal and note the excitation frequency.– Covert the source(s) to phasor form– Represent each circuit element by its impedance– Solve the resulting phasor circuit using previous learnt analysis
tools– Convert the (phasor form) answer to its time domain equivalent.
Ex. 4.16, p180
Example
)451000cos(205.0
05.005.0100
55
1010055
)901000cos(05.0
)(9005.005.0100
5
100
05
05)100100()100(
010)100(100100
100
10010101000/1
2
2
2
1
1
21
21
6
ti
jj
ji
jij
ti
Ajjj
i
ijjij
ijij
jZ
jjZ
L
c
)631000cos(11.0
)05.0
1.0tan1000cos(1.005.0
1.005.005.005.005.0
122
21
t
t
jjjiiiC
a. Calculate the current through the capacitor and inductor.
b). If 10V and 5V batteries are replace by V1=10Vcos(1000t)
and V2=5Vcos(1000t), respectively, calculate the current
through the capacitor.
j
jj
j
jj
j
j
i
jj
j
jj
j
i
05.005.0
10000
1000500500
0100
100100100
5100
10100100
05.010000
500
0100
100100100
05
10010
2
1
Charging a Capacitor
RC
t
etv 1 RC
t
eRdt
tCdv
dt
dqi
0.63
t
v(t)
t=RC= t
i
/R
t=RC=
0.63 /R
Time constant (): time needs to charge a capacitor to 63% of its full charge.
The larger the RC, the longer it takes to charge a capacitor.
The larger the R value, the smaller the current is in the circuit.The larger the C value, the more the charge the capacitor can hold
Discharging a Capacitor
i=0
Vc=++++ ----
t = 0
i Vc=++++ ----
RC
t
RC
t
eR
i
etv
t
vC(t)
Examplea) A young MacGyver enthusiast is attempting to design a simple switched RC circuit to use as a fuse timer. The child has a 5 F capacitor and one AAA cell with an emf of 1.5 V and an internal resistance of 0.6 ohm. If the fuse will ignite when the capacitor is charged to a voltage of 1.0 V, how much time does the youngster have to vacate the premises?
b). With a never ending enthusiasm for adding batteries to a circuit, the youngster connects a fresh 9 V lithium battery as shown. Now how much time expires after switch closure until the fuse is ignited?
Examplea) A young MacGyver enthusiast is attempting to design a simple switched RC circuit to use as a fuse timer. The child has a 5 F capacitor and one AAA cell with an emf of 1.5 V and an internal resistance of 0.6 ohm. If the fuse will ignite when the capacitor is charged to a voltage of 1.0 V, how much time does the youngster have to vacate the premises?
b). With a never ending enthusiasm for adding batteries to a circuit, the youngster connects a fresh 9 V lithium battery as shown. Now how much time expires after switch closure until the fuse is ignited?
sec3.3
5.1
0.11ln56.0
1ln
1
S
C
RC
t
SC
V
VRCt
eVV
•The average ac power (Pav) is the power dissipated on the load resistor. • 0cos1, dependent on the complex load.• ideal power factor: cos=1, Z=R, pure resistive load
AC Power
RI
ZI
VItP
2
2
~
cos~
cos~~
)(
tIti
tVtv
p
p
cos)(
cos)(
rms value
Average power
Review cont.: Complex Power
jQP
ZVZIIVS
av */
~*
~*
~~ 22
• real power Pav: power absorbed by the load resistance.• Q (volt-amperes reactive, VAR): exchange of energy between the source and the reactive part of the load. No net power is gained or lost during the process.• S : compute by measuring the rms load voltage and currents without regard for the phase angle.• if Q<0, the load is capacitive, Q>0, the load is inductive
Instantaneous power p(t)
Pay attention to complex conjugate
Topic 2: Digital Circuit: Combinational Logic
• Logic operation• Real problem to truth table• Karnaugh Map:
– Box “1” or box “0”• Largest supercell possible• 2n ones or zeros in each supercell• Edges of Karnaugh map are connected• Finish all ones or zeros• Doesn’t matter (“d” or “x”) can be considered as either “1” or
“0”.
Digital Circuit Review: Sequential Logic• Flip Flips• Timing diagram
1. When CLK signal arrives (rising edge or falling edge), FF will have outputs (Q and Q’) depending on the input (ex. D, or J, K). At this stage, ignore combinational logic if there exist in the circuit.
2. After finishing the output (Q and Q’), then work on the combinational logic, which typically determines the inputs (ex. D, or J, K) which will determine the output (Q and Q’) at next CLK signal
• Sequential circuit design: State Map1. Construct a state map.2. Convert the state map to truth map. Note: have to include all
combination. Ex. If there are three outputs, Q0, Q1, and Q2, then there are 8 states (combinations) that have to be listed. Some of them may be listed as “d”.
3. Prepare the inputs such that the outputs (Q0, Q1, and Q2) at next state will follow the state map.
4. Convert the truth map to Karnaugh map: the inputs of FF (ex, D, or J, K) is the results in Karnuagh map, i.e. the value of the inputs of FF goes into cells. The outputs of FF is the inputs in the Karnaugh map.
Example: Combinational Logic
• Problem 2 of Exam 2:
CD 00 01 11 10
AB\
00 1 0 0 1
01 1 1 1 0
11 1 1 1 0
10 1 0 0 1
Example
Determine the state diagram for this two-bit counter.
How would you reconfigure the counter to reverse the sequence determined above? (Show all work!)
