Abraham Gallas for the LHCb VELO Upgrade The 20th Anniversary International Workshop on Vertex Detectors 19-24 June 2011, Rust, Austria The LHCb Upgrade

Abraham Gallas for the LHCb VELO Upgrade The 20th Anniversary International Workshop on Vertex Detectors 19-24 June 2011, Rust, Austria The LHCb Upgrade from 1 to 40 MHz readout

Outline: The LHCb upgrade: scenario & strategy The Vertex detector upgrade: Environment & plan Detector module design & layout Sensor options ASIC design Data readout rates RF foil and material constraints Cooling Prototyping results from test beams Summary 2

The LHCb upgrade The Plan: LHCb is currently running with excellent performance at higher luminosity than the nominal: L = 2 10 32 cm 2 s -1 The experiment will collect ~ 5fb -1 before the 2 nd LHC shutdown circa 2017 will largely cover the Physics goals of the experiment During this shutdown we want to upgrade the detector to run at higher luminosity: L = 10 33 cm 2 s -1 to collect 50 fb -1 (5fb -1 /year) and increased energy s = 14 TeV This does not depend on any (HL)-LHC machine upgrade 3

The LHCb upgrade Problem: The L0 hadron hardware trigger loses efficiency at higher luminosities: Because the DAQ event readout rate is limited to 1MHz trigger thresholds (E T ) need to be raised Solution: No hardware trigger, increase the readout rate to 40MHz and implement a fully software-based trigger in the CPU farm 4 L0-buffer 1MHz Current DAQ Front-end router CPU-farm Tell1 40MHz Upgraded DAQ Front-end router CPU-farm Tell40 + LLT-buffer 1MHz 5-10MHz L0 LLT Max 3 kHzMax 20 kHz Storage ~ 50 kB ~ 100 kB

Environment: radiation challenge 5 Severe & non-uniform irradiation damage. Dose after 50 fb -1 The sensors edges placed at 7mm from the beam line during stable beams. After 50 fb -1 they see a fluence > 4x10 15 1 MeV n eq cm -2 Recent RD50 studies have shown that silicon irradiated at these levels still delivers a signal of ~ 10ke - / MIP After that dose, we expect currents of ~120 A/cm 2 @ -15 C and V bias = 900 V Danger of thermal runaway at the tip of the sensor from bulk current and heat injected by ROC Efficient heat removal mandatory to avoid thermal runaway!! Low noise electronics to cope with reduced signal 185 MRad or 4.1 10 15 n eq /cm 2 7mm

Environment: data rate challenge 6 Curves fitted to A.r -1.9 radius (cm) Particle Hits / Event / cm 2 Luminosity (cm -2 s -1 ) 2.10 32 Current 5.10 32 10.10 32 20.10 32 A=0.981.462.464.80 ~ 5 particles/cm 2 /event at r=7.0 mm Particle occupancy per event (simulation) Electronics has to digitize, zero suppress and transmit event data at 40 MHz By pixel standards the occupancy of the VELO is miniscule, but the data rate is HUGE 1 chip O(1cm 2 ) has to transmit ~13 Gbit s -1 Our current granularity, occupancies = ok but FE electronics and DAQ are not

VELO Upgrade plan Different systems of the current VELO 1 will be retained: CO 2 cooling plant LV & HV power supply systems Vacuum vessel and equipment Motion system Major new components: Detector modules based on pixel sensors New readout ASIC: VELOPIX Enhance module cooling interface New design of low material RF foil between beam and detector vacua Multi Gb s -1 readout system Main design concerns: Efficient cooling to avoid thermal runaway Handle the huge data rate Reduce material budget Maintain if not improve the excellent performance 2 : Proper time resolution ~ 40 fs IP resolution ~ 13 + 25/pT m 7 Replace 1,2 See talk by Kazu AKIBA, Silvia Borghi

Sensor tiles: 3 readout ASICs on a single sensor, with a guard ring ~500 m 2 sensor tiles are mounted on opposite sides of a substrate: Readout & power traces on the substrate Substrate choices: CVD diamond : excellent mechanical & thermal properties: => low mass Carbon fibre/TPG or Al/TPG Material in sensitive region ~ 0.8%X 0 Prototype work started using Timepix ROCs (@ CNM). Velo Pixel module 8 ~15mm ASIC ~43mm Sensor tile : sensor Bot Sensor 200um ASIC150um Substrate 400um Cooling channel Glue 50um Top Sensor 200um ASIC150um Connector 60 m Kapon+120 m Al

Pixel module & detector layout 9 BEAM The full detector is composed of 26 stations The modules on either side of the beam are staggered to create overlap regions This layout has been simulated to be fully efficient (~98.3%, 4 hit per track) in the LHCb acceptance 15-250x300mrad Varying spacing along the beam axis. Minimal pitch 24 mm A station is made of 8 sensor tiles. active area ~100% (except small gaps) Closest pixel is at 7.5 mm from the beam center top tiles, bottom tiles ~ 1 mm gap

Sensor options R&D 10 Planar Silicon: Thin sensors seem well suited to the high fluences R&D focus is on: Reducing guard ring size. (closer approach to the beam, better impact parameter resolution) More exotics solutions: trenches, laser scribing & Al 2 O 3 Sidewall passivation (under investigation) Reducing thickness. (less X 0, lower bias voltage) Several wafers with various manufacturers CNM/USC : 150m p-in-n sensors, 150-200m n-in-p sensor single ASICs and later in the year 3x1 ASICs tiles Micron/Liverpool: n-in-p (150 and 300m thick) VTT: slim edge (active) 50,100m edge, different GR, 50-200 m thick Irradiation campaign up to 1.4 x 10 16 MeV n eq /cm 2 : Planar silicon + Medipix3 check performance in test beam Different GR structures to be fabricated at the manufacturers d Dicing distances= 250m, 400m, 600m Distance calculated from the active area. One guard ring. CNM G. Pellegrini et al. Marc Christophersen et al.

Sensor options R&D 3D sensors: Lower depletion voltage and low power less critical for thermal runaway Greater signal charge due to faster collection time (less trapping) potentially super radiation hard Active edge allows closer approach to beam Double-sided increase yield and improved areas of inefficiency Many Medipix /Timepix assemblies available Diamond p-CVD: No thermal run away problem! Very radiation hard Double act: sensor and thermal path Financially affordable for the VELO upgrade ( total surface ~ 1340 cm 2 ) Produced 1.43 x 1.43 cm 2, 750 m thick sensor Will produce Timepix assemblies for position resolution studies in testbeam 11 Fluence (10 15 1 MeV n eq cm -2 ) 90 S r

Strip-based alternative design 12 Designed new R & strip sensors, as backup solution in case material budget or power of the pixel detector beyond acceptable levels: 30 m minimum pitch, 20 x 128 strips per sensor Goal : keep occupancies < 0.6 % at 10 33 cm -2 s -1 Signal to Noise ratio after 50 fb -1 : Keep strip capacitance low Remove pitch adapter to FE ROC 40MHz rad-hard ROC to be designed: Adapted to low capacitance detector Programmable ZS data transmission Possible synergy with ST upgrade Sensitive area less than 500 m from edge. First strip at 7.5 mm from beam Reduce X 0 Test of prototypes from Hamamatsu this year Pixels Strips

ASIC development 13 Timepix(now) Timepix2(end 2011) VELOPIX(2012) 256x256 pixels, size (55 m x 55 m) gives equal spatial precision in both directions, removing the need for double sided modules (factor 2 in material) IBM 130 nm CMOS process 3 modes of operation Counting mode Time of Arrival: ToA Time over threshold: ToT Low occupancy is suited to ToT measurement, with no loss from 1 s deadtime Changes needed Replace shutter based readout/acquisition scheme by continuous, deadtimeless (ZS) operation Sustained readout of pixels with maximum flux 5 particles /cm 2 /25 ns Reduced ToT range and resolution Add bunchtime identification good within 25 ns Timepix2 is an important step towards VELOPIX Similar front end Fast column bus Data Driven readout Simultaneous Time over Threshold and Time of Arrival measurements Collaborating in the design Aim to have first VELOPIX by 2012

ASIC development Timepix2/VELOPIX Analog requirements overlap ~100%: Reduce timewalk:

ASIC development Digital functionality of VELOPIX: Simultaneous 4 bit Time-over-threshold and time identification (12 bit) Data loss must be kept < 0.5% in worst conditions (6kHz pixel hit-rate) Limit ToT < 400ns Adequate buffering & bus speeds Sparse and data driven readout SEU protection of logic & registers multi-Gbit/s output links : 4 x 3.2Gb/s# Design of superpixel (4x4), column bus and EOC logic very advanced Total power budget

Data rates 16 1.3 1.0 5.3 2.6 0.6 1.0 1.3 1.0 5.3 2.6 0.6 1.0 Average #particles/event Numbers at highest occupancies: average particle rate per hottest asic ~ 5 particles/25ns = 200MHz average pixel cluster size ~2: (pessimistic assumption, 200m Si) Information bits per hit pixel : 32 4 bit : Time over Threshold value 12 bit : bunch identification 16 bit : pixel address => Single asic data rate can reach 13 Gbit/s ! 30% data reduction can be achieved by clustering data: share the bunch id (12bit) and address bits between neighbor pixels. must be done before column readout, i.e. inside pixel array ! most efficiently done in units of 4x4 pixels = Super pixel Still requires several multi-gigabit readout links Challenge to divide work between FPGA readout and ASIC logic Current questions: Can we specify stream sizes to reduce workload on DAQ system How much information should we decode for trigger pattern recognition stage?

RF separation foil I 17 Long list of severe requirements: Vacuum tight (< 10 -9 mbar l/s) Radiation hard Low mass ( dominates the X 0 contribution before the second measured point). Rigid to prevent deflection onto the sensors or pinhole leaks Good electrical conductivity: Mirror beam currents and shield against RF noise pick-up in front-end electronics Thermally stable and conductive (heat load from the beam) Material and fabrication options: Aluminium (AlMgMn): 200-350 m thickness: By 5-axis milling of a single homogeneous block Carbon Fiber Reinforced Polymer (CFRP) coated with Aluminium Carbon Fiber (impractical, porosity and thickness vary too much) corrugation

Cake-shaped foil on a 3-axis milling machine Inductive measurements + 3D measurements Leak rate: 6mm

5 plies carbon fiber + epoxy + nano-particles + Al (vapor deposition) RF separation foil III 19 A proof-of-technique prototype has been made Very encoring results, still some issues need to be improved

Cooling studies 20 At the tip of the sensor I leak O(100) A/cm 2 : Thermal runaway avoided if temperature -10C to -15C First ANSYS simulations done: Model includes radial (r -1.9 ) and temperature dependent leakage power generated in Si. 400 m-thick CVD diamond substrate to the tip of the sensor Cooling channel at 1cm from the outermost edge of silicon Two-phase CO 2 cooling capable to -35 for the cooling channel Nominal thickness and thermal conductivities, and ROC heat loads were used Various parameters were modified and the conclusions: The cooling channel should be as close as possible to the silicon The ROC power should be minimized Thermal impedances between cooling line and silicon should be minimized For a ROC power < 3.0 W/chip CO 2 cooling is enough to avoid thermal runaway up to a dose ~10 16 n eq /cm 2. Factor 2 Verifications with thermal mockups are planned CO 2 cooling Temp -35C Tip Temp ~ -17C

Timepix telescope evolution 21 TelescopePixelResolution at DUT Time TagTrack Rate Timepix 2009 55 m2.3 m 100ns100Hz Timepix 2010 (May) 55 m2.0 m ~1ns~700Hz Timepix 2010 (Aug- present) 55 m1.5 m ~1ns 5kHz 6 pixel telescope planes angled in 2 dimensions to optimize resolution Device Under Test moved and rotated via remote controlled stepper motor Fine pitch strip detector with fast electronics LHC readout USB2 readout 700 tracks per second USB1 readout

Timepix Telescope Performance 22 RELAXD interface Scintillator Coincidence and TDC ~1ns RELAXD interface/ LHC readout (Beetle, ) RELAXD interface DUT Cooled Timepix ToT Tracking Logic + TDC Synchronized Trigger Timepix ToA Track Time Tagging Plane ~100ns RELAXD readout from NIKHEF (FPGA-based) >5kHz track rate, resolution @ DUT 1.5 m Implemented a TDC with whichTimepix ToA mode gives us ~1ns per track time stamping Able to provide and record synchronized triggers to 40MHz readout 50,000,000 tracks recorded in 2 weeks (120 GeV @ SPS) Eight different DUTs analysed* Telescope in Time Tagging configuration *arXiv:1103.2739v2 [physics.ins-det]

Planar Silicon: Thin vs Thick 23 Sensor Angle (deg) Thin sensors: Direct comparison of 300 and 150 m thick sensors in identical conditions

Planar sensor 24 Resolution as a function of angle 10V data (close to depletion) 100V data (overdepleted) There is an enormous gain at lower voltage Possible advantage for VELO under investigation Resolution as a function of # bits Resolution as a function of number of bits (shown for three different angles) Input to Timepix2/Velopix design 4 bits and above are safe 3 bits is close to resolution degradation

3D sensors test beam results 25 Detailed characterization of 3d device and direct comparison to planar sensor*. Irradiated sensor also evaluated 3DPlanar * Degrees0o0o 10 o 0o0o Spatial resolution 15.80.19.180.110.150.15.860.1 Voltag e CornerCentreRingPixel 2V35.679.199.191.2 20V 39.186.799.793.0 Binary resolution = 55m / 12 = 15.9m Resolution before and after irradiation close to binary resolution 3D binary resolution = 74.5m / 12 = 23.1m *2011 JINST 6 P05002 doi: 10.1088/1748-0221/6/05/P05002

Results from Diamond p-CVD sensors Strasbourg telescope 26 Goal: produce 400 m sensors and compare their performance with 150 m Si at different level of irradiation First step: laboratory and test bench studies of 750 m sensors in a test beam (CERN RD42 test beam with Strasbourg telescope) Preliminary

Summary We expect the LHCb Upgrade to happen in the 2 nd LHC shutdown circa 2017 The experiment has a firm plan and timeline to achieve the upgrade The VELO pixel module concepts and detector layout will be realizable We are still pursuing different sensor options The ASIC design is progressing well R&D is progressing well in the key aspects of the detector Prototypes are being built and will be tested to assess their performances and suitability in a harsh environment like the current VELO detector 27

Documents

Abraham Gallas for the LHCb VELO Upgrade The 20th Anniversary International Workshop on Vertex Detectors 19-24 June 2011, Rust, Austria The LHCb Upgrade