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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-1 Lecture 9 - MOSFET (I) MOSFET I-V Characteristics October 6, 2005 Contents: 1. MOSFET: cross-section, layout, symbols 2. Qualitative operation 3. I-V characteristics Reading assignment: Howe and Sodini, Ch. 4, §§4.1-4.3 Announcements: Quiz 1: 10/13, 7:30-9:30 PM, (lectures #1-9); open book; must have calculator.

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Page 1: about mos details

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-1

Lecture 9 - MOSFET (I)

MOSFET I-V Characteristics

October 6, 2005

Contents:

1. MOSFET: cross-section, layout, symbols

2. Qualitative operation

3. I-V characteristics

Reading assignment:

Howe and Sodini, Ch. 4, §§4.1-4.3

Announcements: Quiz 1: 10/13, 7:30-9:30 PM,(lectures #1-9); open book; must have calculator.

Page 2: about mos details

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-2

Key questions

• How can carrier inversion be exploited to make a tran-sistor?

• How does a MOSFET work?

• How does one construct a simple first-order model forthe current-voltage characteristics of a MOSFET?

Page 3: about mos details

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-3

1. MOSFET: layout, cross-section, symbols

source

gate

drainbody

gate oxideinversion layer channel

polysilicon gate

p

p

n

n

p+ n+n+

n+

p+ n+

n+

n+n+

gate length

gate

wid

thSTI edge

Key elements:

• inversion layer under gate (depending on gate voltage)

• heavily-doped regions reach underneath gate ⇒ in-version layer electrically connects source and drain

• 4-terminal device: body voltage important

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-4

Image removed due to copyright restrictions.

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-5

2 Circuit symbols

Two complementary devices:

• n-channel device (n-MOSFET) on p-Si substrate(uses electron inversion layer)

• p-channel device (p-MOSFET) on n-Si substrate(uses hole inversion layer)

(a) n-channel MOSFET

D−

G

−IDp

B

(b) p-channel MOSFET

+

_VSG

D

S−

G

+

+

_VGS

IDn IDn

B

VSD > 0

VDS > 0

+

_VBS

+

_VSB

D

GB

S

S S

B

D

G

−IDp

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-6

2. Qualitative operation

Water analogy of MOSFET:

• Source: water reservoir

• Drain: water reservoir

• Gate: gate between source and drain reservoirs

source draingate

VGS

VDSwatern+

n+

n+

p

S

G

D

B

inversion layer

depletion region

VGS

VDS

ID

Want to understand MOSFET operation as a function of:

• gate-to-source voltage (gate height over source waterlevel)

• drain-to-source voltage (water level difference betweenreservoirs)

Initially consider source tied up to body (substrate orback).

Page 7: about mos details

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-7

Three regimes of operation:

2 Cut-off regime:

• MOSFET: VGS < VT , VGD < VT with VDS > 0.

•Water analogy: gate closed; no water can flow regardlessof relative height of source and drain reservoirs.

no water flow

VGD<VTVGS<VT

n+

n+

n+

p

S

G

D

no inversion layer anywhere depletion

region

ID = 0

Page 8: about mos details

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-8

2 Linear or Triode regime:

• MOSFET: VGS > VT , VGD > VT , with VDS > 0.

• Water analogy: gate open but small difference in heightbetween source and drain; water flows.

VGD>VTVGS>VT

n+

n+

n+

p

S

G

D

inversion layer everywhere

depletion region

Electrons drift from source to drain ⇒ electrical current!

• VGS ↑ → |Qn| ↑ → ID ↑

• VDS ↑ → |Ey| ↑ → ID ↑

VDS

small VDSID

VGS>VT

00 VGSVT

small VDSID

VDS

0

Page 9: about mos details

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-9

2 Saturation regime:

• MOSFET: VGS > VT , VGD < VT (VDS > 0).

• Water analogy: gate open; water flows from source todrain, but free-drop on drain side ⇒ total flow indepen-dent of relative reservoir height!

inversion layer "pinched-off" at drain side

VGD<VTVGS>VT

n+

n+

n+

p

S

G

D

depletion region

ID independent of VDS: ID = IDsat

VDS

ID

VDSsat=VGS-VT

VGDsat=VT

00

saturationlinear

Page 10: about mos details

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-10

3. I-V characteristics

Geometry of problem:

n+

n+

n+

p

S

G

D

B

y0

0

L

inversion layer

depletion regionVBS=0

VGS

VDS

IDIS

x

-tox

xj

2 General expression of channel current

Current can only flow in y-direction:

Iy = WQn(y)vy(y)

Drain terminal current is equal to minus channel current:

ID = −WQn(y)vy(y)

Page 11: about mos details

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-11

ID = −WQn(y)vy(y)

Rewrite in terms of voltage at channel location y, Vc(y):

• If electric field is not too big:

vy(y) ' −µnEy(y) = µndVc(y)

dy

• For Qn(y) use charge-control relation at location y:

Qn(y) = −Cox[VGS − Vc(y) − VT ]

for VGS − Vc(y) ≥ VT .

All together:

ID = WµnCox(VGS − Vc(y) − VT )dVc(y)

dy

Simple linear first-order differential equation with one un-known, the channel voltage Vc(y).

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-12

Solve by separating variables:

IDdy = WµnCox(VGS − Vc − VT )dVc

Integrate along the channel in the linear regime:

-for y = 0, Vc(0) = 0

-for y = L, Vc(L) = VDS (linear regime)

Then:

ID

∫ L0 dy = WµnCox

∫ VDS0 (VGS − Vc − VT )dVc

or:

ID =W

LµnCox(VGS −

VDS

2− VT )VDS

Page 13: about mos details

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-13

For small VDS:

ID ' W

LµnCox(VGS − VT )VDS

Key dependencies:

• VDS ↑ → ID ↑ (higher lateral electric field)

• VGS ↑→ ID ↑ (higher electron concentration)

• L ↑ → ID ↓ (lower lateral electric field)

• W ↑ → ID ↑ (wider conduction channel)

VDS

small VDSID

VGS>VT

00 VGSVT

small VDSID

VDS

0

This is the linear or triode regime.

Page 14: about mos details

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-14

In general,

ID =W

LµnCox(VGS − VDS

2− VT )VDS

Equation valid if VGS − Vc(y) ≥ VT at every y.

Worst point is y = L, where Vc(y) = VDS, hence, equa-tion valid if VGS − VDS ≥ VT , or:

VDS ≤ VGS − VT

VDS

ID

VGS

VGS=VT

VDS=VGS-VT

00

term responsible for bend over of ID: −VDS2

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-15

To understand why ID bends over, must understand firstchannel debiasing:

VDS

0

0

0

yL

L

L

y

y

|Qn(y)|

|Ey(y)|

Vc(y)

0

0

0

VGS

VT

VDS

0 L y

VGS-Vc(y)

Cox(VGS-VT)

local gate overdrive

VDS>0

VDS>0

VDS>0

VDS>0

VDS=0

VDS=0

VDS=0

VDS=0

Along channel from source to drain:

y ↑ → Vc(y) ↑ → |Qn(y)| ↓ → |Ey(y)| ↑

Local ”channel overdrive” reduced closer to drain.

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-16

Impact of VDS:

VDS

VDS

VDS=0

0

0

0

yL

L

L

y

y

0

0

0

VGS

VT

VDS

0 L y

Cox(VGS-VT)

local gate overdrive

VDS=0

VDS=0

VDS=0VDS

VDS

VDS

|Qn(y)|

|Ey(y)|

Vc(y)

VGS-Vc(y)

As VDS ↑, channel debiasing more prominent⇒ ID rises more slowly with VDS

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-17

3µm n-channel MOSFET

Output characteristics (VGS = 0 − 4 V, ∆VGS = 0.5 V ):

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-18

Zoom close to origin (VGS = 0 − 2 V, ∆VGS = 0.25 V ):

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-19

Transfer characteristics (VDS = 0 − 100 mV, ∆VDS =20 mV ):

Page 20: about mos details

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-20

Key conclusions

• The MOSFET is a field-effect transistor:

– the amount of charge in the inversion layer is con-trolled by the field-effect action of the gate

– the charge in the inversion layer is mobile ⇒ con-duction possible between source and drain

• In the linear regime:

– VGS ↑⇒ ID ↑: more electrons in the channel

– VDS ↑⇒ ID ↑: stronger field pulling electrons outof the source

• Channel debiasing: inversion layer ”thins down” fromsource to drain ⇒ current saturation as VDS approaches:

VDSsat = VGS − VT