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1 | P a g e
TABLE OF CONTENTS
I. Introduction 1
A. Background of the Study 1
B. Design Overview 1
C. Scope and Delimitation 2
II. Architecture 4
A. Block Diagram 4
B. Address Bus 5
C. Data Bus 5
D. I/O Ports 5
E. Program Counter 5
F. Stack Pointer 5
G. General Purpose Register 5
H. Temporary Register 6
I. Accumulator 6
J. Arithmetic Logic Unit (ALU) 6
K. Status/Flag Register 6
L. Instruction Register (IR) 6
M. Shift Register 7
N. Controller/ Sequencer 7
III. Controller/Sequencer 7
7
A. Microcode Memory 7
B. Next Address Generator 8
C. Control Address Register 8
D. Control Signals 8
2 | P a g e
IV. Instruction Set Architecture 10
A. Instruction Set Format / Opcode Mapping 10
B. Instruction Summary 10
C. Instruction Description 18
V. Simulation Results
A. Sample Code 102
B. Execution Trace (Tabulated)
VI. Design Calculations 103
A. Noise Margin 103
B. Power Dissipation 113
C. Fan Out 114
D. Propagation Delay 123
E. Clock Frequency 124
VII. Recommendations 125
References 125
List of Instructions 126
Appendix A: Hardware Summary
Appendix B: Specification Sheets
3 | P a g e
I. Introduction
__________________________________________________________________
A. Background of the Study
A microprocessor also known as a CPU or central processing unit is a complete
computation engine that is fabricated on a single chip. It is a single integrated circuit that is a
multipurpose, programmable, clock-driven, register based electronic device that accepts binary
data as input, processes it according to instructions stored in its memory, and provides results as
output. The basic functionality of a microprocessor is all based on the inherent ability to respond
to and generate mathematical and logical operations. Generally, it is a component that remains
efficient and productive for the life of the computer.
According to Carpinellis Very Simple CPU Design [1], to begin with the designing of a
microprocessor, the instruction set architecture must be developed which includes its instruction
set and its internal registers. Next thing to be considered is the development of a finite state
machine model of the micro-operations required to fetch, decode and execute each instruction
inside its instruction set. Lastly, an RTL specification for this state machine must also be
developed. The book also provided general design steps in micro-programmed design which we
followed in constructing the control unit of Bochen.
This paper aims to present a Microprocessor design in partial fulfillment of the
requirements of the course COMP421.
B. Design Overview
The unit is an 8-bit microprocessor that has a dedicated 16-bit address bus, 8-bit data bus,
an addressable memory of 64KB and 196 instructions with address modes Direct, Indirect,
Implied, Immediate, Register Direct, Register Indirect, Index and base Index addressing.
It is comprised of the following 8 bit registers: four general purpose register B, C, D, E,
an extended pair register H and L, two bidirectional I/O ports, an Accumulator, a Temporary
register, a Data register and an Instruction register. It also has 16 bit registers indirectly
accessible by the user which are the Address register, a Program counter, a Stack pointer, and an
Index register.
4 | P a g e
The ALU is capable of performing arithmetic operations addition and subtraction for both
BCD and signed integers. It can also perform logical operations AND, OR, XOR and NOT.
Increment and decrement are both performed at the Accumulator. It is capable of register shifting
such as linear shift right and linear shift left, which is done through the shift register. It makes
use of the Accumulator and the Data register as its operands.
The Control circuit is in accordance with the general design steps in microsequencer/
microprogrammed design presented by the book of Carpinelli [1] which are: 1) Designing the
data part and identifying the control and status signals 2) Identifying control flow requirements
to complete control-data interface and the block diagram 3) Generating the symbolic
microprogram 4) Finalizing the microinstruction format 5) Designing the microsequencer 6)
Generating the binary microcode or control ROM contents. It produces 56 control signals that
enable the different operation of the microprocessor needed for every state.
C. Scope and Delimitation
The scope and delimitations of BO-Chen microprocessor are the following
BO-Chen Microprocessor Unit is based on SAP-2 and SAP-3 Architecture
16-bit Address Bus and Data Bus
64kb RAM (design is not included)
8-bit Arithmetic Logic Unit
Arithmetic: Signed and BCD addition, subtraction
Logic: AND, NOT, OR, XOR
8-bit Registers
General Purpose Register: B, C, D, E, H & L
Extended Register pairs BC, DE, & HL
Special Purpose: A(Accumulator), T1(Temporary Register)
IO Port Mode: IO Port1, IO Port2
16-bit Program Counter
16-bit Stack Pointer
5 | P a g e
8-bit Instruction Register
Microsequencer control
Flag Register
Status Registers
2 I/O Ports
Microcode Memory (ROM. Design is not included)
It uses a Low-Endian Scheme for addressing instruction
It has 196 instructions with operational codes from 00h to C3h only.
6 | P a g e
II. Architecture
__________________________________________________________________
A. Block Diagram
FIGURE 1.Block Diagram
7 | P a g e
B. Address Bus
The Address Bus is a 16-bit communication link between all the different parts of the
MPU. The microprocessor uses this bus to specify to the memory which memory location to read
from or write on.
C. The Data Bus
The Data bus is an 8-bit bidirectional set of electrical paths that allows information or data to
travel from one unit to the other.
D. I/O Ports
I/O Ports are bidirectional ports that connect the peripherals to the processor. IO Port1
and IO Port2 ports are connected to the accumulator through the 8 bit data bus. It accepts input
from external devices for data processing and accepts the processed data from the Accumulator
to be sent to the output devices such as LEDs or screens.
E. Program Counter
The Program Counter is a 16-bit presettable up counter whose job is to keep track of the
location of the next instruction to be fetched, decoded and executed.
F. Stack Pointer
The stack pointer is a 16-bit presettable up/down counter which is capable of
incrementing and decrementing from the desired preset or initial value. Its primary function is to
indicate the top of stack.
G. General Purpose Register
The B, C, D, E, H and L are the General Purpose Registers. The designed GPRs are
implemented using 8-bit controlled buffer registers which store the data during a computer run. It
provides the fastest way for the CPU to access data. These registers have bidirectional access to
the bus for read and write operations.
8 | P a g e
H. Temporary Register
The Temporary Register is a register that holds the information used in the processor for
manipulating data and address. It is separated from the ALU for faster data processing. It can be
used as an alternative way to hold the data being added or subtracted from the Arithmetic Logic
Unit.
I. Accumulator
The Accumulator is a register in which intermediate arithmetic and logic results are
stored. It can also be used like a general purpose register which is capable of storing data or
operands for operations.
J. Arithmetic Logic Unit (ALU)
The ALU processes arithmetic and logic operations on the two operands, the
accumulator and the TMP register. The arithmetic unit is capable of doing signed and BCD
addition and subtraction. The logic unit is capable of doing the AND, NOT, OR, and XOR
operations.
K. Status/Flag Register
Status register is used to record the present status/flag of the previous operation done by
the ALU.
L. Instruction Register (IR)
The instruction register holds the instruction that the microprocessor is currently
executing. It is loaded by starting the microprocessor on a Fetch/Execute Cycle - also called an
instruction cycle. It is connected to the microprocessor's internal data bus, but it can only receive
data. It cannot place data on the internal bus.
9 | P a g e
M. Shift Registers
Shift registers are a type of sequential logic circuit, mainly for storage of digital data.
They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
the input of the next flip-flop.
N. Controller/Sequencer
The Bo-Chen unit is designed using a microsequencing control method. Instead of
generating the control signals using combinatorial and sequential circuit as applied in a
Hardwired control, a microsequencer stores its control signals in a lookup ROM, the microcode
memory. By accessing the locations of the ROM in the correct order, the lookup ROM asserts
the control signals in the proper sequence to realize the instructions in the processors instruction
set.
III. Controller/Sequencer
The control unit of BO-Chen is designed using a horizontal microcoded control
(Microsequencer). Under this design, a bit is allocated in the microinstruction for each micro-
operation.
A. Microcode Memory
The microcode, or microprogram, is stored in microcode memory. It consists of the
microinstructions to fetch, decode and execute every instruction in the microprocessors
instruction set.
B. Next Address Generator
The next address generator ensures that the microsequencer accesses the
microinstructions in the order necessary to process each instruction in the instruction set
properly. It uses mapping logic to access the correct execute routine for each instruction.
10 | P a g e
C. Control Address Register
The Control Address Register contains the address of the current microinstruction.
D. Control Signals
Control Signal causes the CPU to perform the desired micro-operations in the correct
order to fetch, decode and execute the instructions in the processors instruction set. Table 1
show that the summary of the control signals used in BO-Chen design.
TABLE 3.1.Control Signal Definition
CONTROL
SIGNALS DEFINITION
ABUS Output accumulator to data bus
ALOAD Enables loading to accumulator
ALUSEL0 Select operation of ALU
ALUSEL1 Select operation of ALU
ALUSEL2 Select Arithmetic or Logical operation of ALU
ARDEC Decrements contents of the Address register
ARINC Increments contents of the Address register
ARLOAD Enables loading to address register
BBUS Output the contents of Register B to [70] bus
BBUS2 Output contents of Register B to [158] bus
BCDSEL Select BCD operation of ALU
BLOAD Enables loading to Register B
CBUS Output register C to data bus
CLA Clear the contents of the Accumulator
CLB Clear the contents of register B
CLC Clear the contents of register C
CLD Clear the contents of register D
CLE Clear the contents of register E
CLF Clear the contents of register F
CLIX Clear the contents of index register
CTR0 Clear the contents of the state counter
CLOAD Enable loading to register C
DBUS Output the contents of Register D to [70] bus
DBUS2 Output contents of Register D to [158] bus
DLOAD Enables loading to Data Register
EBUS Output register E to data bus
11 | P a g e
ELOAD Output contents of Register E to data bus
HBUS Output the contents of Register H to [70] bus
HBUS2 Output contents of Register H to [158] bus
HLOAD Enables loading to Register H
IRLOAD Enables loading to the instruction register
IOP1BUS Outputs the contents of I/O port 1 to the data bus
IOP2BUS Outputs the contents of I/O port 2 to the data bus
IOP1LOAD Enables loading of I/O port 1 from the data bus
IOP2LOAD Enables loading of I/O port 2 from the data bus
IOP1MLOAD Determines whether Port 1 is input or output
IOP2MLOAD Determines whether Port 2 is input or output
IXDEC Decrements contents of the Index register
IXINC Increments contents of the Index register
IXLOAD Enables loading to Index Register
LBUS Output Register L to data bus
LLOAD Enables loading to Register H
MEMBUS
Enables reading of contents from memory and outputs data from memory
to data bus
MEMBUS2
Enables reading of contents from memory and outputs data from memory
to bus[158]
MEMLOAD Enables storing to memory and input of data from the data bus
MEMLOAD2 Enables storing to memory and input of data from the bus[158]
PCBUS Outputs the contents of Program Counter to the data bus
PCINC Increments the contents of Program Counter
PCLOAD Enables loading of the Program Counter
SFENB Enables the output of the Status/Flag Register
SHL Enables the Shift Register to shift left
SHR Enables the Shift Register to shift right
SPBUS Outputs the contents of the Stack Pointer to the address bus
SPDEC Decrements the contents of Stack Pointer
SPINC Increments the contents of Stack Pointer
SPLOAD Enables storing to stack pointer
SUB Enables the carry-in for subtraction operation
SRBUS Outputs the contents of the Shift Register
TBUS Outputs the contents of the Temporary register to the address bus
TLOAD Enables loading to the Temporary register
HLT Disables the circuit's clock
12 | P a g e
IV. Instruction Set Architecture
__________________________________________________________________
A. Instruction Set Format / Opcode Mapping
The BO-Chen microprocessor has 196 instructions which are represented by an 8 bit-
instruction code. The instruction addresses are set by incrementing the value of addresses by 1
starting the address from 0 and ends with C3h or 11000011b.
Figure 4.1.an 8-bit instruction code representation
B7
B6
B5
B4
B3
B2
B1
B0
B. Instruction Summary
The BO-Chen microprocessor has196 instructions which consist of arithmetic instruction,
register instruction, logical instruction, increment instruction, decrement instruction, shift
instruction, input/ output instruction, data transfer instruction, stack instruction, subroutine
instruction, jump instruction, flag instruction. The following summary shows the 196 total of
instructions.
TABLE 4.2.Instruction Summary
INSTRUCTIONS OPCODE T-STATES FLAGS
ADDRESSING BYTES Needed Affected
ADD B 00h 4 None All Register
Direct 1
ADD C 01h 4 None All Register
Direct 1
ADD D 02h 4 None All Register
Direct 1
ADD E 03h 4 None All Register
Direct 1
ADI x 04h 4 None All Immediate 2
ADD M 05h 5 None All Indirect 1
13 | P a g e
ADC B 06h 4 Carry All Register
Direct 1
ADC C 07h 4 Carry All Register
Direct 1
ADC D 08h 4 Carry All Register
Direct 1
ADC E 09h 4 Carry All Register
Direct 1
ADCI x 0Ah 4 Carry All Immediate 2
ADC M 0Bh 5 Carry All Indirect 1
DAD BC 0Ch 8 None All Register
Direct 1
DAD DE 0Dh 8 None All Register
Direct 1
DAI M 0Eh 8 None All Immediate 1
SUB B 0Fh 5 None All Register
Direct 1
SUB C 10h 5 None All Register
Direct 1
SUB D 11h 5 None All Register
Direct 1
SUB E 12h 5 None All Register
Direct 1
SUI x 13h 5 None All Immediate 2
SUB M 14h 6 None All Indirect 1
SUBB B 15h 5 Carry All Register
Direct 1
SUBB C 16h 5 Carry All Register
Direct 1
SUBB D 17h 5 Carry All Register
Direct 1
SUBB E 18h 5 Carry All Register
Direct 1
SCI x 19h 5 Carry All Immediate 2
SCN M 1Ah 6 Carry All Indirect 1
DSUB BC 1Bh 10 None All Register
Direct 1
DSUB DE 1Ch 10 None All Register
Direct 1
DSUBI M 1Dh 10 None All Immediate 1
BADD B 1Eh 4 None All Register
Direct 1
BADD C 1Fh 4 None All Register 1
14 | P a g e
Direct
BADD D 20h 4 None All Register
Direct 1
BADD E 21h 4 None All Register
Direct 1
BADI x 22h 4 None All Immediate 2
BADDN M 23h 5 None All Indirect 1
BADC B 24h 4 Carry All Register
Direct 1
BADC C 25h 4 Carry All Register
Direct 1
BADC D 26h 4 Carry All Register
Direct 1
BADC E 27h 4 Carry All Register
Direct 1
BADCI x 28h 4 Carry All Immediate 2
BACN M 29h 5 Carry All Indirect 1
BDAD BC 2Ah 8 None All Register
Direct 1
BDAD DE 2Bh 8 None All Register
Direct 1
BDADI M 2Ch 8 None All Immediate 1
BSUB B 2Dh 5 None All Register
Direct 1
BSUB C 2Eh 5 None All Register
Direct 1
BSUB D 2Fh 5 None All Register
Direct 1
BSUB E 30h 5 None All Register
Direct 1
BSUI x 31h 5 None All Indirect 2
BSUN M 32h 6 None All Indirect 1
BSUBB B 33h 5 Carry All Register
Direct 1
BSUBB C 34h 5 Carry All Register
Direct 1
BSUBB D 35h 5 Carry All Register
Direct 1
BSUBB E 36h 5 Carry All Register
Direct 1
BSCI x 37h 5 Carry All Immediate 2
BSCN M 38h 5 Carry All Indirect 1
BCSUB BC 39h 10 None All Register 1
15 | P a g e
Direct
BCSUB DE 3Ah 10 None All Register
Direct 1
BCSUBI M 3Bh 10 None All Immediate 1
DEC B 3Ch 6 None All Register
Direct 1
DEC C 3Dh 6 None All Register
Direct 1
DEC D 3Eh 6 None All Register
Direct 1
DEC E 3Fh 6 None All Register
Direct 1
INC B 40h 6 None All Register
Direct 1
INC C 41h 6 None All Register
Direct 1
INC D 42h 6 None All Register
Direct 1
INC E 43h 6 None All Register
Direct 1
DEC A 44h 3 None All Register
Direct 1
INC A 45h 3 None All Register
Direct 1
DECR HL 46h 8 None All Register
Direct 1
INCR HL 47h 8 None All Register
Direct 1
BDEC B 48h 6 None All Register
Direct 1
BDEC C 49h 6 None All Register
Direct 1
BDEC D 4Ah 6 None All Register
Direct 1
BDEC E 4Bh 6 None All Register
Direct 1
BINC B 4Ch 6 None All Register
Direct 1
BINC C 4Dh 6 None All Register
Direct 1
BINC D 4Eh 6 None All Register
Direct 1
BINC E 4Fh 6 None All Register
Direct 1
16 | P a g e
BDEC A 50h 3 None All Register
Direct 1
BINC A 51h 3 None All Register
Direct 1
SHL A 52h 3 None Sign, Zero,
Overflow Implied 1
SHR A 53h 3 None Sign, Zero,
Overflow Implied 1
AND B 54h 5 None Sign, Zero Register
Direct 1
AND C 55h 5 None Sign, Zero Register
Direct 1
AND D 56h 5 None Sign, Zero Register
Direct 1
AND E 57h 5 None Sign, Zero Register
Direct 1
ANDI x 58h 5 None Sign, Zero Immediate 2
ANDA M 59h 5 None Sign, Zero Indirect 1
OR B 5Ah 4 None Sign, Zero Register
Direct 1
OR C 5Bh 4 None Sign, Zero Register
Direct 1
OR D 5Ch 4 None Sign, Zero Register
Direct 1
OR E 5Dh 4 None Sign, Zero Register
Direct 1
ORI x 5Eh 4 None Sign, Zero Immediate 2
ORA M 5Fh 5 None Sign, Zero Indirect 1
XOR B 60h 4 None Sign, Zero Register
Direct 1
XOR C 61h 4 None Sign, Zero Register
Direct 1
XOR D 62h 4 None Sign, Zero Register
Direct 1
XOR E 63h 4 None Sign, Zero Register
Direct 1
XORI x 64h 4 None Sign, Zero Immediate 2
XORA M 65h 5 None Sign, Zero Indirect 1
NOT A 66h 3 None None Register
Direct 1
NOT B 67h 4 None None Register
Direct 1
NOT C 68h 4 None None Register
Direct 1
17 | P a g e
NOT D 69h 4 None None Register
Direct 1
NOT E 6Ah 4 None None Register
Direct 1
IOP1 x 6Bh 3 None None Direct 2
IOP2 x 6Ch 3 None None Direct 2
OUT IOP1 6Dh 3 None None Direct 1
OUT IOP2 6Eh 3 None None Direct 1
IN IOP1 6Fh 3 None None Direct 1
IN IOP2 70h 3 None None Direct 1
MOV A, B 71h 3 None None Register
Direct 1
MOV A, C 72h 3 None None Register
Direct 1
MOV A, D 73h 3 None None Register
Direct 1
MOV A, E 74h 3 None None Register
Direct 1
MOV B, A 75h 3 None None Register
Direct 1
MOV B, C 76H 3 None None Register
Direct 1
MOV B, D 77h 3 None None Register
Direct 1
MOV B, E 78h 3 None None Register
Direct 1
MOV C, A 79h 3 None None Register
Direct 1
MOV C, B 7Ah 3 None None Register
Direct 1
MOV C, D 7Bh 3 None None Register
Direct 1
MOV C, E 7Ch 3 None None Register
Direct 1
MOV D, A 7Dh 3 None None Register
Direct 1
MOV D, B 7Eh 3 None None Register
Direct 1
MOV D, C 7Fh 3 None None Register
Direct 1
MOV D, E 80h 3 None None Register
Direct 1
MOV E, A 81h 3 None None Register
Direct 1
18 | P a g e
MOV E, B 82h 3 None None Register
Direct 1
MOV E, C 83h 3 None None Register
Direct 1
MOV E, D 84h 3 None None Register
Direct 1
MOV A, M 85h 4 None None Register
Direct 1
MOV B, M 86h 4 None None Register
Direct 1
MOV C, M 87h 4 None None Register
Direct 1
MOV D, M 88h 4 None None Register
Direct 1
MOV E, M 89h 4 None None Register
Direct 1
MOV M, A 8Ah 4 None None Register
Direct 1
MOV M, B 8Bh 4 None None Register
Direct 1
MOV M, C 8Ch 4 None None Register
Direct 1
MOV M, D 8Dh 4 None None Register
Direct 1
MOV M, E 8Eh 4 None None Register
Direct 1
MOVI A, x 8Fh 3 None None Immediate 2
MOVI B, x 90h 3 None None Immediate 2
MOVI C, x 91h 3 None None Immediate 2
MOVI D, x 92h 3 None None Immediate 2
MOVI E, x 93h 3 None None Immediate 2
MOVI M, X 94h 5 None None Immediate 2
LDSP xx 95H 4 None None Direct 3
LDA xx 96h 5 None None Direct 3
SA xx 97h 5 None None Direct 3
LDAN 98h 4 None None Indirect 1
STAX 99h 4 None None Indirect 1
INC SP 9Ah 3 None None Direct 1
DEC SP 9BH 3 None None Direct 1
SPHL 9Ch 3 None None Direct 1
PUSH BC 9Dh 6 None None Indirect 1
PUSH DE 9Eh 6 None None Indirect 1
19 | P a g e
PUSH HL 9Fh 6 None None Indirect 1
PUSH AFS A0h 6 None None Indirect 1
POP BC A1h 5 None None Indirect 1
POP DE A2h 5 None None Indirect 1
POP HL A3h 5 None None Indirect 1
POP AFS A4h 5 None None Indirect 1
CALL xx A5h 9 None None Direct 3
CALLZ xx A6h N=2
Y=9 Zero None Direct 3
CALLNZ xx A7h N=2
Y=9 Zero None Direct 3
CALLSF xx A8h N=2
Y=9 Sign None Direct 3
CALLSFNS
xx A9h
N=2
Y=9 Sign None Direct 3
CALLCF xx AAh N=2
Y=9 Carry None Direct 3
CALLCFNZ
xx ABh
N=2
Y=9 Carry None Direct 3
CALLOF xx ACh N=2
Y=9 Overflow None Direct 3
CALLOFNZ
xx ADh
N=2
Y=9 Overflow None Direct 3
RET AEh 7 None None Implied 1
JMP xx AFh 4 None None Direct 3
JZ xx B0h N=2
Y=2 Zero None Direct 3
JNZ xx B1h N=2
Y=3 Zero None Direct 3
JSF xx B2h N=2
Y=4 Sign None Direct 3
JSFNZ xx B3h N=2
Y=4 Sign None Direct 3
JCF xx B4h N=2
Y=4 Carry None Direct 3
JCFN xx B5h N=2
Y=4 Carry None Direct 3
JOF xx B6h N=2
Y=4 Overflow None Direct 3
JFO xx B7h N=2
Y=4 Overflow None Direct 3
LDIX address B8h 5 None None Direct 3
INR IX B9h 3 None All Direct 1
20 | P a g e
DEC IX BAh 3 None All Direct 1
CLIX BBh 3 None All Implied 1
CLA BCh 3 None All Implied 1
CLB BDh 3 None All Implied 1
CLC BEh 3 None All Implied 1
CLD BFh 3 None All Implied 1
CLE C0h 3 None All Implied 1
CLF C1h 3 None All Implied 1
NOP C2h 2 None None Implied 1
HLT C3h 3 None None Implied 1
C. Instruction Description
This section describes each instruction by means of presenting its op code, addressing
mode, T states, flags needed & affected and its microinstructions per T state.
TABLE 4.3.INSTRUCTION DESCRIPTION
INSTRUCTION DESCRIPTION
ADD B Adds the contents of Register B to the Accumulator
Op Code 00h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADD B1 T1B BBUS, TLOAD
ADD B2 A A+T1 ALOAD, ALUSEL2,
ALUSEL0, CTR0
ADD C Adds the contents of Register C to the Accumulator
Op Code 01h
21 | P a g e
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADD C1 T1C CBUS, TLOAD
ADD C2 A A+T1
ALOAD, ALUSEL2,
ALUSEL0, CTR0
ADD D Adds the contents of Register D to the Accumulator
Op Code 02h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADD D1 T1D DBUS, TLOAD
ADD D2 A A+T1 ALOAD, ALUSEL2,
ALUSEL0, CTR0
ADD E Adds the contents of Register E to the Accumulator
Op Code 03h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADD E1 T1E EBUS, TLOAD
ADD E2 A A+T1 ALOAD, ALUSEL2,
22 | P a g e
ALUSEL0, CTR0
ADI x The 8-bit data (operand) is added to the contents of the Accumulator and the
result is stored in the Accumulator.
Op Code 04h
Addressing Immediate
T States 4
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADI x1 T1 M, PC PC+1 MEMBUS, TLOAD,
PCINC
ADI x2 A A+T1 ALOAD, ALUSEL2,
ALUSEL0, CTR0
ADD M Adds the contents of the address pointed by M to the Accumulator
Op Code 05h
Addressing Indirect
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADD M1 AR[15-8] H, AR[7-0] L
HBUS2, LBUS, ARLOAD
ADD M2 T1 MEM MEMBUS, TLOAD
ADD M3 A A+T1 ALOAD, ALUSEL2,
ALUSEL0, CTR0
ADC B Add the contents of Register B to the Accumulator with a carry.
Op Code 06h
Addressing Register Direct
T States 4
Flags Needed Carry
23 | P a g e
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADC B1 T1 B BBUS, TLOAD
ADC B2 A A+T1+CY ALOAD, SFENB,
ALUSEL2, ALUSEL0,
CTR0
ADC C Add the contents of Register C to the Accumulator with a carry.
Op Code 07h
Addressing Register Direct
T States 4
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADC C1 T1 C CBUS, TLOAD
ADC C2 A A+T1+CY ALOAD, SFENB,
ALUSEL2, ALUSEL0,
CTR0
ADC D Add the contents of Register D to the Accumulator with a carry.
Op Code 08h
Addressing Register Direct
T States 4
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADC D1 T1 D DBUS, TLOAD
ADC D2 A A+T1+CY ALOAD, SFENB,
ALUSEL2, ALUSEL0,
CTR0
24 | P a g e
ADC E Add the contents of Register E to the Accumulator with a carry.
Op Code 09h
Addressing Register Direct
T States 4
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADC E1 T1 E ELOAD, TLOAD
ADC E2 A A+T1+CY ALOAD, SFENB,
ALUSEL2, ALUSEL0,
CTR0
ADCI x The 8-bit data (operand) and the Carry flag are added to the contents of the
Accumulator and the result is stored in the Accumulator.
Op Code 0Ah
Addressing Immediate
T States 4
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADCI x1 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
ADCI x2 A A+T1+CY ALOAD, SFENB,
ALUSEL2, ALUSEL0,
CTR0
ADC M Add the contents of address M to the Accumulator with a carry
Op Code 0Bh
Addressing Indirect
T States 5
Flags Needed Carry
Flags
Affected All
25 | P a g e
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ADC M1 AR[15-8] H, AR[7-0] L
HBUS2, LBUS, ARLOAD
ADC M2 T1 MEM MEMBUS, TLOAD
ADC M3 A A+T1+CY ALOAD, SFENB,
ALUSEL2, ALUSEL0,
CTR0
DAD BC Add the contents of the register pair BC to the contents of register pair HL,
then store in HL register pair
Op Code 0Ch
Addressing Register Direct
T States 8
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DAD BC1 A H HBUS, ALOAD
DAD BC2 T1 B BBUS, TLOAD
DAD BC3 H A+T1 ABUS, HLOAD,
ALUSEL2, ALUSEL0
DAD BC4 A L ALOAD, LBUS
DAD BC5 T1 C CBUS, TLOAD
DAD BC6 L A+T1 ABUS, LLOAD,
ALUSEL2, ALUSEL0,
CTR0
DAD DE Add the contents of the register pair DE to the contents of register pair HL,
then store in HL register pair
Op Code 0Dh
Addressing Register Direct
T States 8
Flags Needed None
Flags
Affected All
Microinstructions per T State:
26 | P a g e
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DAD DE1 A H HBUS, ALOAD
DAD DE2 T1 D DBUS, TLOAD
DAD DE3 H A+T1 ABUS, HLOAD,
ALUSEL2, ALUSEL0
DAD DE4 A L ALOAD, LBUS
DAD DE5 T1 E EBUS, TLOAD
DAD DE6 L A+T1 ABUS, TLOAD,
ALUSEL2, ALUSEL0,
CTR0
DAI M Double Add Immediate the contents of the address pointed by M, then store in
HL register pair
Op Code 0Eh
Addressing Immediate
T States 8
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DAI M1 A H HBUS, ALOAD
DAI M2 T1 MEM, PC PC+1, AR AR+1
MEMBUS, TLOAD,
PCINC, ARINC
DAI M3 H A+T1 ABUS, HLOAD,
ALUSEL2, ALUSEL0
DAI M4 A L LBUS, ALOAD
DAI M5 T MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
DAI M6 L A+T1 ABUS, LLOAD,
ALUSEL2, ALUSEL0,
CTR0
SUB B
Subtracts the contents of Register B to the Accumulator
27 | P a g e
Op Code 0Fh
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SUB B1 T1 B BBUS, TLOAD
SUB B2 T1 -T1 ALUSEL2, ALUSEL1
SUB B3 A A+T1 ALOAD, SUB, CTR0
SUB C Subtracts the contents of Register C to the Accumulator
Op Code 10h
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SUB C1 T1 C CBUS, TLOAD
SUB C2 T1 -T1 ALUSEL2, ALUSEL1
SUB C3 A A+T1 ALOAD, SUB, CTR0
SUB D Subtracts the contents of Register D to the Accumulator
Op Code 11h
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
28 | P a g e
SUB D1 T1 D DBUS, TLOAD
SUB D2 T1 -T1 ALUSEL2, ALUSEL1
SUB D3 A A+T1 ALOAD, SUB, CTR0
SUB E Subtracts the contents of Register E to the Accumulator
Op Code 12h
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SUB E1 T1 E EBUS, TLOAD
SUB E2 T1 -T1 ALUSEL2, ALUSEL1
SUB E3 A A+T1 ALOAD, SUB, CTR0
SUI x The 8-bit data (operand) is subtracted from the contents of the Accumulator
and the result is stored in the Accumulator.
Op Code 13h
Addressing Immediate
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SUI x1 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCIN
SUI x2 T1 -T1 ALUSEL2, ALUSEL1
SUI x3 A A+T1 ALOAD, SUB, CTR0
SUB M Subtracts the contents of the address pointed by M to the Accumulator
Op Code 14h
Addressing Indirect
T States 6
29 | P a g e
Flags Needed None
Flags
Affected
All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SUB M1 AR[15-8] H, AR[7-0] L
HBUS2, LBUS, ARLOAD
SUB M2 T1 MEM MEMBUS, TLOAD
SUB M3 T1 -T1 ALUSEL2, ALUSEL1
SUB M4 A A+T1 ALOAD, SUB, CTR0
SUBB B Subtracts the contents of Register B and the borrow from the Accumulator.
Op Code 15h
Addressing Register Direct
T States 5
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SUBB B1 T1 B BBUS, TLOAD
SUBB B2 T1 -T1 ALUSEL2, ALUSEL1
SUBB B3 A A+T1-CY ALOAD, SFENB, CTR0
SUBB C Subtracts the contents of Register C and the borrow from the Accumulator.
Op Code 16h
Addressing Register Direct
T States 5
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SUBB C1 T1 C CBUS, TLOAD
30 | P a g e
SUBB C2 T1 -T1 ALUSEL2, ALUSEL1
SUBB C3 A A+T1-CY ALOAD, SFENB, CTR0
SUBB D Subtracts the contents of Register D and the borrow from the Accumulator.
Op Code 17h
Addressing Register Direct
T States 5
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SUBB D1 T1 D DBUS, TLOAD
SUBB D2 T1 -T1 ALUSEL2, ALUSEL1
SUBB D3 A A+T1-CY ALOAD, SFENB, CTR0
SUBB E Subtracts the contents of Register E and the borrow from the Accumulator.
Op Code 18h
Addressing Register Direct
T States 5
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SUBB E1 T1 E EBUS, TLOAD
SUBB E2 T1 -T1 ALUSEL2, ALUSEL1
SUBB E3 A A+T1-CY ALOAD, SFENB, CTR0
SCI x The 8-bit data (operand) and the Borrow flag are subtracted from the contents
of the accumlator and the result is stored in the accumulator
Op Code 19h
Addressing Immediate
T States 5
Flags Needed Carry
Flags All
31 | P a g e
Affected
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SCI x1 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
SCI x2 T1 -T1 ALUSEL2, ALUSEL1
SCI x3 A A+T1-CY ALOAD, SFENB, CTR0
SCN M Subtract the contents of address M to the Accumulator with a borrow
Op Code 1Ah
Addressing Indirect
T States 6
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SCN M1 AR[15-8] H, AR[7-0] L
HBUS2, LBUS, ARLOAD
SCN M2 T1 MEM MEMBUS, TLOAD
SCN M3 T1 -T1 ALUSEL2, ALUSEL1
SCN M4 A A+T1-CY ALOAD, SFENB, CTR0
DSUB BC Subtract the contents of the register pair BC to the contents of register pair HL,
then store in HL register pair
Op Code 1Bh
Addressing Register Direct
T States 10
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DSUB BC1 A H HBUS, ALOAD
32 | P a g e
DSUB BC2 T1 B BBUS, TLOAD
DSUB BC3 T1 -T1 ALUSEL2, ALUSEL1
DSUB BC4 H A+T1 HLOAD, ABUS,
ALUSEL2, ALUSEL0
DSUB BC5 A L ALOAD, LBUS
DSUB BC6 T1 C CBUS, TLOAD
DSUB BC7 T1 -T1 ALUSEL2, ALUSEL1
DSUB BC8 L A+T1-CY LLOAD, ABUS, SFENB,
CTR0
DSUB DE Subtract the contents of the register pair DE to the contents of register pair HL,
then store in HL register pair
Op Code 1Ch
Addressing Register Direct
T States 10
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DSUB DE1 A H HBUS, ALOAD
DSUB DE2 T1 D DBUS, TLOAD
DSUB DE3 T1 -T1 ALUSEL2, ALUSEL1
DSUB DE4 H A+T1 ABUS, HLOAD
DSUB DE5 A L LBUS, ALOAD
DSUB DE6 T1 E EBUS, TLOAD
DSUB DE7 T1 -T1 ALUSEL2, ALUSEL1
DSUB DE8 L A+T1-CY ABUS, LLOAD, SFENB,
CTR0
DSUBI M Double Subtract Immediate the contents of the address pointed by M, then
store in HL register pair
Op Code 1Dh
Addressing Immediate
T States 10
Flags Needed None
Flags
Affected All
Microinstructions per T State:
33 | P a g e
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DSUBI M1 A H HBUS, ALOAD
DSUBI M2 T1 MEM, PC PC+1, AR AR+1
MEMBUS, TLOAD,
PCINC, ARINC
DSUBI M3 T1 -T1 ALUSEL2, ALUSEL1
DSUBI M4 H A+T1 ABUS, HLOAD
DSUBI M5 A L LBUS, ALOAD
DSUBI M6 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
DSUBI M7 T1 -T1 ALUSEL2, ALUSEL1
DSUBI M8 L A+T1-CY ABUS, LLOAD, SFENB,
CTR0
BADD B BCD Addition of the contents of Register B to the Accumulator
Op Code 1Eh
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BADD B1 T1 B BBUS, TLOAD
BADD B2 A A+T1 ALOAD, ALUSEL2,
ALUSEL0, BCDSEL,
CTR0
BADD C BCD Addition of the contents of Register C to the Accumulator
Op Code 1Fh
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
34 | P a g e
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BADD C1 T1 C CBUS, TLOAD
BADD C2 A A+T1 ALOAD, ALUSEL2,
ALUSEL0, BCDSEL,
CTR0
BADD D BCD Addition of the contents of Register D to the Accumulator
Op Code 20h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BADD D1 T1 D DBUS, TLOAD
BADD D2 A A+T1 ALOAD, ALUSEL2,
ALUSEL0, BCDSEL,
CTR0
BADD E BCD Addition of the contents of Register E to the Accumulator
Op Code 21h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BADD E1 T1 E EBUS, TLOAD
BADD E2 A A+T1 ALOAD, ALUSEL2,
ALUSEL0, BCDSEL,
CTR0
BADI x BCD Addition of the 8-bit data (operand) to the contents of the Accumulator
and the result is stored in the Accumulator.
Op Code 22h
35 | P a g e
Addressing Immediate
T States 4
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BADI x1 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
BADI x2 A A+T1 ALOAD, ALUSEL2,
ALUSEL0, BCDSEL,
CTR0
BADDN M BCD Addition of the contents of the address pointed by M to the Accumulator
Op Code 23h
Addressing Indirect
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BADDN M1 AR[15-8] H, AR[7-0] L
HBUS2, LBUS, ARLOAD
BADDN M2 T1 MEM MEMBUS, TLOAD
BADDN M3 A A+T1 ALOAD, ALUSEL2,
ALUSEL0, BCDSEL,
CTR0
BADC B BCD Addition of the contents of Register B to the Accumulator with a carry.
Op Code 24h
Addressing Register Direct
T States 4
Flags Needed Carry
Flags
Affected All
36 | P a g e
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BADC B1 T1 B BBUS, TLOAD
BADC B2 A A+T1+CY ALOAD, ALUSEL2,
ALUSEL0, SFENB,
BCDSEL, CTR0
BADC C
BCD Addition of the contents of Register C to the Accumulator with a carry.
Op Code 25h
Addressing Register Direct
T States 4
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BADC C1 T1 C CBUS, TLOAD
BADC C2 A A+T1+CY ALOAD, ALUSEL2,
ALUSEL0, SFENB,
BCDSEL, CTR0
BADC D BCD Addition of the contents of Register D to the Accumulator with a carry.
Op Code 26h
Addressing Register Direct
T States 4
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
37 | P a g e
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BADC D1 T1 D DBUS, TLOAD
BADC D2 A A+T1+CY ALOAD, ALUSEL2,
ALUSEL0, SFENB,
BCDSEL
BADC E BCD Addition of the contents of Register E to the Accumulator with a carry.
Op Code 27h
Addressing Register Direct
T States 4
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BADC E1 T1 E EBUS, TLOAD
BADC E2 A A+T1+CY ALOAD, ALUSEL2,
ALUSEL0, SFENB,
BCDSEL, CTR0
BADCI x BCD Addition of the 8-bit data (operand) and the Carry flag to the contents of
the Accumulator and the result is stored in the Accumulator.
Op Code 28h
Addressing Immediate
T States 4
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BADCI x1 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
BADCI x2 A A+T1+CY ALOAD, ALUSEL2,
ALUSEL0, SFENB,
BCDSEL, CTR0
38 | P a g e
BACN M BCD Addition of the contents of address M to the Accumulator with a carry
Op Code 29h
Addressing Indirect
T States 5
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BACN M1 AR[15-8] H, AR[7-0] L
HBUS2, LBUS, ARLOAD
BACN M2 T1 MEM MEMBUS, TLOAD
BACN M3 A A+T1+CY ALOAD, ALUSEL2,
ALUSEL0, SFENB,
BCDSEL, CTR0
BDAD BC BCD Addition of the contents of the register pair BC to the contents of register
pair HL, then store in HL register pair
Op Code 2Ah
Addressing Register Direct
T States 8
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BDAD BC1 A H ALOAD, LBUS
BDAD BC2 T1 B BBUS, TLOAD
BDAD BC3 H A+T1 HLOAD, ALUSEL2,
ALUSEL0
BDAD BC4 A L ALOAD, LBUS
BDAD BC5 T1 C TLOAD, CBUS
BDAD BC6 L A+T1 LLOAD, ALUSEL2,
ALUSEL0, BCDSEL,
CTR0
BDAD DE BCD Addition of the contents of the register pair DE to the contents of register
pair HL, then store in HL register pair
39 | P a g e
Op Code 2Bh
Addressing Register Direct
T States 8
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BDAD DE1 A H HBUS, ALOAD
BDAD DE2 T1 D DBUS, TLOAD
BDAD DE3 H A+T1 HLOAD, ALUSEL2,
ALUSEL0
BDAD DE4 A L LBUS, ALOAD
BDAD DE5 T1 E EBUS, TLOAD
BDAD DE6 L A+T1 LLOAD, ALUSEL2,
ALUSEL0, BCDSEL,
CTR0
BDADI M BCD Double Add Immediate the contents of the address pointed by M, then
store in HL register pair
Op Code 2Ch
Addressing Immediate
T States 8
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BDADI M1 A H HBUS, ALOAD
BDADI M2 T1 MEM, PC PC+1, AR AR+1
MEMBUS, TLOAD,
PCINC, ARINC
BDADI M3 H A+T1 HLOAD, ALUSEL2,
ALUSEL0
BDADI M4 A L LBUS, ALOAD
BDADI M5 T1 MEM, PC PC+1 TLOAD, MEMBUS,
PCIN
BDADI M6 L A+T1 LLOAD, ALUSEL2,
ALUSEL0, BCDSEL,
40 | P a g e
CTR0
BSUB B BCD Subtraction of the contents of Register B to the Accumulator
Op Code 2Dh
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSUB B1 T1 B BBUS, TLOAD
BSUB B2 T1 -T1 ALUSEL2, ALUSEL1
BSUB B3 A A+T1 ALOAD, BCDSEL, CTR0
BSUB C BCD Subtraction of the contents of Register C to the Accumulator
Op Code 2Eh
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSUB C1 T1 C CBUS, TLOAD
BSUB C2 T1 -T1 ALUSEL2, ALUSEL1
BSUB C3 A A+T1 ALOAD, BCDSEL, CTR0
BSUB D BCD Subtraction of the contents of Register D to the Accumulator
Op Code 2Fh
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
41 | P a g e
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSUB D1 T1 D DBUS, TLOAD
BSUB D2 T1 -T1 ALUSEL2, ALUSEL1
BSUB D3 A A+T1 ALOAD, BCDSEL, CTR0
BSUB E BCD Subtraction of the contents of Register E to the Accumulator
Op Code 30h
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSUB E1 T1 E EBUS, TLOAD
BSUB E2 T1 -T1 ALUSEL2, ALUSEL1
BSUB E3 A A+T1 ALOAD, BCDSEL, CTR0
BSUI x BCD Subtraction of the 8-bit data (operand) from the contents of the
Accumulator and the result is stored in the Accumulator
Op Code 31h
Addressing Indirect
T States 5
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSUI x1 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
BSUI x2 T1 -T1 ALUSEL2, ALUSEL1
BSUI x3 A A+T1 ALOAD, BCDSEL, CTR0
BSUN M BCD Subtraction of the contents of the address pointed by M to the
Accumulator
42 | P a g e
Op Code 32h
Addressing Register Direct
T States 5
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSUN M1 AR[15-8] H, AR[7-0] L
HBUS2, LBUS, ARLOAD
BSUN M2 T1 MEM MEMBUS, TLOAD
BSUN M3 T1 -T1 ALUSEL2, ALUSEL1
BSUN M4 A A+T1 ALOAD, BCDSEL, CTR0
BSUBB B BCD Subtraction of the contents of Register B and the borrow from the
Accumulator.
Op Code 33h
Addressing Register Direct
T States 5
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSUBB B1 T1 B BBUS, TLOAD
BSUBB B2 T1 -T1 ALUSEL2, ALUSEL1
BSUBB B3 A A+T1-CY ALOAD, SFENB,
BCDSEL, CTR0
BSUBB C BCD Subtraction of the contents of Register C and the borrow from the
Accumulator.
Op Code 34h
Addressing Register Direct
T States 5
Flags Needed Carry
Flags
Affected All
43 | P a g e
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSUBB C1 T1 C CBUS, TLOAD
BSUBB C2 T1 -T1 ALUSEL2, ALUSEL1
BSUBB C3 A A+T1-CY ALOAD, SFENB,
BCDSEL, CTR0
BSUBB D BCD Subtraction of the contents of Register D and the borrow from the
Accumulator.
Op Code 35h
Addressing Register Direct
T States 5
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSUBB D1 T1 D DBUS, TLOAD
BSUBB D2 T1 -T1 ALUSEL2, ALUSEL1
BSUBB D3 A A+T1-CY ALOAD, SFENB,
BCDSEL, CTR0
BSUBB E BCD Subtraction of the contents of Register e and the borrow from the
Accumulator.
Op Code 36h
Addressing Register Direct
T States 5
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSUBB E1 T1 E EBUS, TLOAD
BSUBB E2 T1 -T1 ALUSEL2, ALUSEL1
BSUBB E3 A A+T1-CY ALOAD, SFENB,
44 | P a g e
BCDSEL, CTR0
BSCI x BCD Subtraction of the 8-bit data (operand) and the Borrow flag from the
contents of the Accumulator and the result is stored in the Accumulator.
Op Code 37h
Addressing Immediate
T States 5
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSCI x1 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
BSCI x2 T1 -T1 ALUSEL2, ALUSEL1
BSCI x3 A A+T1-CY ALOAD, SFENB,
BCDSEL, CTR0
BSCN M BCD Subtraction of the contents of address M to the Accumulator with a
borrow
Op Code 38h
Addressing Immediate
T States 5
Flags Needed Carry
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BSCN M1 AR[15-8] H, AR[7-0] L
HBUS2, LBUS, ARLOAD
BSCN M2 T1 MEM MEMBUS, TLOAD
BSCN M3 T1 -T1 ALUSEL2, ALUSEL1
BSCN M4 A A+T1-CY ALOAD, SFENB,
BCDSEL, CTR0
BCSUB BC BCD Subtraction of the contents of the register pair BC to the contents of
register pair HL, then store in HL register pair
45 | P a g e
Op Code 39h
Addressing Register Direct
T States 10
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BCSUB BC1 A H HBUS, ALOAD
BCSUB BC2 T1 B TLOAD, BBUS
BCSUB BC3 T1 -T1 ALUSEL2, ALUSEL1
BCSUB BC4 H A+T1 HLOAD
BCSUB BC5 A L ALOAD, LBUS
BCSUB BC6 T1 C CBUS, TLOAD
BCSUB BC7 T1 -T1 ALUSEL2, ALUSEL1
BCSUB BC8 L A+T1-CY LBUS, SFENB, BCDSEL,
CTR0
BCSUB DE BCD Subtraction of the contents of the register pair DE to the contents of
register pair HL, then store in HL register pair
Op Code 3Ah
Addressing Register Direct
T States 10
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
46 | P a g e
BCSUB DE1 A H HBUS, ALOAD
BCSUB DE2 T1 D DBUS, TLOAD
BCSUB DE3 T1 -T1 ALUSEL2, ALUSEL1
BCSUB DE4 H A+T1 HLOAD
BCSUB DE5 A L LBUS, ALOAD
BCSUB DE6 T1 E EBUS, TLOAD
BCSUB DE7 T1 -T1 ALUSEL2, ALUSEL1
BCSUB DE8 L A+T1-CY LLOAD, SFENB,
BCDSEL, CTR0
BCSUBI M BCD Double Subtract Immediate the contents of the address pointed by M,
then store in HL register pair
Op Code 3Bh
Addressing Immediate
T States 10
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BCSUBI M1 A H HBUS, ALOAD
BCSUBI M2 T1 MEM, PC PC+1, AR AR+1
MEMBUS, TLOAD,
PCINC, ARINC
BCSUBI M3 T1 -T1 ALUSEL2, ALUSEL1
BCSUBI M4 H A+T1 HLOAD
BCSUBI M5 A L LBUS, ALOAD
47 | P a g e
BCSUBI M6 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
BCSUBI M7 T1 -T1 ALUSEL2, ALUSEL1
BCSUBI M8 L A+T1-CY LLOAD, SFENB,
BCDSEL, CTR0
DEC B Decrements the contents of register B
Op Code 3Ch
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DEC B1 T1 A ABUS, TLOAD
DEC B2 A B BBUS, ALOAD
DEC B3 B A-1 BLOAD, ALUSEL2
DEC B4 A T1 TBUS, ALOAD, CTR0
DEC C Decrements the contents of register C
Op Code 3Dh
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DEC C1 T1 A ABUS, TLOAD
DEC C2 A C CBUS, ALOAD
DEC C3 C A-1 CLOAD, ALUSEL2
DEC C4 A T1 TBUS, ALOAD, CTR0
DEC D Decrements the contents of register D
48 | P a g e
Op Code 3Eh
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DEC D1 T1 A ABUS, TLOAD
DEC D2 A D DBUS, ALOAD
DEC D3 D A-1 DLOAD, ALUSEL2
DEC D4 A T1 TBUS, ALOAD, CTR0
DEC E Decrements the contents of register E
Op Code 3Fh
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DEC E1 T1 A ABUS, TLOAD
DEC E2 A E EBUS, ALOAD
DEC E3 E A-1 ELOAD, ALUSEL2
DEC E4 A T1 TBUS, ALOAD, CTR0
INC B Increments the contents of register B
Op Code 40h
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
49 | P a g e
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
INC B1 T1 A ABUS, TLOAD
INC B2 A B BBUS, ALOAD
INC B3 B A+1 BLOAD, ALUSEL2,
ALUSEL1, ALUSEL0
INC B4 A T1 TBUS, ALOAD, CTR0
INC C Increments the contents of register C
Op Code 41h
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
INC C1 T1 A ABUS, TLOAD
INC C2 A C CBUS, ALOAD
INC C3 C A+1 CLOAD, ALUSEL2,
ALUSEL1, ALUSEL0
INC C4 A T1 ALOAD, TBUS, CTR0
INC D Increments the contents of register D
Op Code 42h
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
INC D1 T1 A ABUS, TLOAD
INC D2 A D DBUS, TLOAD
INC D3 D A+1 DLOAD, ALUSEL2,
ALUSEL1, ALUSEL0
50 | P a g e
INC D4 A T1 TBUS, ALOAD, CTR0
INC E Increments the contents of register E
Op Code 43h
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
INC E1 T1 A ABUS, TLOAD
INC E2 A E EBUS, TLOAD
INC E3 E A+1 ELOAD, ALUSEL2,
ALUSEL1, ALUSEL0
INC E4 A T1 TBUS, ALOAD, CTR0
DEC A Decrements the contents of the Accumulator
Op Code 44h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DEC A1 A A-1 ALOAD, ALUSEL2,
CTR0
INC A Increments the contents of the Accumulator
Op Code 45h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected All
Microinstructions per T State:
51 | P a g e
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
INC A1 A A+1 ALOAD, ALUSEL2,
ALUSEL1, ALUSEL0,
CTR0
DECR HL Decrements the content of the extended register HL
Op Code 46h
Addressing Register Direct
T States 8
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
DECR HL1 T1 A ABUS, TLOAD
DECR HL2 A L LBUS, ALOAD
DECR HL3 L A-1 LLOAD, ALUSEL2
DECR HL4 A H HBUS, ALOAD
DECR HL5 H A-CY HLOAD, ABUS, SFENB
DECR HL6 A T1 TBUS, ALOAD, CTR0
INCR HL Increments the content of the extended register HL
Op Code 47h
Addressing Register Direct
T States 8
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
INCR HL1 T1 A ABUS, TLOAD
INCR HL2 A L LBUS, ALOAD
INCR HL3 L A+1 LLOAD, ALUSEL2,
ALUSEL1, ALUSEL0
INCR HL4 A H HBUS, ALOAD
52 | P a g e
INCR HL5 H A+CY HLOAD, ABUS, SFENB
INCR HL6 A T1 TBUS, ALOAD, CTR0
BDEC B BCD Decrement the contents of Register B
Op Code 48h
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BDEC B1 T1 A ABUS, TLOAD
BDEC B2 A B BBUS, ALOAD
BDEC B3 B A-1 BLOAD, ALUSEL2
BDEC B4 A T1 ALOAD, TLOAD, CTR0
BDEC C BCD Decrement the contents of Register C
Op Code 49h
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BDEC C1 T1 A ABUS, TLOAD
BDEC C2 A C CBUS, ALOAD
BDEC C3 C A-1 CLOAD, ALUSEL2
BDEC C4 A T1 TLOAD, ABUS, CTR0
BDEC D BCD Decrement the contents of Register D
Op Code 4Ah
Addressing Register Direct
T States 6
Flags Needed None
53 | P a g e
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BDEC D1 T1 A ABUS, TLOAD
BDEC D2 A D DBUS, ALOAD
BDEC D3 D A-1 DLOAD, ALUSEL2
BDEC D4 A T1 TBUS, ALOAD, CTR0
BDEC E BCD Decrement the contents of Register E
Op Code 4Bh
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BDEC E1 T1 A ABUS, TLOAD
BDEC E2 A E EBUS, ALOAD
BDEC E3 E A-1 ELOAD, ALUSEL2
BDEC E4 A T1 TBUS, ALOAD, CTR0
BINC B BCD Increment the contents of Register B
Op Code 4Ch
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BINC B1 T1 A ABUS, TLOAD
BINC B2 A B BBUS, ALOAD
54 | P a g e
BINC B3 B A+1 BLOAD, ALUSEL2,
ALUSEL1, ALUSEL0
BINC B4 A T1 TBUS, ALOAD, CTR0
BINC C BCD Increment the contents of Register C
Op Code 4Dh
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BINC C1 T1 A ABUS, TLOAD
BINC C2 A C CBUS, ALOAD
BINC C3 C A+1 CLOAD, ALUSEL2,
ALUSEL1, ALUSEL0
BINC C4 A T1 TBUS, ALOAD, CTR0
BINC D BCD Increment the contents of Register D
Op Code 4Eh
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BINC D1 T1 A ABUS, TLOAD
BINC D2 A D DBUS, ALOAD
BINC D3 D A+1 DLOAD, ALUSEL2,
ALUSEL1, ALUSEL0
BINC D4 A T1 TBUS, ALOAD, CTR0
BINC E BCD Increment the contents of Register E
Op Code 4Fh
55 | P a g e
Addressing Register Direct
T States 6
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BINC E1 T1 A ABUS, TLOAD
BINC E2 A E EBUS, ALOAD
BINC E3 E A+1 ELOAD, ALUSEL2,
ALUSEL1, ALUSEL0
BINC E4 A T1 ALOAD, TBUS, CTR0
BDEC A BCD Decrement the contents of the Accumulator
Op Code 50h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
BDEC A1 A A-1 ALOAD, ALUSEL2,
CTR0
BINC A BCD Increment the contents of the Accumulator
Op Code 51h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected All
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
56 | P a g e
BINC A1 A A+1 ALOAD, ALUSEL2,
ALUSEL1, ALUSEL0,
CTR0
SHL A Shift the contents of the Accumulator to the left
Op Code 52h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected Sign, Zero, Overflowm Implied
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SHL A1 A SHL(A) ALOAD, SHL, CTR0
SHR A Shift the contents of the Accumulator to the right
Op Code 53h
Addressing Implied
T States 3
Flags Needed None
Flags
Affected Sign, Zero, Overflow
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
SHR A1 A SHR(A) ALOAD, SHR, CTR0
AND B Performs the AND operation to the Accumulator and the contents of register B
Op Code 54h
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
57 | P a g e
AND B1 T1 B BBUS, TLOAD
AND B2 A A^T1 ALOAD, ALUSEL0,
CTR0
AND C Performs the AND operation to the Accumulator and the contents of register C
Op Code 55h
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
AND C1 T1 C CBUS, TLOAD
AND C2 A A^T1 ALOAD, ALUSEL0,
CTR0
AND D Performs the AND operation to the Accumulator and the contents of register D
Op Code 56h
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
AND D1 T1 D DBUS, TLOAD
AND D2 A A^T1 ALOAD, ALUSEL0,
CTR0
AND E Performs the AND operation to the Accumulator and the contents of register E
Op Code 57h
Addressing Register Direct
T States 5
Flags Needed None
Flags
Affected Sign, Zero
58 | P a g e
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
AND E1 T1 E EBUS, TLOAD
AND E2 A A^T1 ALOAD, ALUSEL0,
CTR0
ANDI x AND Immediate x with A
Op Code 58h
Addressing Immediate
T States 5
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ANDI x1 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
ANDI x2 A A^T1 ALOAD, ALUSEL0,
CTR0
ANDA M Performs the AND operation of the Accumulator and the address pointed by M
Op Code 59h
Addressing Indirect
T States 5
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ANDA M1 AR[15-8] H, AR[7-0] L
HBUS2, LBUS, ARLOAD
ANDA M2 T1 MEM MEMBUS, TLOAD
ANDA M3 A A^T1 ALOAD, ALUSEL0,
CTR0
59 | P a g e
OR B Performs the OR operation to the Accumulator and the contents of register B
Op Code 5Ah
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
OR B1 T1 B BBUS, TLOAD
OR B2 A A v T1 ALOAD, ALUSEL1,
ALUSEL0, CTR0
OR C Performs the OR operation to the Accumulator and the contents of register C
Op Code 5Bh
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
OR C1 T1 C CBUS, TLOAD
OR C2 A A v T1 ALOAD, ALUSEL1,
ALUSEL0, CTR0
OR D Performs the OR operation to the Accumulator and the contents of register D
Op Code 5Ch
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
60 | P a g e
OR D1 T1 D DBUS, TLOAD
OR D2 A A v T1 ALOAD, ALUSEL1,
ALUSEL0, CTR0
OR E Performs the OR operation to the Accumulator and the contents of register E
Op Code 5Dh
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
OR E1 T1 E EBUS, TLOAD
OR E2 A A v T1 ALOAD, ALUSEL1,
ALUSEL0, CTR0
ORI x OR Immediate x with A
Op Code 5Eh
Addressing Immediate
T States 4
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ORI x1 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
ORI x2 A A v T1 ALOAD, ALUSEL1,
ALUSEL0, CTR0
ORA M Performs the OR operation of the Accumulator and the address pointed by M
Op Code 5Fh
Addressing Indirect
T States 5
Flags Needed None
Flags Sign, Zero
61 | P a g e
Affected
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
ORA M1 AR[15-8] H, AR[7-0] L
ARLOAD, HBUS2, LBUS
ORA M2 T1 MEM MEMBUS, TLOAD
ORA M3 A A v T1 ALOAD, ALUSEL1,
ALUSEL0, CTR0
XOR B Performs the EXCLUSIVE OR operation to the Accumulator and the contents
of register B
Op Code 60h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
XOR B1 T1 B BBUS, TLOAD
XOR B2 A AT1 ALOAD, ALUSEL1,
CTR0
XOR C Performs the EXCLUSIVE OR operation to the Accumulator and the contents
of register C
Op Code 61h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
XOR C1 T1 C CBUS, TLOAD
XOR C2 A AT1 ALOAD, ALUSEL1,
62 | P a g e
CTR0
XOR D Performs the EXCLUSIVE OR operation to the Accumulator and the contents
of register D
Op Code 62h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
XOR D1 T1 D DBUS, TLOAD
XOR D2 A AT1 ALOAD, ALUSEL1,
CTR0
XOR E Performs the EXCLUSIVE OR operation to the Accumulator and the contents
of register E
Op Code 63h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
XOR E1 T1 E EBUS, TLOAD
XOR E2 A AT1 ALOAD, ALUSEL1,
CTR0
XORI x EXCLUSIVELY OR Immediate x with A
Op Code 64h
Addressing Immediate
T States 4
Flags Needed None
Flags
Affected Sign, Zero
63 | P a g e
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
XORI x1 T1 MEM, PC PC+1 MEMBUS, TLOAD,
PCINC
XORI x2 A AT1 ALOAD, ALUSEL1,
CTR0
XORA M Performs the EXCLUSIVE OR operation of the Accumulator and the address
pointed by M
Op Code 65h
Addressing Indirect
T States 5
Flags Needed None
Flags
Affected Sign, Zero
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
XORA M1 AR[15-8] H, AR[7-0] L
HBUS2, LBUS, ARLOAD
XORA M2 T1 MEM MEMBUS, TLOAD
XORA M3 A AT1 ALOAD, ALUSEL1,
CTR0
NOT A Complements the contents of the Accumulator
Op Code 66h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
NOT A1 A A ALOAD, CTR0
NOT B Complements the contents of the Register B
64 | P a g e
Op Code 67h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
NOT B1 T1 B BBUS, TLOAD
NOT B2 B T1 BLOAD, CTR0
NOT C Complements the contents of the Register C
Op Code 68h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
NOT C1 T1 C CBUS, TLOAD
NOT C2 C T1 CLOAD, CTR0
NOT D Complements the contents of the Register D
Op Code 69h
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
NOT D1 T1 D DBUS, TLOAD
NOT D2 D T1 DLOAD, CTR0
65 | P a g e
NOT E Complements the contents of the Register E
Op Code 6Ah
Addressing Register Direct
T States 4
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
NOT E1 T1 E EBUS, TLOAD
NOT E2 E T1 ELOAD, CTR0
IOP1 x Determines whether port 1 is input or output
Op Code 6Bh
Addressing Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
IOP1 x1 IOP1 MEM, PC PC+1
MEMBUS, IOP1LOAD,
PCINC, CTR0
IOP2 x Determines whether port 2 is input or output
Op Code 6Ch
Addressing Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
66 | P a g e
IOP2 x1 IOP2 MEM, PC PC+1 MEMBUS, IOP2LOAD,
PCINC, CTR0
OUT IOP1 Contents of the Accumulator are sent to the output port 1
Op Code 6Dh
Addressing Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
OUT IOP1 1 IOP1 A ABUS, IOP1LOAD,
CTR0
OUT IOP2 Contents of the Accumulator are sent to the output port 2
Op Code 6Eh
Addressing Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
OUT IOP2 1 IOP2 A ABUS, IOP2LOAD,
CTR0
IN IOP1 Contents of the input port 1 are sent to the Accumulator
Op Code 6Fh
Addressing Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
67 | P a g e
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
IN IOP1 1 A IOP1 IOP1BUS, ALOAD,
CTR0
IN IOP2 Contents of the input port 2 are sent to the Accumulator
Op Code 70h
Addressing Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
IN IOP2 1 A IOP2 IOP2BUS, ALOAD,
CTR0
MOV A, B Move the contents of B to A
Op Code 71h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
MOV A, B1 A B BBUS, ALOAD, CTR0
MOV A, C Move the contents of C to A
Op Code 72h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
68 | P a g e
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
MOV A, C1 A C CBUS, ALOAD, CTR0
MOV A, D Move the contents of D to A
Op Code 73h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
MOV A, D1 A D DBUS, ALOAD, CTR0
MOV A, E Move the contents of E to A
Op Code 74h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
MOV A, E1 A E EBUS, ALOAD, CTR0
MOV B, A Move the contents of A to B
Op Code 75h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected None
69 | P a g e
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
MOV B, A1 B A ABUS, BLOAD, CTR0
MOV B, C Move the contents of C to B
Op Code 76h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
MOV B, C1 B C CBUS, BLOAD, CTR0
MOV B, D Move the contents of D to B
Op Code 77h
Addressing Register Direct
T States 3
Flags Needed None
Flags
Affected None
Microinstructions per T State:
FETCH1 ARPC PCBUS, ARLOAD
FETCH2 IR[70]MEM[158], PCPC+1
MEMBUS2, PCINC,
IRLOAD
MOV B, D1 B D DBUS, BLOAD, CTR0
MOV B, E Move the contents of E to B
Op Code 78h
Addressing Register Direct
T States 3
Flags Needed None
70 | P a g e
Flags
Affected None
Microinstr